The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.
Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
prompt "Mainboard vendor"
default VENDOR_EMULATION
+config VENDOR_AAEON
+ bool "Aaeon"
config VENDOR_ABIT
bool "Abit"
config VENDOR_ADVANSUS
endchoice
source "src/mainboard/a-trend/Kconfig"
+source "src/mainboard/aaeon/Kconfig"
source "src/mainboard/abit/Kconfig"
source "src/mainboard/advansus/Kconfig"
source "src/mainboard/advantech/Kconfig"
--- /dev/null
+if VENDOR_AAEON
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_AAEON_PFM_540I_REVB
+ bool "PFM-540I_REVB"
+
+endchoice
+
+source "src/mainboard/aaeon/pfm-540i_revb/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Aaeon"
+
+endif # VENDOR_AAEON
--- /dev/null
+if BOARD_AAEON_PFM_540I_REVB
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_SMSC_SMSCSUPERIO
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_1024
+ select POWER_BUTTON_FORCE_ENABLE
+
+config MAINBOARD_DIR
+ string
+ default aaeon/pfm-540i_revb
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "PFM-540I_REVB"
+
+config IRQ_SLOT_COUNT
+ int
+ default 4
+
+endif # BOARD_AAEON_PFM_540I_REVB
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
--- /dev/null
+chip northbridge/amd/lx
+ device pci_domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ device pci 1.2 on end # AES
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x0000105a"
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "1" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3E8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2E8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci c.0 on end # ISA Bridge (PC104)
+ device pci e.0 on end # Ethernet
+ device pci f.0 on # ISA Bridge
+ chip superio/smsc/smscsuperio
+ device pnp 4e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 4e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 4e.7 on # Keyboard
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 4e.a off end # Runtime/ACPI
+
+ # superio/smsc/smscsuperio currently only supports the first 2 serial ports.
+ device pnp 4e.b off # Com3
+ io 0x60 = 0x3e8
+ irq 0x70 = 10
+ end
+ device pnp 4e.c off # Com4
+ io 0x60 = 0x2e8
+ irq 0x70 = 11
+ end
+ end
+ end
+ device pci f.2 on end # IDE Controller
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device lapic_cluster 0 on
+ chip cpu/amd/model_lx
+ device lapic 0 on end
+ end
+ end
+end
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on irq_tables.c from AMD's DB800 mainboard. */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 5
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 9
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ /* CPU */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+ /* Ethernet */
+ {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+ /* Chipset */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include "chip.h"
+
+static void init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "AAEON PFM-540I_REVB ENTER %s\n", __func__);
+ printk(BIOS_DEBUG, "AAEON PFM-540I_REVB EXIT %s\n", __func__);
+}
+
+static void enable_dev(struct device *dev)
+{
+ dev->ops->init = init;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("AAEON PFM-540I_REVB Mainboard")
+ .enable_dev = enable_dev,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Based on romstage.c from AMD's DB800 mainboard. */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+ if (device != DIMM0)
+ return 0xFF; /* No DIMM1, don't even try. */
+
+ return smbus_read_byte(device, address);
+}
+
+#define ManualConf 0 /* Do automatic strapped PLL config */
+#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
+#define PLLMSRlo 0x00DE60EE
+
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
+
+void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* Note: must do this AFTER the early_setup! It is counting on some
+ * early MSR setup for CS5536.
+ */
+ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset(ManualConf);
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+}
#define A8000 0x77 /* ASUS A8000, a rebranded DME1737(?) */
#define DME1737 0x78
#define SCH3112 0x7c
+#define SCH3114 0x7d
#define SCH5307 0x81 /* Rebranded LPC47B397(?) */
#define SCH5027D 0x89
#define SCH4304 0x90 /* SCH4304, SCH4307 */
{A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
+ {SCH3114, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}},
{SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, 11}},
{SCH4304, {0, 3, 4, 5, -1, 7, -1, 11, -1, -1, -1, -1, 10, -1, -1}},
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