Rudolf Marek [Sat, 26 Feb 2011 19:46:08 +0000 (19:46 +0000)]
Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sat, 26 Feb 2011 18:42:04 +0000 (18:42 +0000)]
Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sat, 26 Feb 2011 17:49:49 +0000 (17:49 +0000)]
Add support for the ASRock E350M1, an AMD family 14h Fusion board.
A video option rom must be added for UMA graphics support. It can
be extracted from the supplied UEFI BIOS.
ASRock E350M1 support is based on the AMD persimmon project. The
major differences are SIO model and DIMM SDP addressing. With this
coreboot and seabios, the board can boot DOS from a SATA drive and
can boot WinPE from a USB flash drive. I was unable to get
Windows setup to run.
The board has a socketed SPI flash BIOS chip and a serial port
header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
Winbond w83627hf is a good enough match to get the serial port
and keyboard working.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sat, 26 Feb 2011 13:34:01 +0000 (13:34 +0000)]
It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by: Rudolf Marek <r.marek@asssembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Thu, 24 Feb 2011 14:35:42 +0000 (14:35 +0000)]
Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
This affects the CMOS options iommu, ECC_memory, max_mem_clock,
hw_scrubber, interleave_chip_selects.
If they're absent in cmos.layout, a Kconfig value is used if it exists,
or a hardcoded default otherwise.
[Patrick: I changed the ramstage CMOS handling a bit, and dropped the
reliance of hw_scrubber on ECC RAM, as it has nothing to do with it -
it's the cache that's being scrubbed here.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Thu, 24 Feb 2011 13:54:10 +0000 (13:54 +0000)]
Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600
coreboot used to set the chipset to IDE mode unconditionally.
Now, the user has a couple of ways to choose the configuration:
- If a CMOS variable sata_mode exist, it is used to decide if IDE or
AHCI is to be used as interface.
- If not, a Kconfig option is used.
- If unchanged, the Kconfig option is set to IDE.
So unless the cmos.layout is extended or Kconfig is modified, this won't
change behaviour.
[Patrick: Compared to Josef's version, I changed the Kconfig option to
be boolean, instead of a magic string. Also, the "IDE" default is
handled in Kconfig, instead of an additional line of code.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 24 Feb 2011 07:43:37 +0000 (07:43 +0000)]
Tyan/s2735 doesn't need to define its own hard_reset function anymore.
The southbridge already provides hard_reset.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6378
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 24 Feb 2011 07:18:11 +0000 (07:18 +0000)]
libpayload: Move stdin/stdout/stderr away from headers
Otherwise they exist in several object files, confusing the linker
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6377
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Thu, 24 Feb 2011 05:00:33 +0000 (05:00 +0000)]
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 22 Feb 2011 14:35:05 +0000 (14:35 +0000)]
Move coreboot specific rules and setup to toplevel Makefile.inc
KERNELVERSION issue found by Stefan is fixed.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6375
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Mon, 21 Feb 2011 09:39:17 +0000 (09:39 +0000)]
[i945] Add SPD adress mapping
The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.
For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.
This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sat, 19 Feb 2011 14:51:31 +0000 (14:51 +0000)]
It turns out that the code which enables specific LDN is somewhat buggy.
Instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it.
I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6373
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 17 Feb 2011 20:48:45 +0000 (20:48 +0000)]
Handle compiler options for source classes more generically
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6372
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 17 Feb 2011 20:47:49 +0000 (20:47 +0000)]
Make Makefile.inc parser loop more generic
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6371
2b7e53f0-3cfb-0310-b3e9-
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David Hendricks [Thu, 17 Feb 2011 00:52:02 +0000 (00:52 +0000)]
add mec1308 support to superiotool
This patch also disables FDC37M81x since it has a conflicting device ID
and is not supported very well anyway.
Signed-off-by: David Hendricks <dhendrix@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6370
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Wed, 16 Feb 2011 17:40:04 +0000 (17:40 +0000)]
Fix build errors introduced in r6367
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6369
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 16 Feb 2011 15:04:59 +0000 (15:04 +0000)]
Add ACPI code for Lenvo X60
It currently supports:
- Sleepbutton
- AC state
- Battery state
- Interrupt routing
- Display Brightness control
- Hotkeys
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6368
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Wed, 16 Feb 2011 13:43:00 +0000 (13:43 +0000)]
Extended K8T890 driver to include the K8T800 and K8M800 northbridges
The K8T800 is almost identical to the K8T800Pro, also added to this patch.
The K8T800_OLD is also defined, which is an older version of the K8T800,
but which has no driver and early HT code yet. Also extended the K8M890 VGA
driver to work for the K8M800 (not tested). According to the datasheet, the
K8T890 and K8T800 are similar enough to be able to use the same
initialization code. At least for the K8T800, this is sufficient to have
a working HT link with the CPU, and to initialise the V-Link to the
southbridge.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6367
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 16 Feb 2011 13:12:41 +0000 (13:12 +0000)]
Lenovo ThinkPad X60: Enable SMI handler
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6366
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Tue, 15 Feb 2011 13:07:32 +0000 (13:07 +0000)]
Remove more files and lines mistakenly copied from Roda to X60
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6365
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Tue, 15 Feb 2011 11:14:17 +0000 (11:14 +0000)]
Remove ACPI mistakenly copied from Roda to ThinkPad X60
It is incorrect, and will be replaced with proper ACPI for X60.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6364
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 15 Feb 2011 00:27:24 +0000 (00:27 +0000)]
Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be addded by the developer if needed.
Fixes abuild issues.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 15 Feb 2011 00:23:05 +0000 (00:23 +0000)]
SERIAL_POST was renamed to CONSOLE_POST a while ago
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6362
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 15 Feb 2011 00:14:32 +0000 (00:14 +0000)]
use git.seabios.org for checking out seabios.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6361
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Mon, 14 Feb 2011 20:02:47 +0000 (20:02 +0000)]
Lenovo ThinkPad X60 / X60s Support
Adds support for Lenovo X60 series ThinkPads. So far, only X60s
(Model 1703) has been tested.
It's a basic patch without SMI and ACPI, as this makes it easier to
review. SMI and ACPI patches will follow.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:26:22 +0000 (19:26 +0000)]
Use fprintf(stderr, ...) in library
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6359
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:25:27 +0000 (19:25 +0000)]
Stub out FILE*, stdout/stdin/stderr and implement fprintf on these
- Add FILE*
- Add stdout, stdin, stderr stubs
- Add fprintf that redirects to printf for stdout and stderr and fails otherwise
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6358
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:24:37 +0000 (19:24 +0000)]
lpgcc was too noisy in some cases
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6357
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:23:33 +0000 (19:23 +0000)]
Some more POSIX compatibility
- Add assert.h
- Add arpa/inet.h
- Add assert macro
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6356
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Mon, 14 Feb 2011 19:21:28 +0000 (19:21 +0000)]
Errata #169 works on HT, not MC
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Mon, 14 Feb 2011 19:19:58 +0000 (19:19 +0000)]
Removed LPC DMA Deadlock workaround...
Setting bit#21 in k8_f0#68 is part of the errata#169
which is handled in amdk8/coherent.c
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Mon, 14 Feb 2011 19:15:36 +0000 (19:15 +0000)]
Fix Typo. (and why is that file, and some of its siblings per-board?)
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 19:04:45 +0000 (19:04 +0000)]
Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 19:00:13 +0000 (19:00 +0000)]
This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:56:10 +0000 (18:56 +0000)]
I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6350
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:52:15 +0000 (18:52 +0000)]
This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6349
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:47:37 +0000 (18:47 +0000)]
This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsics in the build. The former issue will be addressed shortly, and the latter issue requires community assistance. This code is dependent on the AMD Family 14h mainboard code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6348
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:42:12 +0000 (18:42 +0000)]
Add AMD cpu wrapper code. Patch 4 of 8.
This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6347
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:38:14 +0000 (18:38 +0000)]
This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:35:15 +0000 (18:35 +0000)]
This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345
2b7e53f0-3cfb-0310-b3e9-
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Frank Vibrans [Mon, 14 Feb 2011 18:30:54 +0000 (18:30 +0000)]
Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
This code currently generates many warnings that are functionally benign. These are being addressed, but the wheels of bureaucracy turn slowly. This drop supports AMD cpu families 10h and 14h. Only Family 14h is used as an example in this set of patches. Other cpu families are supported by the infrastructure, but their specific support is not included herein. This patch is functionally independent of the other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sat, 12 Feb 2011 16:24:48 +0000 (16:24 +0000)]
Attached patch fixes the LPC decode ranges of SB600/SB800. We enable early only Serial/SIO/RTC.
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Thu, 10 Feb 2011 20:49:56 +0000 (20:49 +0000)]
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermannseppk [Thu, 10 Feb 2011 08:49:57 +0000 (08:49 +0000)]
RS690: Provide support for MMCONF.
If enabled, set up 0xe0000000..0xf0000000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up, so it's disabled by default.
Signed-off-by: Josef Kellermann<seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Thu, 10 Feb 2011 07:51:51 +0000 (07:51 +0000)]
Implemented workaround for erratum 169, obsoleting erratum 131.
Workaround for 131 removed.
Changed workaround for erratum 110 to only include pre-revision-F
processors.
For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)
Based on work and previous patches by:
Rudolf Marek <r.marek@assembler.cz>
Josef Kellermann <seppk@arcor.de>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Thu, 10 Feb 2011 07:48:07 +0000 (07:48 +0000)]
Fix a potential system hang by handling AMD Model F Erratum 89
a bit later.
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6339
2b7e53f0-3cfb-0310-b3e9-
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jakllsch [Tue, 8 Feb 2011 16:07:49 +0000 (16:07 +0000)]
Add NetBSD support to nvramtool.
Signed-off-by: <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6338
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 8 Feb 2011 08:37:47 +0000 (08:37 +0000)]
Fix cmos-files-y for relative paths
Thanks to Josef Kellermann <seppk@arcor.de> for reporting the issue.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6337
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Tue, 8 Feb 2011 02:36:39 +0000 (02:36 +0000)]
Place the W83627EHG MIDI base address mask in the correct position.
Corrects "index 98 has no mask" error at runtime.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6336
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 7 Feb 2011 20:16:40 +0000 (20:16 +0000)]
Reliably build arbitrary Kconfig-based revisions of SeaBIOS
Reliability is accomplished by checking out the desired SeaBIOS commitish
into a branch named 'coreboot' in the local SeaBIOS git repository. Using
a branch allows TAG-$(CONFIG_SEABIOS_..) to refer to any commitish in the
SeaBIOS git repo, not just branches and tags.
Configuration is done with make defconfig followed by enabling and
disabling of the relevant coreboot-specific SeaBIOS options by appending
to .config using echo. This works, because later entries in .config will
overwrite earlier ones.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6335
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Peter Stuge [Sat, 5 Feb 2011 13:32:56 +0000 (13:32 +0000)]
Actually add PC87382 into Kconfig, missing from r6332
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6334
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Sat, 5 Feb 2011 12:26:07 +0000 (12:26 +0000)]
Add PC87392 support
This adds support for the NSC PC87392 Super I/O. It is used in Lenovo
Docking Stations as Super I/O chip.
v2 because of:
- skip some empty files
- missing newlines in Kconfig and Makefile.inc
- add the Kconfig option in sorted order
Thanks to idwer on irc for pointing that out.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6333
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Sat, 5 Feb 2011 12:20:23 +0000 (12:20 +0000)]
Add PC87382 support
This patch adds support for NSC PC87382 Super I/O. It is used in many
Lenovo Notebooks as Docking LPC Switch.
v2 because of:
- Skip some empty files
- Fix newlines in Kconfig and Makefile.inc
- chip.h missed uart8250.h include
- add the Kconfig option in sorted order
Thanks to idwer on irc for pointing that out.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6332
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Christian Ruppert [Thu, 3 Feb 2011 16:00:28 +0000 (16:00 +0000)]
Add support for the IT8720F Super I/O
Signed-off-by: Christian Ruppert <idl0r@gentoo.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6331
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Thu, 3 Feb 2011 09:29:57 +0000 (09:29 +0000)]
Fix subvendor/subdevice programming on RS690
Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 3 Feb 2011 09:14:40 +0000 (09:14 +0000)]
Wrap CONFIG_MAINBOARD_PCI_SUBSYSTEM_{VENDOR,DEVICE}_ID in weak functions
This is so that boards can determine them on runtime based on hardware
properties, if so desired.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Kellermann <Joseph.Kellermann@heitec.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6329
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Uwe Hermann [Wed, 2 Feb 2011 23:56:15 +0000 (23:56 +0000)]
pmh7.[ch]: Add missing license headers.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6328
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Wed, 2 Feb 2011 23:49:41 +0000 (23:49 +0000)]
Add detection/dump support for the NSC PC87382.
It is a rather small 'Super I/O' device, containing a serial port, IR,
GPIO, and a Docking LPC switch. It is used in various Thinkpads.
Add 0x164e/0x16ef to the list of probed ports for NSC chips, as
Thinkpads are using this address pair.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6327
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Tue, 1 Feb 2011 19:19:53 +0000 (19:19 +0000)]
Properly add Lenovo EC to build
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6326
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Tue, 1 Feb 2011 10:44:26 +0000 (10:44 +0000)]
Add support for the Lenovo PMH7 embedded controller
Lenovo PMH7 (Power Management Hardware Hub) is found in
most recent (starting with X60/T60 AFAIK) Lenovo/IBM Laptops.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6325
2b7e53f0-3cfb-0310-b3e9-
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Mathias Krause [Tue, 1 Feb 2011 10:42:52 +0000 (10:42 +0000)]
Fix using custom build configs in abuild
The undocumented config argument for the -t option implicitly assumes
the config file is within the mainboard directory but fails to honor
this assumption when it comes to copying the file.
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6324
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 31 Jan 2011 21:16:48 +0000 (21:16 +0000)]
Fix an infinite loop in pnp_get_ioresource(), which freezes coreboot if
a rare condition arises.
Based on findings by Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6323
2b7e53f0-3cfb-0310-b3e9-
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Alexandru Gagniuc [Mon, 31 Jan 2011 21:14:02 +0000 (21:14 +0000)]
Add PCI ID's for VIA K8T800 and K8M800 northbridges.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6322
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 31 Jan 2011 21:03:14 +0000 (21:03 +0000)]
Build failure because of src/pc80/mc146818rtc_early.c unused variable
Fixes #173
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6321
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Sun, 30 Jan 2011 16:37:39 +0000 (16:37 +0000)]
Replace special rules for auxiliary files by cbfs-files-y entries
VGABIOS, Intel MBI and the bootsplash image were added with special
build rules. These are replaced by generic cbfs-files-y entries now.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6320
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Sun, 30 Jan 2011 16:31:15 +0000 (16:31 +0000)]
Inverse two arguments of cbfs-files-y and adapts its users (one of which already used the new order)
This is in reponse to feedback that the original setup was too complicated.
New cbfs-files-y behaviour:
cbfs-files-y contains the names of files as they appear in CBFS. The
arguments describe the on-filesystem name, the type and (optionally) the
position. Example:
cbfs-files-y += foo
foo-file := bar
foo-type := splashscreen
foo-position := 0xffff8000
This configures a CBFS file called "foo" that is marked "splashscreen",
located at 0xffff8000 in flash and contains the data of the file "bar"
in the filesystem (either in the current directory, ie. where the
corresponding Makefile.inc resides, or if that doesn't exist, relative
to the toplevel directory).
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6319
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Kevin O'Connor [Sun, 30 Jan 2011 07:40:32 +0000 (07:40 +0000)]
Make cbfstool available in $(obj) for simple user access.
- integrated Peter's suggestion ($< $@)
- removed @ prefix, we use the .SILENT pseudo-target
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6318
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Stefan Reinauer [Sat, 29 Jan 2011 05:51:54 +0000 (05:51 +0000)]
Pass all required toolchain parts to SeaBIOS correctly
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6317
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Fri, 28 Jan 2011 20:57:48 +0000 (20:57 +0000)]
Attached patch fixes the LPC decode ranges of SB700. We enable early only Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 28 Jan 2011 08:05:54 +0000 (08:05 +0000)]
This patch gets usbdebug console working in romstage.
- actually hook up usbdebug in printk/print_ for romstage
- make usbdebug.c more similar to the Linux kernel version it was
originally derived from.
- increase retries and timing for usbdebug init (at least one chipset
seems to need this)
- src/pc80/usbdebug_serial.c is not needed
- some small console cleanups
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6315
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 28 Jan 2011 07:56:39 +0000 (07:56 +0000)]
Separate CMOS layout from lbtable handling
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6314
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 28 Jan 2011 07:54:11 +0000 (07:54 +0000)]
Move CMOS handling into separate files in accessors
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6313
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 28 Jan 2011 07:50:33 +0000 (07:50 +0000)]
Move the parser for cmos.layout text files to accessors
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6312
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 28 Jan 2011 07:47:35 +0000 (07:47 +0000)]
rename CONFIG_SERIAL_POST to CONFIG_CONSOLE_POST
because that is what it does.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6311
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 28 Jan 2011 07:47:10 +0000 (07:47 +0000)]
Move CLI portion of nvramtool into cli/ subdirectory as first step towards librarization.
Also: update one regex wrapper user.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6310
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 28 Jan 2011 07:41:10 +0000 (07:41 +0000)]
Eliminate a couple of 3-line functions that barely wrap *printf calls
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6309
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Patrick Georgi [Fri, 28 Jan 2011 07:40:08 +0000 (07:40 +0000)]
No need to add varargs magic to a simple regex wrapper.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6308
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Fri, 28 Jan 2011 01:06:39 +0000 (01:06 +0000)]
Fix Bimini build
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6307
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Stefan Reinauer [Fri, 28 Jan 2011 01:03:18 +0000 (01:03 +0000)]
rk886ex lacked EC_ACPI
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6306
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Stefan Reinauer [Thu, 27 Jan 2011 23:56:48 +0000 (23:56 +0000)]
Only add EC code if EC is selected in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6305
2b7e53f0-3cfb-0310-b3e9-
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Sven Schnelle [Thu, 27 Jan 2011 11:43:03 +0000 (11:43 +0000)]
Add new ec subdir for Embedded Controllers and common ACPI EC support
Adds a new src/ec subdir for embedded controllers (mostly found in laptops)
and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead
of having their own copies of those functions.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304
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Peter Stuge [Thu, 27 Jan 2011 11:09:36 +0000 (11:09 +0000)]
SMM code on i945 platforms needs udelay()
smm-y wasn't required before, because udelay.c used to be #included from
various files in src/mainboard.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6303
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 27 Jan 2011 07:39:38 +0000 (07:39 +0000)]
Add a new CMOS variable which triggers activation of the
LPT port. With the CMOS variable set, LPT is found by SeaBIOS,
with the variable reset, it's not.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302
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Zheng Bao [Thu, 27 Jan 2011 03:31:50 +0000 (03:31 +0000)]
Trivial. Re-indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301
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Zheng Bao [Thu, 27 Jan 2011 02:19:55 +0000 (02:19 +0000)]
Set the phy via weak function.
As Rudolf called.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300
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Stefan Reinauer [Thu, 27 Jan 2011 01:11:20 +0000 (01:11 +0000)]
oops. this is weird. CAR addresses should be specified in the socket and not in
the board. I thought we did this ages ago.
Also push CAR BASE further down so it won't conflict with a 32mbit flash part.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299
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Stefan Reinauer [Tue, 25 Jan 2011 19:27:23 +0000 (19:27 +0000)]
Fix abuild
thanks to Kevin who came up with this
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6298
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Zheng Bao [Tue, 25 Jan 2011 06:06:58 +0000 (06:06 +0000)]
Set the SB800 SATA PHY correctly.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297
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Stefan Reinauer [Mon, 24 Jan 2011 21:27:22 +0000 (21:27 +0000)]
If the tool has 64bit issues, we need to find and fix them. No papering over them.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6296
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Josef Kellermann [Mon, 24 Jan 2011 21:07:57 +0000 (21:07 +0000)]
This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.
Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295
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Rudolf Marek [Mon, 24 Jan 2011 21:05:53 +0000 (21:05 +0000)]
Add CFLAGS when compiling resulting executable. It broke 64bit systems, because the rest uses -m32 now.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6294
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Zheng Bao [Mon, 24 Jan 2011 07:50:07 +0000 (07:50 +0000)]
Change fadt revision back to 3.
The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293
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Kevin O'Connor [Sun, 23 Jan 2011 06:47:09 +0000 (06:47 +0000)]
Clone a tag rather than SeaBIOS stable branch HEAD
Use a tag (rel-0.6.1.3) for SeaBIOS stable checkouts instead of the
stable branch. The tag is a little safer because it prevents an
incorrect commit to the stable branch from being immiediately picked
up by coreboot users.
Note - rel-0.6.1.3 (and 0.6.1-stable) now have the CFLAGS build fix
that was causing build failures for coreboot users.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6292
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Patrick Georgi [Fri, 21 Jan 2011 13:20:10 +0000 (13:20 +0000)]
... And fix the other compile time issues in cmos_layout.bin support
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291
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Patrick Georgi [Fri, 21 Jan 2011 12:45:37 +0000 (12:45 +0000)]
Make YABEL warnings-are-errors safe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6290
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Patrick Georgi [Fri, 21 Jan 2011 11:43:06 +0000 (11:43 +0000)]
Typo. s,CMOS_COMPONENT,CBFS_COMPONENT,.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6289
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Zheng Bao [Fri, 21 Jan 2011 08:46:27 +0000 (08:46 +0000)]
Now bimini can boot linux to login.
Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
smp_write_config_table will run. Then intr_data will be written
into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288
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Stefan Reinauer [Fri, 21 Jan 2011 07:46:32 +0000 (07:46 +0000)]
push ts5300 rom size to 1MB. In fact the flash part on that
board is 2MB and the entry point is somewhere in the middle. quite weird setup
http://www.embeddedarm.com/products/board-detail.php?product=TS-5300
We should probably wipe the board from the tree. It will not work anyways with
current coreboot and the architecture is kind of obscure.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287
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Patrick Georgi [Fri, 21 Jan 2011 07:29:40 +0000 (07:29 +0000)]
Add nvramtool -D option that allows taking cmos data from
a plain binary file. Overrides using cmos.default in CBFS
if both -C and -D are given.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6286
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Patrick Georgi [Fri, 21 Jan 2011 07:24:08 +0000 (07:24 +0000)]
Add nvramtool -C option that takes a CBFS file as argument.
When using this option, nvramtool looks for a cmos_layout.bin
and cmos.default in the image and uses these for layout information
and CMOS data.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6285
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