According to AMD documentation, cache type WP should be used for

execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 7f66f363efb6c592c9bc7a2b621a6ce5ceaa0fc0..26cdec3fbe69c1f1951e549aa3dd0c39bff04fc7 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -294,11 +294,11 @@ clear_fixed_var_mtrr_out:
        xorl    %edx, %edx
        /*
         * IMPORTANT: The two lines below can _not_ be written like this:
-        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
         * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
         */
        movl    $REAL_XIP_ROM_BASE, %eax
-       orl     $MTRR_TYPE_WRBACK, %eax
+       orl     $MTRR_TYPE_WRPROT, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx