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Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
[coreboot.git]
/
src
/
northbridge
/
amd
/
amdmct
/
mct_ddr3
/
mct_d.c
2012-03-02
Marc Jones
Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
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2011-10-15
Stefan Reinauer
AMD CPU and chipset fixes for compilation with gcc 4.6
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2011-06-03
Marc Jones
This patch sets max freq defaults for ddr2 and ddr3for...
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2011-01-06
Zheng Bao
Fix some settings fo AMD MCT. It is based on BIOS test...
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2010-10-08
Zheng Bao
Trivial. Spell checking.
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2010-09-28
Zheng Bao
Trivial. re-Indent the code.
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2010-09-27
Xavi Drudis Ferran
Obviously missing brackets.
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2010-09-21
Zheng Bao
Fix the typo. Field DisAutoRefresh is in DramTimngHi.
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2010-09-09
Arne Georg Gleditsch
Also improve boot time on AMD for the DDR3 code path.
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2010-09-05
Zheng Bao
Trivial. Currently the max frequency is preset as 400Mh...
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2010-09-04
Kerry She
AMD DDR2 and DDR3 MCT function InitPhyCompensation...
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2010-08-31
Zheng Bao
Get Byte65/66 for register manufacture ID code. RegMan1...
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2010-08-30
Kerry She
Trivial syntax correction of AMD mct_ddr3 dir.
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2010-04-23
Zheng Bao
DDR3 support for AMD Fam10.
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