Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,

rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/Kconfig b/src/Kconfig
index be55b4bf9063b43ad3a68a0075de6a245b9051b5..00c5591d00b6eefc796e0c4df2b3c5a91278879d 100644 (file)
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -499,6 +499,16 @@ config DEBUG_RAM_SETUP
 
          If unsure, say N.
 
+config HAVE_DEBUG_CAR
+       def_bool n
+
+config DEBUG_CAR
+       bool "Output verbose Cache-as-RAM debug messages"
+       default n
+       depends on HAVE_DEBUG_CAR
+       help
+         This option enables additional CAR related debug messages.
+
 config DEBUG_PIRQ
        bool "Check PIRQ table consistency"
        default n

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index d7f8cb9c48f21d8b36fd54cb1339ae3a15f0833c..6f47f6628320db3848dca177e19e1b166e9f05ff 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
index 5a9d7049dd431b0c62e5885a342ff5881ded5b62..d8539932b2ad880db15aceb2b98831e9a5079e81 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c
@@ -2,7 +2,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 65cabe9a4ff6a76402e0fd852459b2e2cdfb6aa7..fed8d6a6c3b192f995a5df8f464c005dcfa3475a 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 742700575b422168c44a37d3e81ada52edcdff32..b0a0f088296be9a0b2de763554ba38b510d4c8d4 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 2971a7fc8a137cea97f02b92539c576ea2f713b8..3e190fec9c22f4257f2fb73d5c47d3e13082c211 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1f56947eed4a659d75ac620b5b24efaa00d1650b..aba667986f977ce0279ceeb510a0055d192f1633 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -24,8 +24,6 @@
 
 #define RAMINIT_SYSINFO 1
 
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
 /* Used by raminit. */

diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index cbf8ef570be99f4cc6ecaa86dd31327891d387f1..76b3e9db935320b725568f15d45249b40064b527 100644 (file)
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -24,8 +24,6 @@
 
 #define RAMINIT_SYSINFO 1
 
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
 unsigned int get_sbdn(unsigned bus);
 
 /* Used by raminit. */

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index a0725eeb5be99b3ad952a63d081f4a7b59da589d..770cee1cbe2268aeecb2c731e95f746adcb5d75b 100644 (file)
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
index 7644ab49ba593bbf2aa5b28362f89adc5dfc6e72..1ecbd61be45d38a47043f8006cb3a8441c362783 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
@@ -25,7 +25,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c
index d429b4cd3124d2ee16ac459247a69b3ab34abacc..0883a5a60ff72ef90b8235ea1b9cdbc8687156a6 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/ap_romstage.c
+++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 9e221fc94808344af888b9a785c751384f64d2dc..13664418ab70ca9e412f2a855b2c61b93d0d248e 100644 (file)
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 56133accd14f033ec4ceab9a75d4a54d95b0461c..64b560d683f800f36f7b54e3b80a9681407e404f 100644 (file)
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 38d94a60d4174d14a63dc9b0120f9e3adc23f5a4..e53ddf4251db1a62c4a399cf1605effb34c4d22d 100644 (file)
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -22,7 +22,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 1af5c2c55f5110f536795595e4ce8999d92d1fc7..8fea9d9abffeb3041f1ce2b2539c1f9d34b42fb5 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 706014b9c28bdd1e850353913d684bef0413c756..77691a6ce2cc0e2c5b6e3865399ddf52832ee42a 100644 (file)
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 706014b9c28bdd1e850353913d684bef0413c756..77691a6ce2cc0e2c5b6e3865399ddf52832ee42a 100644 (file)
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -1,5 +1,4 @@
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 24302fe19a195fb7e2ee530710eaa477254c04e1..b966c465e8ed4cea54f9a24aac0d3697ee4641eb 100644 (file)
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -23,7 +23,6 @@
 //#define SYSTEM_TYPE 2        /* MOBILE */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 1
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c
index 5b88a6d989dfc7e97d804dd63854faadff5864fe..16b47685a6dd1b2d660b2c2f9027295b7363f733 100644 (file)
--- a/src/mainboard/msi/ms7260/ap_romstage.c
+++ b/src/mainboard/msi/ms7260/ap_romstage.c
@@ -24,7 +24,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 #define SET_NB_CFG_54 1                        /* Used by RAM init. */
 #define QRANK_DIMM_SUPPORT 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 908138a5d3df8d92121fa726a38b74a795c122f0..2605a16c3fc30cf2081c3778f234942bb4056d92 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -20,7 +20,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
 // #define RAM_TIMING_DEBUG 1
 // #define DQS_TRAIN_DEBUG 1
 // #define RES_DEBUG 1

diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index a2bf78bf1baed04165c3b25b8f5f6fc6c4d75737..522e2f3e11520d130108326cb01a593bbf0a6908 100644 (file)
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -24,7 +24,6 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index ed8ee856470c5d820c5ee88fc1ef7f8c85738e59..950f7dca59992ab78d21e16f1c9746aa33b305b4 100644 (file)
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -23,7 +23,6 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
index 8d3cb8d9c71950de11e9b532eb2a5a8b08577dd5..5d6f45e3287bf89738a668fe2c1bd80a3e477fe7 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c
index 8643bed96fdce486567e60abadecf62f2856fba8..8e8b73bd2a413b61e407167b4d2ae2816a551d76 100644 (file)
--- a/src/mainboard/supermicro/h8dme/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dme/ap_romstage.c
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c
index 8643bed96fdce486567e60abadecf62f2856fba8..8e8b73bd2a413b61e407167b4d2ae2816a551d76 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c
index 99036d0716fbd65d3716b665d5fc17fb1b7d88ca..e60992f88ad423b4842e6fbdb523b0202e89319b 100644 (file)
--- a/src/mainboard/tyan/s2912/ap_romstage.c
+++ b/src/mainboard/tyan/s2912/ap_romstage.c
@@ -23,7 +23,6 @@
 #define __PRE_RAM__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #define SET_NB_CFG_54 1
 

diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index abf87a77fc0c12d9ae2758c3fbe5cfb309cb74d9..479305fa2e92875c078f13e1600e811627677965 100644 (file)
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -23,7 +23,6 @@
  */
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 #define PAYLOAD_IS_SEABIOS 0
 
 #include <stdint.h>

diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index 38eda7c37fc9cda3b66f5669d0b5d0e11e7363ca..7e5b9dca4f08d5b922ea1fd09c806de46b7a148a 100644 (file)
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDFAM10
        bool
        select HAVE_DEBUG_RAM_SETUP
        select HAVE_DEBUG_SMBUS
+       select HAVE_DEBUG_CAR
        select HYPERTRANSPORT_PLUGIN_SUPPORT
        select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
        select MMCONF_SUPPORT

diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7aa7751820b097566c35209c45813160b56128c9..df4c079bbe2c3493a2bbb522c5dbdb8d9c8dbca1 100644 (file)
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -26,7 +26,7 @@
 
 static inline void print_debug_addr(const char *str, void *val)
 {
-#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
                printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }

diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 02a23ab36ea5364fa5c1afeca111ec9346e2c0f9..77a08f2f46011d062ec58815b71dbc0d176455bb 100644 (file)
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -21,6 +21,7 @@ config NORTHBRIDGE_AMD_AMDK8
        bool
        select HAVE_DEBUG_RAM_SETUP
        select HAVE_DEBUG_SMBUS
+       select HAVE_DEBUG_CAR
        select HYPERTRANSPORT_PLUGIN_SUPPORT
 
 config AGP_APERTURE_SIZE

diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 5cb996aa89c3730bd8a2e0f5710a0ac1419a2e62..ee8050ea5943d684496b5dcb3cefeaedba16029d 100644 (file)
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -3,13 +3,9 @@
  *
  */
 
-#ifndef CACHE_AS_RAM_ADDRESS_DEBUG
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-#endif
-
 static inline void print_debug_addr(const char *str, void *val)
 {
-#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
+#if CONFIG_DEBUG_CAR
                printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
 #endif
 }

diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 63755c3181c44c3c0537b813f60f18f5d55dc151..48f7173e8d1c1a80548848c538be7ec4e425b168 100644 (file)
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -21,7 +21,6 @@
 #define ASSEMBLY 1
 #define __PRE_RAM__
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
 #include <stdint.h>
 #include <device/pci_def.h>