src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #define RAMINIT_SYSINFO 1
   2 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   3
   4 #define SET_NB_CFG_54 1
   5
   6 //used by raminit
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 //used by incoherent_ht
  10 //#define K8_ALLOCATE_IO_RANGE 1
  11
  12 //used by init_cpus and fidvid
  13 #define SET_FIDVID 0
  14 //if we want to wait for core1 done before DQS training, set it to 0
  15 #define SET_FIDVID_CORE0_ONLY 1
  16
  17 #if CONFIG_K8_REV_F_SUPPORT == 1
  18 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  19 #endif
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <pc80/mc146818rtc.h>
  30
  31 #include <console/console.h>
  32 #include <cpu/amd/model_fxx_rev.h>
  33 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  34 #include <reset.h>
  35 #include "northbridge/amd/amdk8/raminit.h"
  36 #include "cpu/amd/model_fxx/apic_timer.c"
  37
  38 #include "cpu/x86/lapic/boot_cpu.c"
  39 #include "northbridge/amd/amdk8/reset_test.c"
  40
  41 #include "cpu/x86/bist.h"
  42
  43 #include "lib/delay.c"
  44
  45 #include "northbridge/amd/amdk8/debug.c"
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include <cpu/amd/mtrr.h>
  48 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  49
  50 #include "northbridge/amd/amdk8/setup_resource_map.c"
  51
  52 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  53
  54 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  55
  56 static void memreset_setup(void)
  57 {
  58         //GPIO on amd8111 to enable MEMRST ????
  59         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  60         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  68 {
  69 #define SMBUS_HUB 0x18
  70         int ret,i;
  71         unsigned device=(ctrl->channel0[0])>>8;
  72         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  73         i=2;
  74         do {
  75                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  76         } while ((ret!=0) && (i-->0));
  77
  78         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  79 }
  80 #if 0
  81 static inline void change_i2c_mux(unsigned device)
  82 {
  83 #define SMBUS_HUB 0x18
  84         int ret, i;
  85         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  86         i=2;
  87         do {
  88                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  89                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  90         } while ((ret!=0) && (i-->0));
  91         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  92         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  93 }
  94 #endif
  95
  96 static inline int spd_read_byte(unsigned device, unsigned address)
  97 {
  98         return smbus_read_byte(device, address);
  99 }
 100
 101 #include "northbridge/amd/amdk8/amdk8.h"
 102 #include "northbridge/amd/amdk8/incoherent_ht.c"
 103 #include "northbridge/amd/amdk8/coherent_ht.c"
 104 #include "northbridge/amd/amdk8/raminit_f.c"
 105 #include "lib/generic_sdram.c"
 106
 107  /* tyan does not want the default */
 108 #include "resourcemap.c"
 109
 110 #include "cpu/amd/dualcore/dualcore.c"
 111
 112 #define RC0 ((1<<0)<<8)
 113 #define RC1 ((1<<1)<<8)
 114 #define RC2 ((1<<2)<<8)
 115 #define RC3 ((1<<3)<<8)
 116
 117 #define DIMM0 0x50
 118 #define DIMM1 0x51
 119 #define DIMM2 0x52
 120 #define DIMM3 0x53
 121 #define DIMM4 0x54
 122 #define DIMM5 0x55
 123 #define DIMM6 0x56
 124 #define DIMM7 0x57
 125
 126
 127 #include "cpu/amd/car/post_cache_as_ram.c"
 128
 129 #include "cpu/amd/model_fxx/init_cpus.c"
 130
 131 #include "cpu/amd/model_fxx/fidvid.c"
 132
 133 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 134 #include "northbridge/amd/amdk8/early_ht.c"
 135
 136 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 137 {
 138         static const uint16_t spd_addr[] = {
 139                         //first node
 140                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 141                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 142 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 143                         //second node
 144                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 145                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 146 #endif
 147 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 148                         // third node
 149                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 150                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 151                         // four node
 152                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 153                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 154 #endif
 155
 156         };
 157
 158         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 159
 160         int needs_reset;
 161         unsigned bsp_apicid = 0;
 162 #if SET_FIDVID == 1
 163         struct cpuid_result cpuid1;
 164 #endif
 165
 166         if (!cpu_init_detectedx && boot_cpu()) {
 167                 /* Nothing special needs to be done to find bus 0 */
 168                 /* Allow the HT devices to be found */
 169
 170                 enumerate_ht_chain();
 171
 172                 /* Setup the rom access for 4M */
 173                 amd8111_enable_rom();
 174         }
 175
 176         if (bist == 0) {
 177                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 178         }
 179
 180 //      post_code(0x32);
 181
 182         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 183         uart_init();
 184         console_init();
 185
 186 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 187
 188         /* Halt if there was a built in self test failure */
 189         report_bist_failure(bist);
 190
 191         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 192
 193         setup_mb_resource_map();
 194 #if 0
 195         dump_pci_device(PCI_DEV(0, 0x18, 0));
 196         dump_pci_device(PCI_DEV(0, 0x19, 0));
 197 #endif
 198
 199         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 200
 201 #if CONFIG_MEM_TRAIN_SEQ == 1
 202         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 203 #endif
 204         setup_coherent_ht_domain(); // routing table and start other core0
 205
 206         wait_all_core0_started();
 207 #if CONFIG_LOGICAL_CPUS==1
 208         // It is said that we should start core1 after all core0 launched
 209         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 210          * So here need to make sure last core0 is started, esp for two way system,
 211          * (there may be apic id conflicts in that case)
 212          */
 213         start_other_cores();
 214         wait_all_other_cores_started(bsp_apicid);
 215 #endif
 216
 217         /* it will set up chains and store link pair for optimization later */
 218         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 219
 220 #if 0
 221         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 222         needs_reset = optimize_link_coherent_ht();
 223         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 224 #endif
 225
 226 #if SET_FIDVID == 1
 227         /* Check to see if processor is capable of changing FIDVID  */
 228         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 229         cpuid1 = cpuid(0x80000007);
 230         if( (cpuid1.edx & 0x6) == 0x6 ) {
 231
 232         {
 233                 /* Read FIDVID_STATUS */
 234                 msr_t msr;
 235                 msr=rdmsr(0xc0010042);
 236                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 237
 238         }
 239
 240         enable_fid_change();
 241
 242         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 243
 244         init_fidvid_bsp(bsp_apicid);
 245
 246         // show final fid and vid
 247         {
 248                 msr_t msr;
 249                 msr=rdmsr(0xc0010042);
 250                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 251
 252         }
 253
 254         } else {
 255                 print_debug("Changing FIDVID not supported\n");
 256         }
 257
 258 #endif
 259
 260 #if 1
 261         needs_reset = optimize_link_coherent_ht();
 262         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 263
 264         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 265         if (needs_reset) {
 266                 print_info("ht reset -\n");
 267                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 268         }
 269 #endif
 270         allow_all_aps_stop(bsp_apicid);
 271
 272         //It's the time to set ctrl in sysinfo now;
 273         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 274
 275         enable_smbus();
 276
 277 #if 0
 278         int i;
 279         for(i=0;i<4;i++) {
 280                 activate_spd_rom(&cpu[i]);
 281                 dump_smbus_registers();
 282         }
 283 #endif
 284
 285 #if 0
 286         for(i=1;i<256;i<<=1) {
 287                 change_i2c_mux(i);
 288                 dump_smbus_registers();
 289         }
 290 #endif
 291
 292         memreset_setup();
 293
 294         //do we need apci timer, tsc...., only debug need it for better output
 295         /* all ap stopped? */
 296 //        init_timer(); // Need to use TMICT to synconize FID/VID
 297
 298         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 299
 300 #if 0
 301         print_pci_devices();
 302 #endif
 303
 304 #if 0
 305 //        dump_pci_devices();
 306         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 307         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 308 #endif
 309
 310         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 311
 312 }
 313