2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 // #define RAM_TIMING_DEBUG 1
24 // #define DQS_TRAIN_DEBUG 1
25 // #define RES_DEBUG 1
27 #define RAMINIT_SYSINFO 1
28 #define K8_ALLOCATE_IO_RANGE 1
29 #define QRANK_DIMM_SUPPORT 1
30 #if CONFIG_LOGICAL_CPUS == 1
31 #define SET_NB_CFG_54 1
34 /* Used by init_cpus and fidvid. */
37 /* If we want to wait for core1 done before DQS training, set it to 0. */
38 #define SET_FIDVID_CORE0_ONLY 1
40 #if CONFIG_K8_REV_F_SUPPORT == 1
41 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
46 #include <device/pci_def.h>
47 #include <device/pci_ids.h>
49 #include <device/pnp_def.h>
50 #include <arch/romcc_io.h>
51 #include <cpu/x86/lapic.h>
52 #include <pc80/mc146818rtc.h>
54 #include <console/console.h>
56 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
57 #include "pc80/usbdebug_serial.c"
59 #include "lib/ramtest.c"
60 #include <cpu/amd/model_fxx_rev.h>
61 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
62 #include "northbridge/amd/amdk8/raminit.h"
63 #include "cpu/amd/model_fxx/apic_timer.c"
64 #include "lib/delay.c"
66 #include "cpu/x86/lapic/boot_cpu.c"
67 #include "northbridge/amd/amdk8/reset_test.c"
68 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
69 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
71 #include "cpu/x86/bist.h"
72 #include "northbridge/amd/amdk8/debug.c"
73 #include "cpu/x86/mtrr/earlymtrr.c"
74 #include "northbridge/amd/amdk8/setup_resource_map.c"
76 /* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
77 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
79 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
81 static void memreset(int controllers, const struct mem_controller *ctrl) {}
82 static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
84 static inline int spd_read_byte(unsigned int device, unsigned int address)
86 return smbus_read_byte(device, address);
89 #include "northbridge/amd/amdk8/amdk8_f.h"
90 #include "northbridge/amd/amdk8/incoherent_ht.c"
91 #include "northbridge/amd/amdk8/coherent_ht.c"
92 #include "northbridge/amd/amdk8/raminit_f.c"
93 #include "lib/generic_sdram.c"
95 #include "resourcemap.c"
96 #include "cpu/amd/dualcore/dualcore.c"
99 #define MCP55_USE_NIC 1
100 #define MCP55_USE_AZA 1
101 #define MCP55_PCI_E_X_0 0
103 #define MCP55_MB_SETUP \
104 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
105 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
106 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
107 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
108 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
109 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
111 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
112 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
114 #include "cpu/amd/car/post_cache_as_ram.c"
115 #include "cpu/amd/model_fxx/init_cpus.c"
116 #include "cpu/amd/model_fxx/fidvid.c"
118 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
119 #include "northbridge/amd/amdk8/early_ht.c"
121 static void sio_setup(void)
126 byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b);
128 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte);
130 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0);
132 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword);
134 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
136 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
139 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
141 static const uint16_t spd_addr[] = {
143 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
144 (0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
146 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
147 (0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
150 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
151 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
154 unsigned bsp_apicid = 0;
156 if (!cpu_init_detectedx && boot_cpu()) {
157 /* Nothing special needs to be done to find bus 0. */
158 /* Allow the HT devices to be found. */
159 enumerate_ht_chain();
163 /* Setup the MCP55. */
168 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
170 /* FIXME: This should be part of the Super I/O code/config. */
171 pnp_enter_ext_func_mode(SERIAL_DEV);
172 /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
173 pnp_write_config(SERIAL_DEV, 0x24, 0);
174 w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
175 pnp_exit_ext_func_mode(SERIAL_DEV);
177 setup_mb_resource_map();
179 report_bist_failure(bist); /* Halt upon BIST failure. */
181 mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
182 early_usbdebug_init();
186 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
187 print_debug("bsp_apicid=");
188 print_debug_hex8(bsp_apicid);
191 #if CONFIG_MEM_TRAIN_SEQ == 1
192 /* In BSP so could hold all AP until sysinfo is in RAM. */
193 set_sysinfo_in_ram(0);
196 setup_coherent_ht_domain(); /* Routing table and start other core0. */
197 wait_all_core0_started();
199 #if CONFIG_LOGICAL_CPUS == 1
200 /* It is said that we should start core1 after all core0 launched
201 * becase optimize_link_coherent_ht is moved out from
202 * setup_coherent_ht_domain, so here need to make sure last core0 is
203 * started, esp for two way system (there may be APIC ID conflicts in
207 wait_all_other_cores_started(bsp_apicid);
210 /* Set up chains and store link pair for optimization later. */
211 ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
215 msr_t msr = rdmsr(0xc0010042);
216 print_debug("begin msr fid, vid ");
217 print_debug_hex32(msr.hi);
218 print_debug_hex32(msr.lo);
223 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
224 init_fidvid_bsp(bsp_apicid);
227 msr_t msr = rdmsr(0xc0010042);
228 print_debug("end msr fid, vid ");
229 print_debug_hex32(msr.hi);
230 print_debug_hex32(msr.lo);
235 init_timer(); /* Need to use TMICT to synconize FID/VID. */
237 needs_reset |= optimize_link_coherent_ht();
238 needs_reset |= optimize_link_incoherent_ht(sysinfo);
239 needs_reset |= mcp55_early_setup_x();
241 /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
243 print_info("ht reset -\n");
246 allow_all_aps_stop(bsp_apicid);
248 /* It's the time to set ctrl in sysinfo now. */
249 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
253 /* All AP stopped? */
255 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
257 /* bsp switch stack to RAM and copy sysinfo RAM now. */