src/southbridge/intel/sch/ide.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009-2010 iWave Systems
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <device/device.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25
  26 /* PCI Configuration Space (D31:F1): IDE */
  27 #define   INTR_LN                       0x3c
  28 #define   IDE_TIM_PRI           0x80    /* IDE timings, primary */
  29
  30 extern int sch_port_access_read(int port,int reg, int bytes);
  31 static void ide_init(struct device *dev)
  32 {
  33         u32 ideTimingConfig;
  34         u32 reg32;
  35         printk(BIOS_DEBUG, "sch_ide: initializing... ");
  36
  37         reg32 = pci_read_config32(dev, PCI_COMMAND);
  38         pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
  39
  40         /* Program the clock */
  41
  42         if (sch_port_access_read(5,3,4) & (1<<3))
  43         {
  44                 /*533MHz
  45                 Read PCI MC register*/
  46                 reg32 = pci_read_config32(dev, 0x60);
  47                 pci_write_config32(dev,0x60,reg32 | 1);
  48         }
  49         else
  50         {
  51                 /*400MHz*/
  52                 reg32 = pci_read_config32(dev, 0x60);
  53                 reg32 &=~(1);
  54                 pci_write_config32(dev,0x60,reg32);
  55         }
  56
  57
  58         /* Enable primary IDE interface.
  59         80=04 81=00 82=02 83=80
  60         */
  61         ideTimingConfig = 0x80020000;
  62         printk(BIOS_DEBUG, "IDE0 ");
  63         pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
  64
  65         /* Set Interrupt Line */
  66         /* Interrupt Pin is set by D31IP.PIP */
  67         printk(BIOS_DEBUG, "\n");
  68 }
  69
  70 static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  71 {
  72         if (!vendor || !device) {
  73                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  74                                 pci_read_config32(dev, PCI_VENDOR_ID));
  75         } else {
  76                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  77                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  78         }
  79 }
  80
  81 static struct pci_operations ide_pci_ops = {
  82         .set_subsystem    = ide_set_subsystem,
  83 };
  84
  85 static struct device_operations ide_ops = {
  86         .read_resources         = pci_dev_read_resources,
  87         .set_resources          = pci_dev_set_resources,
  88         .enable_resources       = pci_dev_enable_resources,
  89         .init                   = ide_init,
  90         .scan_bus               = 0,
  91         .ops_pci                = &ide_pci_ops,
  92 };
  93
  94 static const struct pci_driver sch_ide __pci_driver = {
  95         .ops    = &ide_ops,
  96         .vendor = PCI_VENDOR_ID_INTEL,
  97         .device = 0x811A,
  98 };