2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008-2009 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <device/pci_ids.h>
25 #include <device/pci_ops.h>
29 #define HDA_ICII_REG 0x68
30 #define HDA_ICII_BUSY (1 << 0)
31 #define HDA_ICII_VALID (1 << 1)
33 typedef struct southbridge_intel_sch_config config_t;
35 static int set_bits(u32 port, u32 mask, u32 val)
40 /* Write (val & mask) to port */
47 /* Wait for readback of register to
48 * match what was just written to it
52 /* Wait 1ms based on BKDG wait time */
56 } while ((reg32 != val) && --count);
58 /* Timeout occurred */
64 static int codec_detect(u32 base)
69 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
70 if (set_bits(base + 0x08, 1, 1) == -1)
73 /* clear STATESTS bits (BAR + 0xE)[2:0] */
74 reg32 = read32(base + 0x0E);
76 write32(base + 0x0E, reg32);
78 /* Wait for readback of register to
79 * match what was just written to it
83 /* Wait 1ms based on BKDG wait time */
85 reg32 = read32(base + 0x0E);
86 } while ((reg32 != 0) && --count);
91 /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */
92 if (set_bits(base + 0x08, 1, 0) == -1)
95 /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
96 if (set_bits(base + 0x08, 1, 1) == -1)
99 /* Read in Codec location (BAR + 0xe)[2..0] */
100 reg32 = read32(base + 0xe);
108 /* Codec Not found */
109 /* Put HDA back in reset (BAR + 0x8) [0] */
110 set_bits(base + 0x08, 1, 0);
111 printk(BIOS_DEBUG, "sch_audio: No codec!\n");
115 const u32 *cim_verb_data = NULL;
116 u32 cim_verb_data_size = 0;
118 static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
120 printk(BIOS_DEBUG, "sch_audio: dev=%s\n", dev_path(dev));
121 printk(BIOS_DEBUG, "sch_audio: Reading viddid=%x\n", viddid);
125 while (idx < (cim_verb_data_size / sizeof(u32))) {
126 u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32
127 verb_size++; // we ship an additional gain value
128 if (cim_verb_data[idx] != viddid) {
129 idx += verb_size + 3; // skip verb + header
132 *verb = &cim_verb_data[idx + 3];
136 /* Not all codecs need to load another verb */
141 * Wait 50usec for the codec to indicate it is ready
142 * no response would imply that the codec is non-operative
145 static int wait_for_ready(u32 base)
147 /* Use a 50 usec timeout - the Linux kernel uses the
153 u32 reg32 = read32(base + HDA_ICII_REG);
154 if (!(reg32 & HDA_ICII_BUSY))
163 * Wait 50usec for the codec to indicate that it accepted
164 * the previous command. No response would imply that the code
168 static int wait_for_valid(u32 base)
170 /* Use a 50 usec timeout - the Linux kernel uses the
175 write32(base + 0x68, 1);
181 u32 reg32 = read32(base + 0x68);
182 if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) {
184 write32(base + 0x68, 2);
193 static void codec_init(struct device *dev, u32 base, int addr)
200 printk(BIOS_DEBUG, "sch_audio: Initializing codec #%d\n", addr);
203 if (wait_for_ready(base) == -1)
206 reg32 = (addr << 28) | 0x000f0000;
207 write32(base + 0x60, reg32);
209 if (wait_for_valid(base) == -1)
212 reg32 = read32(base + 0x0);
213 printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32);
215 reg32 = read32(base + 0x4);
216 printk(BIOS_DEBUG, "sch_audio: OUTPAY: %08x\n", reg32);
217 reg32 = read32(base + 0x6);
218 printk(BIOS_DEBUG, "sch_audio: INPAY: %08x\n", reg32);
220 reg32 = read32(base + 0x64);
223 printk(BIOS_DEBUG, "sch_audio: codec viddid: %08x\n", reg32);
224 verb_size = find_verb(dev, reg32, &verb);
227 printk(BIOS_DEBUG, "sch_audio: No verb!\n");
230 printk(BIOS_DEBUG, "sch_audio: verb_size: %d\n", verb_size);
233 for (i = 0; i < verb_size; i++) {
234 if (wait_for_ready(base) == -1)
237 write32(base + 0x60, verb[i]);
239 if (wait_for_valid(base) == -1)
242 printk(BIOS_DEBUG, "sch_audio: verb loaded.\n");
245 static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
249 for (i = 2; i >= 0; i--) {
250 if (codec_mask & (1 << i))
251 codec_init(dev, base, i);
255 static void sch_audio_init(struct device *dev)
258 struct resource *res;
262 res = find_resource(dev, 0x10);
266 reg32 = pci_read_config32(dev, PCI_COMMAND);
267 pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MEMORY);
269 // NOTE this will break as soon as the sch_audio get's a bar above
270 // 4G. Is there anything we can do about it?
271 base = (u32) res->base;
272 printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base);
273 codec_mask = codec_detect(base);
276 printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n",
278 codecs_init(dev, base, codec_mask);
280 /* No audio codecs found disable HD audio controller */
281 pci_write_config32(dev, 0x10, 0);
282 pci_write_config32(dev, PCI_COMMAND, 0);
283 reg32 = pci_read_config32(dev, 0xFC);
284 pci_write_config32(dev, 0xFC, reg32 | 1);
288 static void sch_audio_set_subsystem(device_t dev, unsigned vendor,
291 if (!vendor || !device) {
292 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
293 pci_read_config32(dev, PCI_VENDOR_ID));
295 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
296 ((device & 0xffff) << 16) | (vendor & 0xffff));
300 static struct pci_operations sch_audio_pci_ops = {
301 .set_subsystem = sch_audio_set_subsystem,
304 static struct device_operations sch_audio_ops = {
305 .read_resources = pci_dev_read_resources,
306 .set_resources = pci_dev_set_resources,
307 .enable_resources = pci_dev_enable_resources,
308 .init = sch_audio_init,
310 .ops_pci = &sch_audio_pci_ops,
313 /* SCH audio function */
314 static const struct pci_driver sch_audio __pci_driver = {
315 .ops = &sch_audio_ops,
316 .vendor = PCI_VENDOR_ID_INTEL,