op_group : in op_info_t;\r
left_operand : in gp_register_t;\r
right_operand : in gp_register_t;\r
- displacement : in gp_register_t;\r
+ \r
+ displacement : in gp_register_t;\r
prog_cnt : in instr_addr_t;\r
brpr : in std_logic;\r
+ \r
op_detail : in op_opt_t;\r
+ \r
alu_state : in alu_result_rec;\r
+ pval : in gp_register_t;\r
+ \r
alu_result : out alu_result_rec;\r
- addr : out word_t; --memaddr\r
- data : out gp_register_t --mem data --ureg\r
+ addr : out word_t; --memaddr\r
+ data : out gp_register_t; --mem data --ureg\r
+ \r
+ pinc : out std_logic;\r
+ pwr_en : out std_logic;\r
+ paddr : out paddr_t\r
);\r
\r
end alu;\r
end component exec_op;\r
\r
signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
- signal left, right : gp_register_t;\r
+ signal left_o, right_o : gp_register_t;\r
\r
begin\r
\r
add_inst : entity work.exec_op(add_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);\r
\r
and_inst : entity work.exec_op(and_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);\r
\r
or_inst : entity work.exec_op(or_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);\r
\r
xor_inst : entity work.exec_op(xor_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);\r
\r
shift_inst : entity work.exec_op(shift_op)\r
- port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
\r
calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr)\r
variable result_v : alu_result_rec;\r
\r
res_prod := '1';\r
mem_en := '0';\r
- mem_op := '0';\r
+ mem_op := '0';\r
alu_jump := '0';\r
\r
- left <= left_operand;\r
- right <= right_operand;\r
+ left_o <= left_operand;\r
+ right_o <= right_operand;\r
\r
addr <= add_result.result;\r
data <= right_operand;\r
mem_op := '0';\r
end if;\r
if op_detail(ST_OPT) = '1' then\r
- right <= displacement;\r
+ right_o <= displacement;\r
mem_en := '1';\r
end if;\r
when JMP_OP =>\r
if op_detail(JMP_REG_OPT) = '0' then\r
- left <= prog_cnt;\r
+ left_o <= prog_cnt;\r
end if;\r
alu_jump := '1';\r
when JMP_ST_OP => null;\r
+ \r
end case;\r
\r
\r
\r
result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
result_v.mem_en := mem_en and cond_met;\r
- result_v.mem_op := mem_op and cond_met;\r
+ result_v.mem_op := mem_op and cond_met;\r
result_v.alu_jump := alu_jump and cond_met;\r
result_v.brpr := brpr and nop;\r
\r
use IEEE.numeric_std.all;
use work.common_pkg.all;
+use work.extension_pkg.all;
--use work.core_extension.all;
package alu_pkg is
- type status_rec is record
- zero : std_logic;
- oflo : std_logic;
- sign : std_logic;
- carry : std_logic;
- end record;
-
- constant PADDR_WIDTH : integer := 2;
- type pointers_t is array(0 to 2**PADDR_WIDTH-1) of gp_register_t;
- subtype paddr_t is std_logic_vector(PADDR_WIDTH-1 downto 0);
-
- subtype status_t is byte_t;
--type alu_interal_rec is record
--
--end record alu_internal_rec;
op_group : in op_info_t;
left_operand : in gp_register_t;
right_operand : in gp_register_t;
- displacement : in gp_register_t;
- prog_cnt : in instr_addr_t;
- brpr : in std_logic;
+
+ displacement : in gp_register_t;
+ prog_cnt : in instr_addr_t;
+ brpr : in std_logic;
+
op_detail : in op_opt_t;
+
alu_state : in alu_result_rec;
+ pval : in gp_register_t;
+
alu_result : out alu_result_rec;
- addr : out word_t; --memaddr
- data : out gp_register_t --mem data --ureg
+ addr : out word_t; --memaddr
+ data : out gp_register_t; --mem data --ureg
+
+ pinc : out std_logic;
+ pwr_en : out std_logic;
+ paddr : out paddr_t
);
end component alu;
regfile_val : in gp_register_t;
reg_we : in std_logic;
reg_addr : in gp_addr_t;
- --System output
- result : out gp_register_t;--reg
- result_addr : out gp_addr_t;--reg
- addr : out word_t; --memaddr
- data : out gp_register_t; --mem data --ureg
- alu_jump : out std_logic;--reg
- brpr : out std_logic; --reg
- wr_en : out std_logic;--regop --reg
- dmem : out std_logic;--memop
- dmem_write_en : out std_logic;
- hword : out std_logic;
- byte_s : out std_logic
+ ext_reg : in extmod_rec;
+ --System output
+ result : out gp_register_t;--reg
+ result_addr : out gp_addr_t;--reg
+ addr : out word_t; --memaddr
+ data : out gp_register_t; --mem data --ureg
+ alu_jump : out std_logic;--reg
+ brpr : out std_logic; --reg
+ wr_en : out std_logic;--regop --reg
+ dmem : out std_logic;--memop
+ dmem_write_en : out std_logic;
+ hword : out std_logic;
+ byte_s : out std_logic;
+
+ ext_data_out : out gp_register_t
);
end component execute_stage;
signal dmem_wr_en_pin : std_logic;
signal hword_pin : std_logic;
signal byte_s_pin : std_logic;
+
+ signal gpm_in_pin : ext_mod_rec;
+ signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
-
begin
fetch_st : fetch_stage
exec_st : execute_stage
generic map('0')
- port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin,
- data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+ port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
writeback_st : writeback_stage
generic map('0', '1')
use work.common_pkg.all;
use work.alu_pkg.all;
-use work.gpm_pkg.all;
+use work.extension_pkg.all;
+--use work.gpm_pkg.all;
entity execute_stage is
regfile_val : in gp_register_t;
reg_we : in std_logic;
reg_addr : in gp_addr_t;
- --System output
- result : out gp_register_t;--reg
- result_addr : out gp_addr_t;--reg
- addr : out word_t; --memaddr
- data : out gp_register_t; --mem data --ureg
- alu_jump : out std_logic;--reg
- brpr : out std_logic; --reg
- wr_en : out std_logic;--regop --reg
- dmem : out std_logic;--memop
- dmem_write_en : out std_logic;
- hword : out std_logic;
- byte_s : out std_logic
+ ext_reg : in extmod_rec;
+ --System output
+ result : out gp_register_t;--reg
+ result_addr : out gp_addr_t;--reg
+ addr : out word_t; --memaddr
+ data : out gp_register_t; --mem data --ureg
+ alu_jump : out std_logic;--reg
+ brpr : out std_logic; --reg
+ wr_en : out std_logic;--regop --reg
+ dmem : out std_logic;--memop
+ dmem_write_en : out std_logic;
+ hword : out std_logic;
+ byte_s : out std_logic;
+
+ ext_data_out : out gp_register_t
);
end execute_stage;
signal ext_gpmp : extmod_rec;
signal data_out : gp_register_t;
+signal pval : gp_register_t;
+signal paddr : paddr_t;
+signal pinc, pwr_en : std_logic;
+
type exec_internal is record
alu_inst : alu
port map(clk, reset, condition, op_group,
- left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data);
+ left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr);
clk,
reset,
ext_gpmp,
- data_out,
- alu_nxt,
- psw
-
+ ext_data_out,
+ alu_nxt.status,
+ paddr,
+ pinc,
+ pwr_en,
+ psw,
+ pval
);
use work.common_pkg.all;
use work.extension_pkg.all;
-use work.alu_pkg.all;
+--use work.alu_pkg.all;
--use work.gpm_pkg.all;
entity extension_gpm is
reset : in std_logic;
-- general extension interface
ext_reg : in extmod_rec;
- data_out : out gp_register_t;
+ data_out : out gp_register_t;
-- Input
- alu_nxt : in alu_result_rec;
+ psw_nxt : in status_rec;
paddr : in paddr_t;
pinc : in std_logic;
pwr_en : in std_logic;
-- Ouput
psw : out status_rec;
pval : out gp_register_t
-
);
end extension_gpm;
use work.extension_pkg.all;
architecture behav of extension_gpm is
+
+type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t;
+
type gpm_internal is record
- status : status_rec;
+ status : status_rec;
preg : pointers_t;
end record gpm_internal;
syn : process (clk, reset)
begin
if (reset = RESET_VALUE) then
- reg.status <= ('0','0','0','0');
+ reg.status <= (others=>'0');
reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH)));
elsif rising_edge(clk) then
reg <= reg_nxt;
end if;
end process syn;
-asyn : process (clk, reset, reg, alu_nxt, ext_reg, pval, pwr_en, pinc, paddr)
+asyn : process (clk, reset, reg, psw_nxt, ext_reg, pval, pwr_en, pinc, paddr)
variable reg_nxt_v : gpm_internal;
variable incb : gp_register_t;
variable sel_pval : gp_register_t;
+
+ variable data_out_v : gp_register_t;
+ variable data_v : gp_register_t;
+ variable tmp_data : gp_register_t;
begin
reg_nxt_v := reg;
+ data_v := ext_reg.data;
psw <= reg.status;
- data_out <= (others => '0');
+
+ data_out_v := (others => '0');
- incb := (others => '0');
incb(0) := '1';
if pinc = '1' then
- incb := (others => '1');
+ incb(incb'high downto 1) := (others => '1');
+ else
+ incb(incb'high downto 1) := (others => '0');
end if;
-
+
if (ext_reg.sel = '1') and ext_reg.wr_en = '1' then
case ext_reg.addr(1 downto 0) is
when "00" =>
if ext_reg.byte_en(0) = '1' then
- reg_nxt_v.psw := (ext_reg.data(0),ext_reg.data(1),ext_reg.data(3),ext_reg.data(2));
+ reg_nxt_v.psw := (data_v(0), data_v(1), data_v(3), data_v(2));
psw <= reg_nxt_v.psw;
end if;
when "01" =>
--STACK_POINTER
+ tmp_data := (others =>'0');
+ tmp_data(tmp_data'high downto BYTE_ADDR) := reg.preg(0);
+
if ext_reg.byte_en(0) = '1' then
- reg_next_v.preg(0)(byte_t'range) := ext_reg.data(byte_t'range);
+ tmp_data(byte_t'range) := data_v(byte_t'range);
end if;
if ext_reg.byte_en(1) = '1' then
- reg_next_v.preg(0)((byte_t'length*2)-1 downto byte_t'length) :=
- ext_reg.data((byte_t'length*2)-1 downto byte_t'length) ;
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v(2*byte_t'length-1) downto byte_t'length);
end if;
if ext_reg.byte_en(2) = '1' then
- reg_next_v.preg(0)((byte_t'length*3)-1 downto byte_t'length*2) :=
- ext_reg.data((byte_t'length*3)-1 downto byte_t'length*2) ;
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v(3*byte_t'length-1) downto 2*byte_t'length);
end if;
if ext_reg.byte_en(3) = '1' then
- reg_next_v.preg(0)((byte_t'length*4)-1 downto byte_t'length*3) :=
- ext_reg.data((byte_t'length*4)-1 downto byte_t'length*3) ;
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v(4*byte_t'length-1) downto 3*byte_t'length);
end if;
+
+ reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTE_ADDR);
when others => null;
end case;
end if;
-
+
+
if (ext_reg.sel = '1') and wr_en = '0' then
case ext_reg.addr(1 downto 0) is
when "00" =>
if ext_reg.byte_en(0) = '1' then
- data_out(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
+ data_out_v(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
end if;
when "01" =>
--STACK_POINTER
- if ext_reg.byte_en(0) = '1' then
- data_out(byte_t'range) <= reg.preg(0)(byte_t'range);
- end if;
- if ext_reg.byte_en(1) = '1' then
- data_out((byte_t'length*2)-1 downto byte_t'length) <=
- reg_preg(0)((byte_t'length*2)-1 downto byte_t'length) ;
- end if;
- if ext_reg.byte_en(2) = '1' then
- data_out((byte_t'length*3)-1 downto 2*byte_t'length) <=
- reg_preg(0)((byte_t'length*3)-1 downto 2*byte_t'length) ;
- end if;
- if ext_reg.byte_en(3) = '1' then
- data_out((byte_t'length*4)-1 downto 3*byte_t'length) <=
- reg_preg(0)((byte_t'length*4)-1 downto 3*byte_t'length) ;
- end if;
+ data_out_v(data_out_v'high downto BYTE_ADDR) := reg.preg(0);
when others => null;
end case;
end if;
sel_pval := reg_nxt_v.preg(unsigned(paddr));
- pval <= sel_pval;
+
if pwr_en = '1' then
reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
end if;
- reg_nxt_v.status := alu_nxt.status;
+ reg_nxt_v.status := psw_nxt;
reg_nxt <= reg_nxt_v;
+ data_out <= data_out_v;
+
+ pval <= (others =>'0');
+ pval(pval'high downto BYTE_ADDR) <= sel_pval;
end process asyn;
end behav;
use IEEE.numeric_std.all;
use work.common_pkg.all;
-use work.alu_pkg.all;
+--use work.alu_pkg.all;
--use work.gpm_pkg.all;
package extension_pkg is
constant EXTWORDL : integer := log2c(4);
constant BYTEADDR : integer := log2c(4);
-constant PCOUNT : integer := log2c(4);
+constant PCOUNT : integer := 3;
constant EXTWORDS : integer := EXTWORDL + BYTEADDR;
subtype ext_addrid_t is std_logic_vector(gp_register_t'high - EXTWORDS downto 0);
subtype ext_addr_t is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0);
-subtype pointer_count is std_logic_vector(PCOUNT-1 downto 0);
+subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);
type extmod_rec is record
sel : std_logic;
end record;
-
+type status_rec is record
+ zero : std_logic;
+ oflo : std_logic;
+ sign : std_logic;
+ carry : std_logic;
+end record;
constant EXT_7SEG_ADDR: ext_addrid_t := x"FFFFFFA";
constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
reset : in std_logic;
-- general extension interface
ext_reg : in extmod_rec;
- data_out : out gp_register_t;
+ data_out : out gp_register_t;
-- Input
- alu_nxt : in alu_result_rec;
+ psw_nxt : in status_rec;
paddr : in paddr_t;
pinc : in std_logic;
pwr_en : in std_logic;
-- Ouput
psw : out status_rec;
pval : out gp_register_t
-
-
);
end component extension_gpm;
projects / calu.git / commitdiff