From f4f734f50124027f0371a3cb5f4de18353692235 Mon Sep 17 00:00:00 2001 From: "U-Thor\\Schakal" Date: Fri, 3 Dec 2010 13:56:16 +0100 Subject: [PATCH] modified: interfaces according to SP operation --- cpu/src/alu.vhd | 15 ++++++-- cpu/src/alu_b.vhd | 25 ++++++------- cpu/src/alu_pkg.vhd | 32 ++++++++--------- cpu/src/core_pkg.vhd | 27 +++++++------- cpu/src/core_top.vhd | 8 +++-- cpu/src/execute_stage.vhd | 30 +++++++++------- cpu/src/execute_stage_b.vhd | 17 ++++++--- cpu/src/extension.vhd | 7 ++-- cpu/src/extension_b.vhd | 71 +++++++++++++++++++------------------ cpu/src/extension_pkg.vhd | 19 +++++----- 10 files changed, 140 insertions(+), 111 deletions(-) diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index e59d268..3df35c9 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -17,14 +17,23 @@ entity alu is op_group : in op_info_t; left_operand : in gp_register_t; right_operand : in gp_register_t; - displacement : in gp_register_t; + + displacement : in gp_register_t; prog_cnt : in instr_addr_t; brpr : in std_logic; + op_detail : in op_opt_t; + alu_state : in alu_result_rec; + pval : in gp_register_t; + alu_result : out alu_result_rec; - addr : out word_t; --memaddr - data : out gp_register_t --mem data --ureg + addr : out word_t; --memaddr + data : out gp_register_t; --mem data --ureg + + pinc : out std_logic; + pwr_en : out std_logic; + paddr : out paddr_t ); end alu; diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 696e0f7..c46f9e5 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -22,24 +22,24 @@ architecture behaviour of alu is end component exec_op; signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec; - signal left, right : gp_register_t; + signal left_o, right_o : gp_register_t; begin add_inst : entity work.exec_op(add_op) - port map(clk,reset,left, right, op_detail, alu_state, add_result); + port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result); and_inst : entity work.exec_op(and_op) - port map(clk,reset,left, right, op_detail, alu_state, and_result); + port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result); or_inst : entity work.exec_op(or_op) - port map(clk,reset,left, right, op_detail, alu_state, or_result); + port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result); xor_inst : entity work.exec_op(xor_op) - port map(clk,reset,left, right, op_detail, alu_state, xor_result); + port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result); shift_inst : entity work.exec_op(shift_op) - port map(clk,reset,left, right, op_detail, alu_state, shift_result); + port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result); calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr) variable result_v : alu_result_rec; @@ -54,11 +54,11 @@ begin res_prod := '1'; mem_en := '0'; - mem_op := '0'; + mem_op := '0'; alu_jump := '0'; - left <= left_operand; - right <= right_operand; + left_o <= left_operand; + right_o <= right_operand; addr <= add_result.result; data <= right_operand; @@ -124,15 +124,16 @@ begin mem_op := '0'; end if; if op_detail(ST_OPT) = '1' then - right <= displacement; + right_o <= displacement; mem_en := '1'; end if; when JMP_OP => if op_detail(JMP_REG_OPT) = '0' then - left <= prog_cnt; + left_o <= prog_cnt; end if; alu_jump := '1'; when JMP_ST_OP => null; + end case; @@ -149,7 +150,7 @@ begin result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; result_v.mem_en := mem_en and cond_met; - result_v.mem_op := mem_op and cond_met; + result_v.mem_op := mem_op and cond_met; result_v.alu_jump := alu_jump and cond_met; result_v.brpr := brpr and nop; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index 7a9564e..57e2dc4 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -4,23 +4,12 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.common_pkg.all; +use work.extension_pkg.all; --use work.core_extension.all; package alu_pkg is - type status_rec is record - zero : std_logic; - oflo : std_logic; - sign : std_logic; - carry : std_logic; - end record; - - constant PADDR_WIDTH : integer := 2; - type pointers_t is array(0 to 2**PADDR_WIDTH-1) of gp_register_t; - subtype paddr_t is std_logic_vector(PADDR_WIDTH-1 downto 0); - - subtype status_t is byte_t; --type alu_interal_rec is record -- --end record alu_internal_rec; @@ -86,14 +75,23 @@ package alu_pkg is op_group : in op_info_t; left_operand : in gp_register_t; right_operand : in gp_register_t; - displacement : in gp_register_t; - prog_cnt : in instr_addr_t; - brpr : in std_logic; + + displacement : in gp_register_t; + prog_cnt : in instr_addr_t; + brpr : in std_logic; + op_detail : in op_opt_t; + alu_state : in alu_result_rec; + pval : in gp_register_t; + alu_result : out alu_result_rec; - addr : out word_t; --memaddr - data : out gp_register_t --mem data --ureg + addr : out word_t; --memaddr + data : out gp_register_t; --mem data --ureg + + pinc : out std_logic; + pwr_en : out std_logic; + paddr : out paddr_t ); end component alu; diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 828f610..4d31870 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -93,18 +93,21 @@ package core_pkg is regfile_val : in gp_register_t; reg_we : in std_logic; reg_addr : in gp_addr_t; - --System output - result : out gp_register_t;--reg - result_addr : out gp_addr_t;--reg - addr : out word_t; --memaddr - data : out gp_register_t; --mem data --ureg - alu_jump : out std_logic;--reg - brpr : out std_logic; --reg - wr_en : out std_logic;--regop --reg - dmem : out std_logic;--memop - dmem_write_en : out std_logic; - hword : out std_logic; - byte_s : out std_logic + ext_reg : in extmod_rec; + --System output + result : out gp_register_t;--reg + result_addr : out gp_addr_t;--reg + addr : out word_t; --memaddr + data : out gp_register_t; --mem data --ureg + alu_jump : out std_logic;--reg + brpr : out std_logic; --reg + wr_en : out std_logic;--regop --reg + dmem : out std_logic;--memop + dmem_write_en : out std_logic; + hword : out std_logic; + byte_s : out std_logic; + + ext_data_out : out gp_register_t ); end component execute_stage; diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index bb95789..d67243c 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -47,10 +47,12 @@ architecture behav of core_top is signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; signal byte_s_pin : std_logic; + + signal gpm_in_pin : ext_mod_rec; + signal gpm_out_pin : gp_register_t; signal nop_pin : std_logic; - begin fetch_st : fetch_stage @@ -105,8 +107,8 @@ begin exec_st : execute_stage generic map('0') - port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, result_pin, result_addr_pin,addr_pin, - data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin); + port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin, + data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin); writeback_st : writeback_stage generic map('0', '1') diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd index afcf986..ff24942 100644 --- a/cpu/src/execute_stage.vhd +++ b/cpu/src/execute_stage.vhd @@ -4,7 +4,8 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.alu_pkg.all; -use work.gpm_pkg.all; +use work.extension_pkg.all; +--use work.gpm_pkg.all; entity execute_stage is @@ -23,18 +24,21 @@ entity execute_stage is regfile_val : in gp_register_t; reg_we : in std_logic; reg_addr : in gp_addr_t; - --System output - result : out gp_register_t;--reg - result_addr : out gp_addr_t;--reg - addr : out word_t; --memaddr - data : out gp_register_t; --mem data --ureg - alu_jump : out std_logic;--reg - brpr : out std_logic; --reg - wr_en : out std_logic;--regop --reg - dmem : out std_logic;--memop - dmem_write_en : out std_logic; - hword : out std_logic; - byte_s : out std_logic + ext_reg : in extmod_rec; + --System output + result : out gp_register_t;--reg + result_addr : out gp_addr_t;--reg + addr : out word_t; --memaddr + data : out gp_register_t; --mem data --ureg + alu_jump : out std_logic;--reg + brpr : out std_logic; --reg + wr_en : out std_logic;--regop --reg + dmem : out std_logic;--memop + dmem_write_en : out std_logic; + hword : out std_logic; + byte_s : out std_logic; + + ext_data_out : out gp_register_t ); end execute_stage; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index a7809e5..ccbfee3 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -19,6 +19,10 @@ signal psw : status_rec; signal ext_gpmp : extmod_rec; signal data_out : gp_register_t; +signal pval : gp_register_t; +signal paddr : paddr_t; +signal pinc, pwr_en : std_logic; + type exec_internal is record @@ -35,7 +39,7 @@ begin alu_inst : alu port map(clk, reset, condition, op_group, - left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data); + left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr); @@ -45,10 +49,13 @@ port map(clk, reset, condition, op_group, clk, reset, ext_gpmp, - data_out, - alu_nxt, - psw - + ext_data_out, + alu_nxt.status, + paddr, + pinc, + pwr_en, + psw, + pval ); diff --git a/cpu/src/extension.vhd b/cpu/src/extension.vhd index aa19e9d..2751359 100644 --- a/cpu/src/extension.vhd +++ b/cpu/src/extension.vhd @@ -4,7 +4,7 @@ use IEEE.numeric_std.all; use work.common_pkg.all; use work.extension_pkg.all; -use work.alu_pkg.all; +--use work.alu_pkg.all; --use work.gpm_pkg.all; entity extension_gpm is @@ -19,16 +19,15 @@ entity extension_gpm is reset : in std_logic; -- general extension interface ext_reg : in extmod_rec; - data_out : out gp_register_t; + data_out : out gp_register_t; -- Input - alu_nxt : in alu_result_rec; + psw_nxt : in status_rec; paddr : in paddr_t; pinc : in std_logic; pwr_en : in std_logic; -- Ouput psw : out status_rec; pval : out gp_register_t - ); end extension_gpm; diff --git a/cpu/src/extension_b.vhd b/cpu/src/extension_b.vhd index 0c18a7d..d004bbb 100644 --- a/cpu/src/extension_b.vhd +++ b/cpu/src/extension_b.vhd @@ -9,8 +9,11 @@ use work.mem_pkg.all; use work.extension_pkg.all; architecture behav of extension_gpm is + +type pointers_t is array( 0 to ((2**(paddr_t'length))-1)) of ext_addr_t; + type gpm_internal is record - status : status_rec; + status : status_rec; preg : pointers_t; end record gpm_internal; @@ -21,94 +24,94 @@ begin syn : process (clk, reset) begin if (reset = RESET_VALUE) then - reg.status <= ('0','0','0','0'); + reg.status <= (others=>'0'); reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH))); elsif rising_edge(clk) then reg <= reg_nxt; end if; end process syn; -asyn : process (clk, reset, reg, alu_nxt, ext_reg, pval, pwr_en, pinc, paddr) +asyn : process (clk, reset, reg, psw_nxt, ext_reg, pval, pwr_en, pinc, paddr) variable reg_nxt_v : gpm_internal; variable incb : gp_register_t; variable sel_pval : gp_register_t; + + variable data_out_v : gp_register_t; + variable data_v : gp_register_t; + variable tmp_data : gp_register_t; begin reg_nxt_v := reg; + data_v := ext_reg.data; psw <= reg.status; - data_out <= (others => '0'); + + data_out_v := (others => '0'); - incb := (others => '0'); incb(0) := '1'; if pinc = '1' then - incb := (others => '1'); + incb(incb'high downto 1) := (others => '1'); + else + incb(incb'high downto 1) := (others => '0'); end if; - + if (ext_reg.sel = '1') and ext_reg.wr_en = '1' then case ext_reg.addr(1 downto 0) is when "00" => if ext_reg.byte_en(0) = '1' then - reg_nxt_v.psw := (ext_reg.data(0),ext_reg.data(1),ext_reg.data(3),ext_reg.data(2)); + reg_nxt_v.psw := (data_v(0), data_v(1), data_v(3), data_v(2)); psw <= reg_nxt_v.psw; end if; when "01" => --STACK_POINTER + tmp_data := (others =>'0'); + tmp_data(tmp_data'high downto BYTE_ADDR) := reg.preg(0); + if ext_reg.byte_en(0) = '1' then - reg_next_v.preg(0)(byte_t'range) := ext_reg.data(byte_t'range); + tmp_data(byte_t'range) := data_v(byte_t'range); end if; if ext_reg.byte_en(1) = '1' then - reg_next_v.preg(0)((byte_t'length*2)-1 downto byte_t'length) := - ext_reg.data((byte_t'length*2)-1 downto byte_t'length) ; + tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v(2*byte_t'length-1) downto byte_t'length); end if; if ext_reg.byte_en(2) = '1' then - reg_next_v.preg(0)((byte_t'length*3)-1 downto byte_t'length*2) := - ext_reg.data((byte_t'length*3)-1 downto byte_t'length*2) ; + tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v(3*byte_t'length-1) downto 2*byte_t'length); end if; if ext_reg.byte_en(3) = '1' then - reg_next_v.preg(0)((byte_t'length*4)-1 downto byte_t'length*3) := - ext_reg.data((byte_t'length*4)-1 downto byte_t'length*3) ; + tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v(4*byte_t'length-1) downto 3*byte_t'length); end if; + + reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTE_ADDR); when others => null; end case; end if; - + + if (ext_reg.sel = '1') and wr_en = '0' then case ext_reg.addr(1 downto 0) is when "00" => if ext_reg.byte_en(0) = '1' then - data_out(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero); + data_out_v(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero); end if; when "01" => --STACK_POINTER - if ext_reg.byte_en(0) = '1' then - data_out(byte_t'range) <= reg.preg(0)(byte_t'range); - end if; - if ext_reg.byte_en(1) = '1' then - data_out((byte_t'length*2)-1 downto byte_t'length) <= - reg_preg(0)((byte_t'length*2)-1 downto byte_t'length) ; - end if; - if ext_reg.byte_en(2) = '1' then - data_out((byte_t'length*3)-1 downto 2*byte_t'length) <= - reg_preg(0)((byte_t'length*3)-1 downto 2*byte_t'length) ; - end if; - if ext_reg.byte_en(3) = '1' then - data_out((byte_t'length*4)-1 downto 3*byte_t'length) <= - reg_preg(0)((byte_t'length*4)-1 downto 3*byte_t'length) ; - end if; + data_out_v(data_out_v'high downto BYTE_ADDR) := reg.preg(0); when others => null; end case; end if; sel_pval := reg_nxt_v.preg(unsigned(paddr)); - pval <= sel_pval; + if pwr_en = '1' then reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb)); end if; - reg_nxt_v.status := alu_nxt.status; + reg_nxt_v.status := psw_nxt; reg_nxt <= reg_nxt_v; + data_out <= data_out_v; + + pval <= (others =>'0'); + pval(pval'high downto BYTE_ADDR) <= sel_pval; end process asyn; end behav; diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd index daa2306..5d3eb12 100644 --- a/cpu/src/extension_pkg.vhd +++ b/cpu/src/extension_pkg.vhd @@ -4,19 +4,19 @@ use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.common_pkg.all; -use work.alu_pkg.all; +--use work.alu_pkg.all; --use work.gpm_pkg.all; package extension_pkg is constant EXTWORDL : integer := log2c(4); constant BYTEADDR : integer := log2c(4); -constant PCOUNT : integer := log2c(4); +constant PCOUNT : integer := 3; constant EXTWORDS : integer := EXTWORDL + BYTEADDR; subtype ext_addrid_t is std_logic_vector(gp_register_t'high - EXTWORDS downto 0); subtype ext_addr_t is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0); -subtype pointer_count is std_logic_vector(PCOUNT-1 downto 0); +subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0); type extmod_rec is record sel : std_logic; @@ -27,7 +27,12 @@ subtype pointer_count is std_logic_vector(PCOUNT-1 downto 0); end record; - +type status_rec is record + zero : std_logic; + oflo : std_logic; + sign : std_logic; + carry : std_logic; +end record; constant EXT_7SEG_ADDR: ext_addrid_t := x"FFFFFFA"; constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB"; @@ -48,17 +53,15 @@ constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF"; reset : in std_logic; -- general extension interface ext_reg : in extmod_rec; - data_out : out gp_register_t; + data_out : out gp_register_t; -- Input - alu_nxt : in alu_result_rec; + psw_nxt : in status_rec; paddr : in paddr_t; pinc : in std_logic; pwr_en : in std_logic; -- Ouput psw : out status_rec; pval : out gp_register_t - - ); end component extension_gpm; -- 2.25.1