cpu/src/execute_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7 use work.gpm_pkg.all;
   8 use work.extension_pkg.all;
   9
  10 architecture behav of execute_stage is
  11
  12 signal condition : condition_t;
  13 signal op_group : op_info_t;
  14 signal op_detail : op_opt_t;
  15 signal left_operand, right_operand : gp_register_t;
  16 signal alu_state, alu_nxt : alu_result_rec;
  17 signal psw : status_rec;
  18                 -- extension signals
  19                 signal ext_gpmp :  extmod_rec;
  20                 signal data_out    : gp_register_t;
  21
  22
  23
  24 type exec_internal is record
  25         result : gp_register_t;
  26         res_addr : gp_addr_t;
  27         alu_jump : std_logic;
  28         brpr    : std_logic;
  29         wr_en   : std_logic;
  30 end record;
  31
  32 signal reg, reg_nxt : exec_internal;
  33
  34 begin
  35
  36 alu_inst : alu
  37 port map(clk, reset, condition, op_group,
  38          left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data);
  39
  40
  41
  42         gpmp_inst :  extension_gpm
  43                 generic map (RESET_VALUE)
  44                 port map (
  45                         clk,
  46                         reset,
  47                         ext_gpmp,
  48                         data_out,
  49                         alu_nxt,
  50                         psw
  51
  52                 );
  53
  54
  55
  56 syn: process(clk, reset)
  57
  58 begin
  59
  60         if reset = RESET_VALUE then
  61                 reg.alu_jump <= '0';
  62                 reg.brpr <= '0';
  63                 reg.wr_en <= '0';
  64                 reg.result <= (others =>'0');
  65                 reg.res_addr <= (others => '0');
  66         elsif rising_edge(clk) then
  67                 reg <= reg_nxt;
  68         end if;
  69
  70 end process;
  71
  72 asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
  73 begin
  74
  75         condition <= dec_instr.condition;
  76         op_group <= dec_instr.op_group;
  77         op_detail <= dec_instr.op_detail;
  78
  79
  80
  81         alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0');
  82
  83
  84         if reset = RESET_VALUE then
  85                 condition <= COND_NEVER;
  86         else
  87
  88         end if;
  89
  90         reg_nxt.brpr <= alu_nxt.brpr;
  91         reg_nxt.alu_jump <= alu_nxt.alu_jump;
  92         reg_nxt.wr_en <= alu_nxt.reg_op;
  93         reg_nxt.result <= alu_nxt.result;
  94         reg_nxt.res_addr <= alu_nxt.result_addr;
  95
  96 end process asyn;
  97
  98 forward: process(regfile_val, reg_we, reg_addr, dec_instr)
  99 begin
 100         left_operand <= dec_instr.src1;
 101         right_operand <= dec_instr.src2;
 102
 103         if reg_we = '1' then
 104                 if dec_instr.saddr1 = reg_addr then
 105                         left_operand <= regfile_val;
 106                 end if;
 107                 if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
 108                         right_operand <= regfile_val;
 109                 end if;
 110         end if;
 111 end process forward;
 112
 113 result <= reg.result;
 114 result_addr <= reg.res_addr;
 115 alu_jump <= reg.alu_jump;
 116 brpr <= reg.brpr;
 117 wr_en <= reg.wr_en;
 118 dmem <= alu_nxt.mem_op;
 119 --dmem <= reg.result(4);
 120 dmem_write_en <= alu_nxt.mem_en;
 121 --dmem_write_en <= reg.result(0);
 122 --dmem_write_en <= '1';
 123 hword <= alu_nxt.hw_op;
 124 --hword <= reg.result(1);
 125 byte_s <= alu_nxt.byte_op;
 126
 127 --addr <= alu_nxt.result;
 128 --data <= right_operand;
 129 --byte_s <= reg.result(2);
 130 end behav;
 131