cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 -------------------------------------------------------------------------------
   9 -- ENTITY
  10 -------------------------------------------------------------------------------
  11 entity pipeline_tb is
  12
  13 end pipeline_tb;
  14
  15
  16 -------------------------------------------------------------------------------
  17 -- ARCHITECTURE
  18 -------------------------------------------------------------------------------
  19 architecture behavior of pipeline_tb is
  20
  21         constant cc : time := 30 ns;        -- test clock period
  22
  23                 signal sys_clk_pin : std_logic;
  24                 signal sys_res_n_pin : std_logic;
  25                 --Data input
  26
  27                 signal dummy : std_logic;
  28
  29                 signal jump_result_pin : instruction_addr_t;
  30                 signal prediction_result_pin : instruction_addr_t;
  31                 signal branch_prediction_bit_pin : std_logic;
  32                 signal alu_jump_bit_pin : std_logic;
  33                 signal instruction_pin : instruction_word_t;
  34
  35                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  36                 signal reg_wr_data_pin : gp_register_t;
  37                 signal reg_we_pin : std_logic;
  38                 signal to_next_stage_pin : dec_op;
  39
  40 begin
  41
  42 --              instruction_ram : r_w_ram
  43 --              generic map (
  44 --                      PHYS_INSTR_ADDR_WIDTH,
  45 --                      WORD_WIDTH
  46 --              )
  47 --
  48 --              port map (
  49 --                      sys_clk,
  50 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  51 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  52 --                      instr_we,
  53 --                      instr_wr_data,
  54 --                      instr_rd_data
  55 --              );
  56
  57         fetch_st : fetch_stage
  58                 generic map (
  59
  60                         '0',
  61                         '1'
  62                 )
  63
  64                 port map (
  65                 --System inputs
  66                         clk => sys_clk_pin, --: in std_logic;
  67                         reset => sys_res_n_pin, --: in std_logic;
  68
  69                 --Data inputs
  70                         jump_result => jump_result_pin, --: in instruction_addr_t;
  71                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  72                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  73                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  74
  75                 --Data outputs
  76                         instruction => instruction_pin --: out instruction_word_t
  77                 );
  78
  79         decode_st : decode_stage
  80                 generic map (
  81                         -- active reset value
  82                         '0',
  83                         -- active logic value
  84                         '1'
  85
  86                         )
  87                 port map (
  88                 --System inputs
  89                         clk => sys_clk_pin, --: in std_logic;
  90                         reset => sys_res_n_pin, -- : in std_logic;
  91
  92                 --Data inputs
  93                         instruction => instruction_pin, --: in instruction_word_t;
  94                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  95                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
  96                         reg_we => reg_we_pin, --: in std_logic;
  97
  98                 --Data outputs
  99                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 100                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 101                         to_next_stage => to_next_stage_pin
 102
 103                 );
 104
 105
 106
 107 -------------------------------------------------------------------------------
 108 -- generate simulation clock
 109 -------------------------------------------------------------------------------
 110   CLKGEN : process
 111   begin
 112     sys_clk_pin <= '1';
 113     wait for cc/2;
 114     sys_clk_pin <= '0';
 115     wait for cc/2;
 116   end process CLKGEN;
 117
 118 -------------------------------------------------------------------------------
 119 -- test the design
 120 -------------------------------------------------------------------------------
 121   TEST_IT : process
 122
 123     -- wait for n clock cycles
 124     procedure icwait(cycles : natural) is
 125     begin
 126       for i in 1 to cycles loop
 127         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 128       end loop;
 129     end;
 130
 131   begin
 132     -----------------------------------------------------------------------------
 133     -- initial reset
 134     -----------------------------------------------------------------------------
 135         sys_res_n_pin <= '0';
 136         reg_w_addr_pin <= (others => '0');
 137         reg_wr_data_pin <= (others => '0');
 138         reg_we_pin <= '0';
 139
 140         icwait(10);
 141         dummy <= '1';
 142         sys_res_n_pin <= '1';
 143         wait until sys_res_n_pin = '1';
 144
 145
 146         icwait(100000);
 147
 148     ---------------------------------------------------------------------------
 149     -- exit testbench
 150     ---------------------------------------------------------------------------
 151     assert false
 152       report "Test finished"
 153       severity error;
 154
 155   end process test_it;
 156
 157 end behavior;
 158
 159
 160 -------------------------------------------------------------------------------
 161 -- configuration
 162 -------------------------------------------------------------------------------
 163 configuration pipeline_conf_beh of pipeline_tb is
 164   for behavior
 165     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 166     end for;
 167     for decode_st : decode_stage use entity work.decode_stage(behav);
 168     end for;
 169
 170   end for;
 171 end pipeline_conf_beh;