cpu/src/core_top.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 entity core_top is
   9
  10         port(
  11                 --System input pins
  12                         sys_clk : in std_logic;
  13                         sys_res : in std_logic;
  14
  15                         to_next_stage : out dec_op
  16
  17                 );
  18
  19 end core_top;
  20
  21 architecture behav of core_top is
  22
  23                 signal jump_result_pin : instruction_addr_t;
  24                 signal prediction_result_pin : instruction_addr_t;
  25                 signal branch_prediction_bit_pin : std_logic;
  26                 signal alu_jump_bit_pin : std_logic;
  27                 signal instruction_pin : instruction_word_t;
  28
  29                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  30                 signal reg_wr_data_pin : gp_register_t;
  31                 signal reg_we_pin : std_logic;
  32
  33 --              signal reg1_rd_data_pin : gp_register_t;
  34 --              signal reg2_rd_data_pin : gp_register_t;
  35
  36
  37 begin
  38
  39         fetch_st : fetch_stage
  40                 generic map (
  41
  42                         '0',
  43                         '1'
  44                 )
  45
  46                 port map (
  47                 --System inputs
  48                         clk => sys_clk, --: in std_logic;
  49                         reset => sys_res, --: in std_logic;
  50
  51                 --Data inputs
  52                         jump_result => jump_result_pin, --: in instruction_addr_t;
  53                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  54                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  55                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  56
  57                 --Data outputs
  58                         instruction => instruction_pin --: out instruction_word_t
  59                 );
  60
  61         decode_st : decode_stage
  62                 generic map (
  63                         -- active reset value
  64                         '0',
  65                         -- active logic value
  66                         '1'
  67
  68                         )
  69                 port map (
  70                 --System inputs
  71                         clk => sys_clk, --: in std_logic;
  72                         reset => sys_res, -- : in std_logic;
  73
  74                 --Data inputs
  75                         instruction => instruction_pin, --: in instruction_word_t;
  76                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  77                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
  78                         reg_we => reg_we_pin, --: in std_logic;
  79
  80                 --Data outputs
  81                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
  82                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
  83                         to_next_stage => to_next_stage
  84                 );
  85
  86
  87 --init : process(all)
  88
  89 --begin
  90         jump_result_pin <= (others => '0');
  91         alu_jump_bit_pin <= '0';
  92         reg_w_addr_pin <= (others => '0');
  93         reg_wr_data_pin <= (others => '0');
  94         reg_we_pin <= '0';
  95
  96 --end process;
  97
  98
  99 end behav;