cpu/sim/testcore.do

   1 vlib work
   2 vmap work work
   3
   4 vcom -work work ../src/mem_pkg.vhd
   5 vcom -work work ../src/r_w_ram.vhd
   6 vcom -work work ../src/r_w_ram_b.vhd
   7 vcom -work work ../src/r2_w_ram.vhd
   8 vcom -work work ../src/r2_w_ram_b.vhd
   9 vcom -work work ../src/common_pkg.vhd
  10 vcom -work work ../src/core_pkg.vhd
  11 vcom -work work ../src/decoder.vhd
  12 vcom -work work ../src/decoder_b.vhd
  13 vcom -work work ../src/fetch_stage.vhd
  14 vcom -work work ../src/fetch_stage_b.vhd
  15 vcom -work work ../src/decode_stage.vhd
  16 vcom -work work ../src/decode_stage_b.vhd
  17 vcom -work work ../src/pipeline_tb.vhd
  18
  19 vsim work.pipeline_conf_beh -t ns
  20
  21 add wave  -format logic /pipeline_tb/sys_clk_pin
  22 add wave  -format logic /pipeline_tb/sys_res_n_pin
  23 add wave  -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
  24 add wave  -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
  25 add wave  -format logic /pipeline_tb/fetch_st/branch_prediction_bit
  26 add wave  -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
  27
  28 add wave  -radix hexadecimal /pipeline_tb/decode_st/instruction
  29 add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
  30 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
  31 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
  32 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
  33 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
  34 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
  35 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_we
  36
  37 run 500000 ns