2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
8 -------------------------------------------------------------------------------
10 -------------------------------------------------------------------------------
16 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 architecture behavior of pipeline_tb is
21 constant cc : time := 30 ns; -- test clock period
23 signal sys_clk_pin : std_logic;
24 signal sys_res_n_pin : std_logic;
27 signal dummy : std_logic;
29 signal jump_result_pin : instruction_addr_t;
30 signal prediction_result_pin : instruction_addr_t;
31 signal branch_prediction_bit_pin : std_logic;
32 signal alu_jump_bit_pin : std_logic;
33 signal instruction_pin : instruction_word_t;
35 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
36 signal reg_wr_data_pin : gp_register_t;
37 signal reg_we_pin : std_logic;
38 signal reg1_rd_data_pin : gp_register_t;
39 signal reg2_rd_data_pin : gp_register_t;
44 -- instruction_ram : r_w_ram
46 -- PHYS_INSTR_ADDR_WIDTH,
52 -- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
53 -- instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
59 fetch_st : fetch_stage
68 clk => sys_clk_pin, --: in std_logic;
69 reset => sys_res_n_pin, --: in std_logic;
72 jump_result => jump_result_pin, --: in instruction_addr_t;
73 prediction_result => prediction_result_pin, --: in instruction_addr_t;
74 branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
75 alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
78 instruction => instruction_pin --: out instruction_word_t
81 decode_st : decode_stage
91 clk => sys_clk_pin, --: in std_logic;
92 reset => sys_res_n_pin, -- : in std_logic;
95 instruction => instruction_pin, --: in instruction_word_t;
96 reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
97 reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
98 reg_we => reg_we_pin, --: in std_logic;
101 reg1_rd_data => reg1_rd_data_pin, --: gp_register_t;
102 reg2_rd_data => reg2_rd_data_pin, --: gp_register_t;
103 branch_prediction_res => prediction_result_pin, --: instruction_word_t;
104 branch_prediction_bit => branch_prediction_bit_pin --: std_logic
110 -------------------------------------------------------------------------------
111 -- generate simulation clock
112 -------------------------------------------------------------------------------
121 -------------------------------------------------------------------------------
123 -------------------------------------------------------------------------------
126 -- wait for n clock cycles
127 procedure icwait(cycles : natural) is
129 for i in 1 to cycles loop
130 wait until sys_clk_pin = '1' and sys_clk_pin'event;
135 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
138 sys_res_n_pin <= '0';
139 reg_w_addr_pin <= (others => '0');
140 reg_wr_data_pin <= (others => '0');
145 sys_res_n_pin <= '1';
146 wait until sys_res_n_pin = '1';
151 ---------------------------------------------------------------------------
153 ---------------------------------------------------------------------------
155 report "Test finished"
163 -------------------------------------------------------------------------------
165 -------------------------------------------------------------------------------
166 configuration pipeline_conf_beh of pipeline_tb is
168 for fetch_st : fetch_stage use entity work.fetch_stage(behav);
170 for decode_st : decode_stage use entity work.decode_stage(behav);
174 end pipeline_conf_beh;