1951c5f20c0e87f4227ff65102623a4b22cbc0ad
[calu.git] / cpu / sim / testcore.do
1 vlib work
2 vmap work work
3
4 vcom -work work ../src/mem_pkg.vhd
5 vcom -work work ../src/r_w_ram.vhd
6 vcom -work work ../src/r_w_ram_b.vhd
7 vcom -work work ../src/r_w_ram_be.vhd
8 vcom -work work ../src/r_w_ram_be_b.vhd
9 vcom -work work ../src/r2_w_ram.vhd
10 vcom -work work ../src/r2_w_ram_b.vhd
11 vcom -work work ../src/rom.vhd
12 vcom -work work ../src/rom_b.vhd
13 vcom -work work ../src/common_pkg.vhd
14 vcom -work work ../src/extension_pkg.vhd
15 vcom -work work ../src/core_pkg.vhd
16 vcom -work work ../src/extension_uart_pkg.vhd
17 vcom -work work ../src/extension_uart.vhd
18 vcom -work work ../src/extension_uart_b.vhd
19 vcom -work work ../src/extension_7seg_pkg.vhd
20 vcom -work work ../src/extension_7seg.vhd
21 vcom -work work ../src/extension_7seg_b.vhd
22 vcom -work work ../src/rs232_tx.vhd
23 vcom -work work ../src/rs232_tx_arc.vhd
24 vcom -work work ../src/rs232_rx.vhd
25 vcom -work work ../src/rs232_rx_arc.vhd
26
27 vcom -work work ../src/decoder.vhd
28 vcom -work work ../src/decoder_b.vhd
29 vcom -work work ../src/fetch_stage.vhd
30 vcom -work work ../src/fetch_stage_b.vhd
31 vcom -work work ../src/decode_stage.vhd
32 vcom -work work ../src/decode_stage_b.vhd
33
34 vcom -work work ../src/alu_pkg.vhd
35 vcom -work work ../src/extension_pkg.vhd
36
37 vcom -work work ../src/exec_op.vhd
38 vcom -work work ../src/exec_op/add_op_b.vhd
39 vcom -work work ../src/exec_op/and_op_b.vhd
40 vcom -work work ../src/exec_op/or_op_b.vhd
41 vcom -work work ../src/exec_op/xor_op_b.vhd
42 vcom -work work ../src/exec_op/shift_op_b.vhd
43
44 vcom -work work ../src/alu.vhd
45 vcom -work work ../src/alu_b.vhd
46 vcom -work work ../src/extension_pkg.vhd
47 #vcom -work work ../src/gpm_pkg.vhd
48
49 #vcom -work work ../src/gpm.vhd
50 #vcom -work work ../src/gpm_b.vhd
51
52 vcom -work work ../src/extension.vhd
53 vcom -work work ../src/extension_b.vhd
54
55 vcom -work work ../src/execute_stage.vhd
56 vcom -work work ../src/execute_stage_b.vhd
57
58
59 vcom -work work ../src/writeback_stage.vhd
60 vcom -work work ../src/writeback_stage_b.vhd
61
62 vcom -work work ../src/pipeline_tb.vhd
63
64 vsim work.pipeline_conf_beh -t ns
65
66 add wave  -format logic /pipeline_tb/sys_clk_pin
67 add wave  -format logic /pipeline_tb/sys_res_n_pin
68 add wave  -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr
69 add wave  -radix hexadecimal /pipeline_tb/fetch_st/instr_r_addr_nxt
70 add wave  -format logic /pipeline_tb/fetch_st/branch_prediction_bit
71 add wave  -radix hexadecimal /pipeline_tb/fetch_st/prediction_result
72
73 add wave  -radix hexadecimal /pipeline_tb/decode_st/instruction
74 add wave  -radix hexadecimal /pipeline_tb/decode_st/instr_spl
75 add wave  -radix hexadecimal /pipeline_tb/decode_st/to_next_stage
76 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg1_mem_data
77 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg2_mem_data
78 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec_nxt
79 add wave  -radix hexadecimal /pipeline_tb/decode_st/rtw_rec
80 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_w_addr
81 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_wr_data
82 add wave  -radix hexadecimal /pipeline_tb/decode_st/reg_we
83
84 add wave  -radix hexadecimal /pipeline_tb/exec_st/gpmp_inst/psw
85
86 add wave  -radix hexadecimal /pipeline_tb/addr_pin
87 add wave  -radix hexadecimal /pipeline_tb/data_pin
88 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
89 add wave  -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
90 add wave  -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
91 add wave  -radix hexadecimal /pipeline_tb/writeback_st/data_addr
92
93 add wave  -radix hexadecimal /pipeline_tb/tx_pin
94 add wave  -radix hexadecimal /pipeline_tb/rx_pin
95
96 add wave  -radix decimal     /pipeline_tb/cycle_cnt
97
98 run 10000 ns