cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17 signal rx_data : std_logic_vector(7 downto 0);
  18
  19 signal uart_int_nxt : std_logic;
  20
  21 signal uart_data_read, uart_data_read_nxt : std_logic;
  22
  23 begin
  24
  25
  26 rs232_tx_inst : rs232_tx
  27 generic map(
  28                 RESET_VALUE
  29                 )
  30 port map(
  31         --System inputs
  32         clk,
  33         reset,
  34
  35         --Bus
  36         bus_tx,
  37
  38         --From/to sendlogic
  39         new_tx_data,
  40         w3_uart_send(byte_t'range),
  41         tx_rdy,
  42         bd_rate,
  43         w1_st_co(0)
  44 );
  45
  46 rs232_rx_inst : rs232_rx
  47 generic map(
  48                 RESET_VALUE,
  49                 2
  50                 )
  51 port map(
  52         --System inputs
  53         clk,
  54         reset,
  55
  56         --Bus
  57         bus_rx,
  58
  59         --From/to sendlogic
  60         new_bus_rx,
  61         rx_data,
  62         bd_rate
  63 );
  64
  65
  66
  67
  68 syn : process (clk, reset)
  69 begin
  70    if (reset = RESET_VALUE) then
  71                         w1_st_co <= (others=>'0');
  72                         w2_uart_config(31 downto 16) <= (others=>'0');
  73                         -- todo mit einer konstante versehen
  74                         w2_uart_config(15 downto 0) <= x"01B2";
  75                         w3_uart_send <= (others=>'0');
  76                         w4_uart_receive <= (others=>'0');
  77                         tx_rdy_int <= '0';
  78                         new_tx_data <= '0';
  79                         uart_data_read <= '0';
  80                         uart_int <= '0';
  81
  82         elsif rising_edge(clk) then
  83                         w1_st_co <= w1_st_co_nxt;
  84                         w2_uart_config <= w2_uart_config_nxt;
  85                         w3_uart_send <= w3_uart_send_nxt;
  86                         w4_uart_receive <= w4_uart_receive_nxt;
  87                         new_tx_data <= new_tx_data_nxt;
  88                         tx_rdy_int <= tx_rdy;
  89                         uart_data_read <= uart_data_read_nxt;
  90                         uart_int <= uart_int_nxt;
  91    end if;
  92 end process syn;
  93
  94 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  95
  96 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
  97
  98 variable tmp_data  : gp_register_t;
  99
 100 begin
 101                 uart_int_nxt <= '0';
 102                 w1_st_co_nxt <= w1_st_co;
 103                 w2_uart_config_nxt <= w2_uart_config;
 104                 w3_uart_send_nxt <= w3_uart_send;
 105                 w4_uart_receive_nxt <= w4_uart_receive;
 106
 107         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 108                 tmp_data := (others =>'0');
 109                 if ext_reg.byte_en(0) = '1' then
 110                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
 111                 end if;
 112                 if ext_reg.byte_en(1) = '1' then
 113                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
 114                 end if;
 115                 if ext_reg.byte_en(2) = '1' then
 116                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
 117                 end if;
 118                 if ext_reg.byte_en(3) = '1' then
 119                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
 120                 end if;
 121
 122                 case ext_reg.addr(1 downto 0) is
 123                 when "00" =>
 124                         w1_st_co_nxt <= tmp_data;
 125                 when "01" =>
 126                         w2_uart_config_nxt <= tmp_data;
 127                 when "10" =>
 128                         w1_st_co_nxt(16) <= '1'; -- busy flag set
 129                         w3_uart_send_nxt <= tmp_data;
 130                 when "11" =>
 131                         --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
 132                 when others => null;
 133                 end case;
 134         end if;
 135
 136         if  tx_rdy = '1' and tx_rdy_int = '0' then
 137                 w1_st_co_nxt(16) <= '0'; -- busy flag reset
 138         end if;
 139
 140         if new_bus_rx = '1' then
 141                 w4_uart_receive_nxt(7 downto 0) <= rx_data;
 142                 w1_st_co_nxt(17) <= '1';
 143                 uart_int_nxt <= '1';
 144         end if;
 145
 146         if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
 147                 w1_st_co_nxt(17) <= '0';
 148         end if;
 149
 150 end process gwriten;
 151
 152 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 153
 154 variable tmp_data  : gp_register_t;
 155
 156 begin
 157
 158         uart_data_read_nxt <= '0';
 159
 160         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 161                 case ext_reg.addr(1 downto 0) is
 162                 when "00" =>
 163                         tmp_data := (others =>'0');
 164                         if ext_reg.byte_en(0) = '1' then
 165                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 166                         end if;
 167                         if ext_reg.byte_en(1) = '1' then
 168                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 169                         end if;
 170                         if ext_reg.byte_en(2) = '1' then
 171                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 172                         end if;
 173                         if ext_reg.byte_en(3) = '1' then
 174                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 175                         end if;
 176                         data_out <= tmp_data;
 177                 when "01" =>
 178                         tmp_data := (others =>'0');
 179                         if ext_reg.byte_en(0) = '1' then
 180                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 181                         end if;
 182                         if ext_reg.byte_en(1) = '1' then
 183                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 184                         end if;
 185                         if ext_reg.byte_en(2) = '1' then
 186                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 187                         end if;
 188                         if ext_reg.byte_en(3) = '1' then
 189                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 190                         end if;
 191                         data_out <= tmp_data;
 192                 when "10" =>
 193                         tmp_data := (others =>'0');
 194                         if ext_reg.byte_en(0) = '1' then
 195                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 196                         end if;
 197                         if ext_reg.byte_en(1) = '1' then
 198                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 199                         end if;
 200                         if ext_reg.byte_en(2) = '1' then
 201                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 202                         end if;
 203                         if ext_reg.byte_en(3) = '1' then
 204                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 205                         end if;
 206                         data_out <= tmp_data;
 207                 when "11" =>
 208                         tmp_data := (others =>'0');
 209                         uart_data_read_nxt <= '1';
 210                         if ext_reg.byte_en(0) = '1' then
 211                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 212                         end if;
 213                         if ext_reg.byte_en(1) = '1' then
 214                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 215                         end if;
 216                         if ext_reg.byte_en(2) = '1' then
 217                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 218                         end if;
 219                         if ext_reg.byte_en(3) = '1' then
 220                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 221                         end if;
 222                         data_out <= tmp_data;
 223                 when others => null;
 224                 end case;
 225         else
 226                 data_out  <= (others=>'0');
 227         end if;
 228 end process gread;
 229
 230
 231 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 232
 233 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 234
 235 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 236
 237
 238 begin
 239
 240         new_tx_data_nxt <= '0';
 241         bd_rate <= w2_uart_config(15 downto 0);
 242
 243         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 244                 case ext_reg.addr(1 downto 0) is
 245                 when "00" =>
 246
 247                 when "01" =>
 248
 249                 when "10" =>
 250                         new_tx_data_nxt <= '1';
 251                 when "11" =>
 252
 253                 when others => null;
 254                 end case;
 255         end if;
 256
 257 end process dataprocess;
 258
 259
 260
 261 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 262
 263 end behav;
 264