cpu/src/extension_uart_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7
   8 use work.mem_pkg.all;
   9 use work.extension_pkg.all;
  10 use work.extension_uart_pkg.all;
  11
  12 architecture behav of extension_uart is
  13
  14 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
  15 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
  16 signal  bd_rate : baud_rate_l;
  17 signal rx_data : std_logic_vector(7 downto 0);
  18
  19 signal uart_data_read, uart_data_read_nxt : std_logic;
  20
  21 begin
  22
  23
  24 rs232_tx_inst : rs232_tx
  25 generic map(
  26                 RESET_VALUE
  27                 )
  28 port map(
  29         --System inputs
  30         clk,
  31         reset,
  32
  33         --Bus
  34         bus_tx,
  35
  36         --From/to sendlogic
  37         new_tx_data,
  38         w3_uart_send(byte_t'range),
  39         tx_rdy,
  40         bd_rate,
  41         w1_st_co(0)
  42 );
  43
  44 rs232_rx_inst : rs232_rx
  45 generic map(
  46                 RESET_VALUE,
  47                 2
  48                 )
  49 port map(
  50         --System inputs
  51         clk,
  52         reset,
  53
  54         --Bus
  55         bus_rx,
  56
  57         --From/to sendlogic
  58         new_bus_rx,
  59         rx_data,
  60         bd_rate
  61 );
  62
  63
  64
  65
  66 syn : process (clk, reset)
  67 begin
  68    if (reset = RESET_VALUE) then
  69                         w1_st_co <= (others=>'0');
  70                         w2_uart_config(31 downto 16) <= (others=>'0');
  71                         -- todo mit einer konstante versehen
  72                         w2_uart_config(15 downto 0) <= x"01B2";
  73                         w3_uart_send <= (others=>'0');
  74                         w4_uart_receive <= (others=>'0');
  75                         tx_rdy_int <= '0';
  76                         new_tx_data <= '0';
  77                         uart_data_read <= '0';
  78
  79         elsif rising_edge(clk) then
  80                         w1_st_co <= w1_st_co_nxt;
  81                         w2_uart_config <= w2_uart_config_nxt;
  82                         w3_uart_send <= w3_uart_send_nxt;
  83                         w4_uart_receive <= w4_uart_receive_nxt;
  84                         new_tx_data <= new_tx_data_nxt;
  85                         tx_rdy_int <= tx_rdy;
  86                         uart_data_read <= uart_data_read_nxt;
  87    end if;
  88 end process syn;
  89
  90 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
  91
  92 gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
  93
  94 variable tmp_data  : gp_register_t;
  95
  96 begin
  97
  98                 w1_st_co_nxt <= w1_st_co;
  99                 w2_uart_config_nxt <= w2_uart_config;
 100                 w3_uart_send_nxt <= w3_uart_send;
 101                 w4_uart_receive_nxt <= w4_uart_receive;
 102
 103         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 104                 tmp_data := (others =>'0');
 105                 if ext_reg.byte_en(0) = '1' then
 106                         tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
 107                 end if;
 108                 if ext_reg.byte_en(1) = '1' then
 109                         tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
 110                 end if;
 111                 if ext_reg.byte_en(2) = '1' then
 112                         tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
 113                 end if;
 114                 if ext_reg.byte_en(3) = '1' then
 115                         tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
 116                 end if;
 117
 118                 case ext_reg.addr(1 downto 0) is
 119                 when "00" =>
 120                         w1_st_co_nxt <= tmp_data;
 121                 when "01" =>
 122                         w2_uart_config_nxt <= tmp_data;
 123                 when "10" =>
 124                         w1_st_co_nxt(16) <= '1'; -- busy flag set
 125                         w3_uart_send_nxt <= tmp_data;
 126                 when "11" =>
 127                         --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
 128                 when others => null;
 129                 end case;
 130         end if;
 131
 132         if  tx_rdy = '1' and tx_rdy_int = '0' then
 133                 w1_st_co_nxt(16) <= '0'; -- busy flag reset
 134         end if;
 135
 136         if new_bus_rx = '1' then
 137                 w4_uart_receive_nxt(7 downto 0) <= rx_data;
 138                 w1_st_co_nxt(17) <= '1';
 139         end if;
 140
 141         if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
 142                 w1_st_co_nxt(17) <= '0';
 143         end if;
 144
 145 end process gwriten;
 146
 147 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
 148
 149 variable tmp_data  : gp_register_t;
 150
 151 begin
 152
 153         uart_data_read_nxt <= '0';
 154
 155         if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
 156                 case ext_reg.addr(1 downto 0) is
 157                 when "00" =>
 158                         tmp_data := (others =>'0');
 159                         if ext_reg.byte_en(0) = '1' then
 160                                 tmp_data(byte_t'range) := w1_st_co(byte_t'range);
 161                         end if;
 162                         if ext_reg.byte_en(1) = '1' then
 163                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
 164                         end if;
 165                         if ext_reg.byte_en(2) = '1' then
 166                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
 167                         end if;
 168                         if ext_reg.byte_en(3) = '1' then
 169                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
 170                         end if;
 171                         data_out <= tmp_data;
 172                 when "01" =>
 173                         tmp_data := (others =>'0');
 174                         if ext_reg.byte_en(0) = '1' then
 175                                 tmp_data(byte_t'range) := w2_uart_config(byte_t'range);
 176                         end if;
 177                         if ext_reg.byte_en(1) = '1' then
 178                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_uart_config((2*byte_t'length-1) downto byte_t'length);
 179                         end if;
 180                         if ext_reg.byte_en(2) = '1' then
 181                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_uart_config((3*byte_t'length-1) downto 2*byte_t'length);
 182                         end if;
 183                         if ext_reg.byte_en(3) = '1' then
 184                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_uart_config((4*byte_t'length-1) downto 3*byte_t'length);
 185                         end if;
 186                         data_out <= tmp_data;
 187                 when "10" =>
 188                         tmp_data := (others =>'0');
 189                         if ext_reg.byte_en(0) = '1' then
 190                                 tmp_data(byte_t'range) := w3_uart_send(byte_t'range);
 191                         end if;
 192                         if ext_reg.byte_en(1) = '1' then
 193                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_uart_send((2*byte_t'length-1) downto byte_t'length);
 194                         end if;
 195                         if ext_reg.byte_en(2) = '1' then
 196                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_uart_send((3*byte_t'length-1) downto 2*byte_t'length);
 197                         end if;
 198                         if ext_reg.byte_en(3) = '1' then
 199                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_uart_send((4*byte_t'length-1) downto 3*byte_t'length);
 200                         end if;
 201                         data_out <= tmp_data;
 202                 when "11" =>
 203                         tmp_data := (others =>'0');
 204                         uart_data_read_nxt <= '1';
 205                         if ext_reg.byte_en(0) = '1' then
 206                                 tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
 207                         end if;
 208                         if ext_reg.byte_en(1) = '1' then
 209                                 tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_uart_receive((2*byte_t'length-1) downto byte_t'length);
 210                         end if;
 211                         if ext_reg.byte_en(2) = '1' then
 212                                 tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_uart_receive((3*byte_t'length-1) downto 2*byte_t'length);
 213                         end if;
 214                         if ext_reg.byte_en(3) = '1' then
 215                                 tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_uart_receive((4*byte_t'length-1) downto 3*byte_t'length);
 216                         end if;
 217                         data_out <= tmp_data;
 218                 when others => null;
 219                 end case;
 220         else
 221                 data_out  <= (others=>'0');
 222         end if;
 223 end process gread;
 224
 225
 226 -------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
 227
 228 -------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
 229
 230 dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
 231
 232
 233 begin
 234
 235         new_tx_data_nxt <= '0';
 236         bd_rate <= w2_uart_config(15 downto 0);
 237
 238         if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
 239                 case ext_reg.addr(1 downto 0) is
 240                 when "00" =>
 241
 242                 when "01" =>
 243
 244                 when "10" =>
 245                         new_tx_data_nxt <= '1';
 246                 when "11" =>
 247
 248                 when others => null;
 249                 end case;
 250         end if;
 251
 252 end process dataprocess;
 253
 254
 255
 256 -------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
 257
 258 end behav;
 259