bugfix in fetch

diff --git a/cpu/create_project.tcl b/cpu/create_project.tcl
index c2dc47b0e9dba54033faef02ede2f623af9d6c68..2ffd7d390f03ea453343a6b4f6ce0ffb78a930f6 100755 (executable)
--- a/cpu/create_project.tcl
+++ b/cpu/create_project.tcl
@@ -36,6 +36,8 @@ if {$make_assignments} {
        set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
        set_global_assignment -name VHDL_FILE ../src/rom.vhd
        set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
        set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
        set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
        set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd

diff --git a/cpu/cyc1.tcl b/cpu/cyc1.tcl
index a0951bbf510a8b0556791356a23fd01b116923e6..a6189e7b5c67519aaaa15de7ba170d5ffd2ebfa4 100644 (file)
--- a/cpu/cyc1.tcl
+++ b/cpu/cyc1.tcl
@@ -14,7 +14,7 @@
 
 # Quartus II: Generate Tcl File for Project
 # File: cyc1.tcl
-# Generated on: Mon Dec 20 23:24:35 2010
+# Generated on: Thu Dec 23 21:48:06 2010
 
 # Load Quartus II Tcl Project package
 package require ::quartus::project
@@ -48,65 +48,77 @@ if {$make_assignments} {
        set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
        set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
        set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
-       set_global_assignment -name USE_CONFIGURATION_DEVICE ON
        set_global_assignment -name GENERATE_RBF_FILE ON
        set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
        set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
        set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
        set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+       set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+       set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+       set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
+       set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+       set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+       set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+       set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+       set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+       set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+       set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+       set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+       set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+       set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
        set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
        set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
        set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
        set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
        set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-       set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-       set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
-       set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
+       set_global_assignment -name VHDL_FILE ../src/rom.vhd
+       set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
+       set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/rw_r_ram_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/rw_r_ram.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
+       set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
+       set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
+       set_global_assignment -name VHDL_FILE ../src/pipeline_tb.vhd
+       set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/extension.vhd
+       set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
+       set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/decoder.vhd
+       set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
+       set_global_assignment -name VHDL_FILE ../src/core_top.vhd
+       set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
+       set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/alu.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
+       set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
        set_global_assignment -name SMART_RECOMPILE ON
-       set_global_assignment -name ENABLE_DRC_SETTINGS ON
        set_global_assignment -name ENABLE_CLOCK_LATENCY ON
        set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
        set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
@@ -114,15 +126,10 @@ if {$make_assignments} {
        set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
        set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
        set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
-       set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
        set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
-       set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
        set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
-       set_global_assignment -name MUX_RESTRUCTURE OFF
-       set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-       set_location_assignment PIN_42 -to sys_res
-       set_location_assignment PIN_166 -to bus_tx
        set_location_assignment PIN_152 -to sys_clk
+       set_location_assignment PIN_42 -to sys_res
        set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
        # Commit assignments

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index a7374face2fa6497cad465f36a972af0acf01fcf..c79541bae71caca087c017026557b9fa9dc772e6 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -185,7 +185,7 @@ begin
                        pinc_v := '1';
                        res_prod := '0';
                        addr <= pval_nxt;
-                       data <= left_o;
+                       data <= left_operand;
                else
                        addr <= std_logic_vector(unsigned(pval_nxt)-4);
                end if;

diff --git a/cpu/src/extension_pkg.vhd b/cpu/src/extension_pkg.vhd
index 35c13d747ce60614c6c12cb5c2f344294e616f4d..c61266cebcea3344414de7088e0a060a344c43eb 100644 (file)
--- a/cpu/src/extension_pkg.vhd
+++ b/cpu/src/extension_pkg.vhd
@@ -42,7 +42,7 @@ constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
 constant EXT_UART_ADDR:   ext_addrid_t := x"0000200";
 constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
 
- component extension_gpm is
+component extension_gpm is
         --some modules won't need all inputs/outputs
        generic (
                        -- active reset value

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index 1ff0fad814872a115dcfba8b1fd80baa0a1bdb4d..cdc6dc6a018f58b578a1759ccd5a110b462af13c 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -77,7 +77,7 @@ begin
        end case;
        instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
 
-       if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1') then
+       if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1' and rom_ram = ROM_USE) then
                rom_ram_nxt <= RAM_USE;
                instr_r_addr_nxt <= (others => '0');
        end if;