cpu/src/pipeline_tb.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.core_pkg.all;
   7 -------------------------------------------------------------------------------
   8 -- ENTITY
   9 -------------------------------------------------------------------------------
  10 entity pipeline_tb is
  11
  12 end pipeline_tb;
  13
  14
  15 -------------------------------------------------------------------------------
  16 -- ARCHITECTURE
  17 -------------------------------------------------------------------------------
  18 architecture behavior of pipeline_tb is
  19
  20         constant cc : time := 30 ns;        -- test clock period
  21
  22                 signal sys_clk_pin : std_logic;
  23                 signal sys_res_n_pin : std_logic;
  24                 --Data input
  25
  26                 signal dummy : std_logic;
  27
  28                 signal jump_result_pin : instruction_addr_t;
  29                 signal prediction_result_pin : instruction_addr_t;
  30                 signal branch_prediction_bit_pin : std_logic;
  31                 signal alu_jump_bit_pin : std_logic;
  32                 signal instruction_pin : instruction_word_t;
  33
  34                 signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
  35                 signal reg_wr_data_pin : gp_register_t;
  36                 signal reg_we_pin : std_logic;
  37                 signal to_next_stage_pin : dec_op;
  38
  39                  signal result_pin : gp_register_t;--reg
  40                  signal result_addr_pin : gp_addr_t;--reg
  41                  signal addr_pin : word_t; --memaddr
  42                  signal data_pin : gp_register_t; --mem data --ureg
  43                  signal alu_jump_pin : std_logic;--reg
  44                  signal brpr_pin  : std_logic;  --reg
  45                  signal wr_en_pin : std_logic;--regop --reg
  46                  signal dmem_pin  : std_logic;--memop
  47                  signal dmem_wr_en_pin : std_logic;
  48                  signal hword_pin  : std_logic;
  49                  signal byte_s_pin : std_logic;
  50                  signal nop_pin : std_logic;
  51
  52 begin
  53
  54 --              instruction_ram : r_w_ram
  55 --              generic map (
  56 --                      PHYS_INSTR_ADDR_WIDTH,
  57 --                      WORD_WIDTH
  58 --              )
  59 --
  60 --              port map (
  61 --                      sys_clk,
  62 --                      instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  63 --                      instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
  64 --                      instr_we,
  65 --                      instr_wr_data,
  66 --                      instr_rd_data
  67 --              );
  68
  69         fetch_st : fetch_stage
  70                 generic map (
  71
  72                         '0',
  73                         '1'
  74                 )
  75
  76                 port map (
  77                 --System inputs
  78                         clk => sys_clk_pin, --: in std_logic;
  79                         reset => sys_res_n_pin, --: in std_logic;
  80
  81                 --Data inputs
  82                         jump_result => jump_result_pin, --: in instruction_addr_t;
  83                         prediction_result => prediction_result_pin, --: in instruction_addr_t;
  84                         branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
  85                         alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
  86
  87                 --Data outputs
  88                         instruction => instruction_pin --: out instruction_word_t
  89                 );
  90
  91         decode_st : decode_stage
  92                 generic map (
  93                         -- active reset value
  94                         '0',
  95                         -- active logic value
  96                         '1'
  97
  98                         )
  99                 port map (
 100                 --System inputs
 101                         clk => sys_clk_pin, --: in std_logic;
 102                         reset => sys_res_n_pin, -- : in std_logic;
 103
 104                 --Data inputs
 105                         instruction => instruction_pin, --: in instruction_word_t;
 106                         reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
 107                         reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
 108                         reg_we => reg_we_pin, --: in std_logic;
 109                         nop => nop_pin,
 110
 111                 --Data outputs
 112                         branch_prediction_res => prediction_result_pin, --: instruction_word_t;
 113                         branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
 114                         to_next_stage => to_next_stage_pin
 115
 116                 );
 117           exec_st : execute_stage
 118                 generic map('0')
 119                 port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin,
 120                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
 121
 122           writeback_st : writeback_stage
 123                 generic map('0', '1')
 124                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
 125                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
 126                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 127
 128
 129         nop_pin <= (alu_jump_bit_pin xor brpr_pin);
 130
 131 -------------------------------------------------------------------------------
 132 -- generate simulation clock
 133 -------------------------------------------------------------------------------
 134   CLKGEN : process
 135   begin
 136     sys_clk_pin <= '1';
 137     wait for cc/2;
 138     sys_clk_pin <= '0';
 139     wait for cc/2;
 140   end process CLKGEN;
 141
 142 -------------------------------------------------------------------------------
 143 -- test the design
 144 -------------------------------------------------------------------------------
 145   TEST_IT : process
 146
 147     -- wait for n clock cycles
 148     procedure icwait(cycles : natural) is
 149     begin
 150       for i in 1 to cycles loop
 151         wait until sys_clk_pin = '1' and sys_clk_pin'event;
 152       end loop;
 153     end;
 154
 155   begin
 156     -----------------------------------------------------------------------------
 157     -- initial reset
 158     -----------------------------------------------------------------------------
 159         sys_res_n_pin <= '0';
 160 --      reg_w_addr_pin <= (others => '0');
 161 --      reg_wr_data_pin <= (others => '0');
 162 --      reg_we_pin <= '0';
 163
 164         icwait(10);
 165         dummy <= '1';
 166         sys_res_n_pin <= '1';
 167         wait until sys_res_n_pin = '1';
 168
 169
 170         icwait(100000);
 171
 172     ---------------------------------------------------------------------------
 173     -- exit testbench
 174     ---------------------------------------------------------------------------
 175     assert false
 176       report "Test finished"
 177       severity error;
 178
 179   end process test_it;
 180
 181 end behavior;
 182
 183
 184 -------------------------------------------------------------------------------
 185 -- configuration
 186 -------------------------------------------------------------------------------
 187 configuration pipeline_conf_beh of pipeline_tb is
 188   for behavior
 189     for fetch_st : fetch_stage use entity work.fetch_stage(behav);
 190     end for;
 191     for decode_st : decode_stage use entity work.decode_stage(behav);
 192     end for;
 193     for exec_st : execute_stage use entity work.execute_stage(behav);
 194     end for;
 195     for writeback_st : writeback_stage use entity work.writeback_stage(behav);
 196     end for;
 197
 198   end for;
 199 end pipeline_conf_beh;