3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
8 architecture behaviour of r_w_ram is
10 subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
11 type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
13 signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000", -- r0 = r3 + r2 (always)
14 1 => "11100101000000001000100000000010", -- r0 = r1 << 0 (always)
15 2 => "11100000000010000001100000000000", -- r1 = r0 + r3 (always)
16 3 => "11100000101000000001000000000000",
17 4 => "11100001000110010111011001101100",
18 others => x"F0000000");
23 if rising_edge(clk) then
24 data_out <= ram(to_integer(UNSIGNED(rd_addr)));
27 ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
31 end architecture behaviour;