From 381f0449828b8451fbbe78878816a6156b078bf6 Mon Sep 17 00:00:00 2001 From: Stefan Rebernig Date: Tue, 16 Nov 2010 08:31:53 +0100 Subject: [PATCH] nop insertion added --- cpu/src/core_pkg.vhd | 1 + cpu/src/core_top.vhd | 3 +++ cpu/src/decode_stage.vhd | 1 + cpu/src/decoder_b.vhd | 3 +++ cpu/src/pipeline_tb.vhd | 3 +++ cpu/src/r2_w_ram_b.vhd | 2 +- cpu/src/r_w_ram_b.vhd | 2 +- 7 files changed, 13 insertions(+), 2 deletions(-) diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd index 13ac382..b613dcb 100644 --- a/cpu/src/core_pkg.vhd +++ b/cpu/src/core_pkg.vhd @@ -52,6 +52,7 @@ package core_pkg is reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data : in gp_register_t; reg_we : in std_logic; + nop : in std_logic; --Data outputs -- reg1_rd_data : out gp_register_t; diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd index f146d8d..7a60407 100644 --- a/cpu/src/core_top.vhd +++ b/cpu/src/core_top.vhd @@ -44,6 +44,7 @@ architecture behav of core_top is signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; signal byte_s_pin : std_logic; + signal nop_pin : std_logic; begin @@ -88,6 +89,7 @@ begin reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data => reg_wr_data_pin, --: in gp_register_t; reg_we => reg_we_pin, --: in std_logic; + nop => nop_pin, --Data outputs branch_prediction_res => prediction_result_pin, --: instruction_word_t; @@ -119,5 +121,6 @@ begin --end process; result <= result_pin; + nop_pin <= (alu_jump_bit_pin xor brpr_pin); end behav; diff --git a/cpu/src/decode_stage.vhd b/cpu/src/decode_stage.vhd index 103822c..e99825d 100644 --- a/cpu/src/decode_stage.vhd +++ b/cpu/src/decode_stage.vhd @@ -25,6 +25,7 @@ entity decode_stage is reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data : in gp_register_t; reg_we : in std_logic; + nop : in std_logic; --Data outputs -- reg1_rd_data : out gp_register_t; diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd index b0ae0dd..c045d6a 100644 --- a/cpu/src/decoder_b.vhd +++ b/cpu/src/decoder_b.vhd @@ -311,6 +311,9 @@ begin instr_s.op_detail(IMM_OPT) := '1'; end if; + instr_s.op_detail(NO_DST_OPT) := '1'; + instr_s.op_group := ADDSUB_OP; + instr_s.op_detail(SUB_OPT) := '1'; end if; diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd index c1c6b0c..0f19495 100644 --- a/cpu/src/pipeline_tb.vhd +++ b/cpu/src/pipeline_tb.vhd @@ -47,6 +47,7 @@ architecture behavior of pipeline_tb is signal dmem_wr_en_pin : std_logic; signal hword_pin : std_logic; signal byte_s_pin : std_logic; + signal nop_pin : std_logic; begin @@ -105,6 +106,7 @@ begin reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0); reg_wr_data => reg_wr_data_pin, --: in gp_register_t; reg_we => reg_we_pin, --: in std_logic; + nop => nop_pin, --Data outputs branch_prediction_res => prediction_result_pin, --: instruction_word_t; @@ -124,6 +126,7 @@ begin reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin); + nop_pin <= (alu_jump_bit_pin xor brpr_pin); ------------------------------------------------------------------------------- -- generate simulation clock diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd index a0b1639..9f22736 100644 --- a/cpu/src/r2_w_ram_b.vhd +++ b/cpu/src/r2_w_ram_b.vhd @@ -15,7 +15,7 @@ architecture behaviour of r2_w_ram is 1 => x"00000001", 2 => x"FFFFFFFF", 3 => x"00000003", - others=> x"00000000"); + others=> (others => '0')); begin process(clk) diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd index 3664ea1..db886c4 100644 --- a/cpu/src/r_w_ram_b.vhd +++ b/cpu/src/r_w_ram_b.vhd @@ -15,7 +15,7 @@ architecture behaviour of r_w_ram is 2 => "11100000000010000001100000000000", -- r1 = r0 + r3 (always) 3 => "11100000101000000001000000000000", 4 => "11100001000110010111011001101100", - others => x"E0000000"); + others => x"F0000000"); begin process(clk) -- 2.25.1