agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c
-agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c
agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c
agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c
agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
+agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnCpb.c
agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c
agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c
+++ /dev/null
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Comal platform solution
- *
- * This file generates the defaults tables for the "Comal" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 49803 $ @e \$Date: 2011-03-29 15:20:04 +0800 (Tue, 29 Mar 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "TrinyPI "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Comal solution is defined to be family 0x15 in the FS1 and FP2 sockets.
-#define INSTALL_FS1_SOCKET_SUPPORT TRUE
-#define INSTALL_FP2_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_15_SUPPORT TRUE
-
-#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
- #if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE
- #undef INSTALL_FS1_SOCKET_SUPPORT
- #define INSTALL_FS1_SOCKET_SUPPORT FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FP2_SOCKET_SUPPORT
- #if BLDOPT_REMOVE_FP2_SOCKET_SUPPORT == TRUE
- #undef INSTALL_FP2_SOCKET_SUPPORT
- #define INSTALL_FP2_SOCKET_SUPPORT FALSE
- #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
-#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
-#define DFLT_HPET_BASE_ADDRESS 0xFED00000
-#define DFLT_SMI_CMD_PORT 0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
-#define DFLT_GEC_BASE_ADDRESS 0xFED61000
-#define DFLT_AZALIA_SSID 0x780D1022
-#define DFLT_SMBUS_SSID 0x780B1022
-#define DFLT_IDE_SSID 0x780C1022
-#define DFLT_SATA_AHCI_SSID 0x78011022
-#define DFLT_SATA_IDE_SSID 0x78001022
-#define DFLT_SATA_RAID5_SSID 0x78031022
-#define DFLT_SATA_RAID_SSID 0x78021022
-#define DFLT_EHCI_SSID 0x78081022
-#define DFLT_OHCI_SSID 0x78071022
-#define DFLT_LPC_SSID 0x780E1022
-#define DFLT_FCH_GPP_LINK_CONFIG PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
+++ /dev/null
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Deccan platform solution
- *
- * This file generates the defaults tables for the "Deccan" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 35276 $ @e \$Date: 2010-07-19 10:47:05 -0700 (Mon, 19 Jul 2010) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "KrishaPI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'K', 'r', 'i', 's', 'h', 'a', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '3', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Deccan solution is defined to be family 0x14, models 10h-1fh in the FT2 socket.
-#define INSTALL_FT2_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
-#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
-#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
-#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
-#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
-#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
-#define DFLT_HPET_BASE_ADDRESS 0xFED00000
-#define DFLT_SMI_CMD_PORT 0xB0
-#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
-#define DFLT_GEC_BASE_ADDRESS 0xFED61000
-#define DFLT_AZALIA_SSID 0x780D1022
-#define DFLT_SMBUS_SSID 0x780B1022
-#define DFLT_IDE_SSID 0x780C1022
-#define DFLT_SATA_AHCI_SSID 0x78011022
-#define DFLT_SATA_IDE_SSID 0x78001022
-#define DFLT_SATA_RAID5_SSID 0x78031022
-#define DFLT_SATA_RAID_SSID 0x78021022
-#define DFLT_EHCI_SSID 0x78081022
-#define DFLT_OHCI_SSID 0x78071022
-#define DFLT_LPC_SSID 0x780E1022
-#define DFLT_FCH_GPP_LINK_CONFIG PortA4
-#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
-#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
-#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
-#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
-#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
// Family 12h equates
#define AMD_FAMILY_12_LN 0x0000000000000020ull
-#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
-#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
+#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
+#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
// Family 14h equates
#define AMD_FAMILY_14_ON 0x0000000000000040ull
-#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
-#define AMD_FAMILY_14_KR 0x0000000000000080ull
-#define AMD_FAMILY_KR (AMD_FAMILY_14_KR)
-#define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR)
+#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
+#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
// Family 15h equates
#define AMD_FAMILY_15_OR 0x0000000000000100ull
#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
-#define AMD_FAMILY_15_TN 0x0000000000000200ull
-#define AMD_FAMILY_TN (AMD_FAMILY_15_TN)
-#define AMD_FAMILY_15_KM 0x0000000000000400ull
-#define AMD_FAMILY_KM (AMD_FAMILY_15_KM)
-#define AMD_FAMILY_15 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | AMD_FAMILY_15_KM)
+#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
// Family 16h equates
#define AMD_FAMILY_16 0x0000000000000800ull
#define AMD_F14_ON_Cx (AMD_F14_ON_C0)
#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
-#define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1)
-#define AMD_F14_KR_Bx AMD_F14_KR_B0
-#define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx)
-
-#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL | AMD_F14_UNKNOWN)
+#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
-#define AMD_F15_TN_Ax (AMD_F15_TN_A0)
-#define AMD_F15_TN_ALL (AMD_F15_TN_Ax)
-
-#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_TN_ALL | AMD_F15_UNKNOWN)
+#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
// Family 16h CPU_LOGICAL_ID.Revision equates
// TBD
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
// AmlObjName = '10DA';
- AmlObjName = 0x31304441;
+ AmlObjName = Int32FromChar ('1', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// AmlObjName = '30DA';
- AmlObjName = 0x33304441;
+ AmlObjName = Int32FromChar ('3', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader);
BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader);
// AmlObjName = '40DA';
- AmlObjName = 0x34304441;
+ AmlObjName = Int32FromChar ('4', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '50DA';
- AmlObjName = 0x35304441;
+ AmlObjName = Int32FromChar ('5', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '01DA';
- AmlObjName = 0x30314441;
+ AmlObjName = Int32FromChar ('0', '1', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
// AmlObjName = '20DA';
- AmlObjName = 0x32304441;
+ AmlObjName = Int32FromChar ('2', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '60DA';
- AmlObjName = 0x36304441;
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '60DA';
- AmlObjName = 0x36304441;
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '70DA';
- AmlObjName = 0x37304441;
+ AmlObjName = Int32FromChar ('7', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
AgesaStatus = AGESA_SUCCESS;
AltVddNbSupport = TRUE;
// AmlObjName = 'A0DA';
- AmlObjName = 0x41304441;
+ AmlObjName = Int32FromChar ('A', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
- * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
+ * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
*/
/*
*****************************************************************************
* GNB configuration info
*----------------------------------------------------------------------------
*/
+
+/// LVDS Misc Control Field
+typedef struct {
+ IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode
+ ///< @li FALSE = LVDS 888 panel in LDI mode
+ ///< @li TRUE = LVDS 888 panel in FPDI mode
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+ IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping
+ ///< @li FALSE = Lower link and upper link not swap
+ ///< @li TRUE = Lower link and upper link are swapped
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+ IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream
+ ///< @li FALSE = Active high Frame Pulse/Vsync
+ ///< @li TRUE = Active low Frame Pulse/Vsync
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
+ IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data
+ ///< @li FALSE = Active high Line Pulse
+ ///< @li TRUE = Active low Line Pulse / Hsync
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
+ IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin
+ ///< @li FALSE = Not inverted(active high)
+ ///< @li TRUE = Inverted (active low)
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+ IN UINT8 Reserved:3; ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+ IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
/// Configuration settings for GNB.
typedef struct {
IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+ IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
} GNB_ENV_CONFIGURATION;
/// GNB configuration info
///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< The LVDS Misc control
+ IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
IN BOOLEAN Reserved; ///< reserved...
} BUILD_OPT_CFG;
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
- IN UINT64 HeapBasePtr; ///< Location of the heap
+ IN VOID *HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
-/*
- *****************************************************************************
+/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
* ***************************************************************************
*
*/
memDefFalse (
VOID
);
+
+VOID
+MemRecDefRet (VOID);
+
+BOOLEAN
+MemRecDefTrue (VOID);
+
#endif // _ADVANCED_API_H_
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
- * @e \$Revision: 40817 $ @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
+ * @e \$Revision: 53801 $ @e \$Date: 2011-05-25 12:03:55 -0600 (Wed, 25 May 2011) $
*/
-/*
- *****************************************************************************
+/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * ***************************************************************************
+ ****************************************************************************
*
*/
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The Brazos solution is defined to be family 0x14 in the FT1 socket.
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
- * @e \$Revision: 40742 $ @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
+ * @e \$Revision: 46485 $ @e \$Date: 2011-02-03 09:03:14 -0700 (Thu, 03 Feb 2011) $
*/
/*
*****************************************************************************
#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D)
#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E)
#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F)
+#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA10)
+#define PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE (0xCA11)
#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21)
#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23)
#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24)
-#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA25)
#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE (0xCA2C)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE (0xCA2D)
// Family 15h
#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
+ *
+ ****************************************************************************
*
*/
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of Advanced Micro Devices, Inc. nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
+ *
* ***************************************************************************
*
*/
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#else
- #pragma warning(disable: 4127)
- #ifdef __GNUC__
+ #ifndef __GNUC__
+ #pragma warning(disable: 4127)
#define IDS_HDT_CONSOLE(f, s, ...)
- #else
- #define IDS_HDT_CONSOLE(f, s, ...)
- #endif
+ #else
+ #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__);
+ #endif
#endif
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#endif
///For IDS feat use
-#define IDS_FAMILY_ALL 0x0ull
+#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
#define IDS_BSP_ONLY TRUE
#define IDS_ALL_CORES FALSE
#define OPTION_CPB_FEAT
#define F10_CPB_SUPPORT
#define F12_CPB_SUPPORT
+#define F14_ON_CPB_SUPPORT
#define F15_CPB_SUPPORT
#if OPTION_CPB == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+ #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 10h
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#endif
#endif
+ // Family 14h
+ #ifdef OPTION_FAMILY14H
+ #if OPTION_FAMILY14H == TRUE
+ #if OPTION_FAMILY14H_ON == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+ #undef OPTION_CPB_FEAT
+ #define OPTION_CPB_FEAT &CpuFeatureCpb,
+ extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
+ #undef F14_ON_CPB_SUPPORT
+ #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
+ #endif
+ #endif
+ #endif
+
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
{
F10_CPB_SUPPORT
F12_CPB_SUPPORT
+ F14_ON_CPB_SUPPORT
F15_CPB_SUPPORT
{0, NULL}
};
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
#if OPTION_FAMILY14H_ON == TRUE
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
+ extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
&F14EarlySampleMsrRegisterTable,
#endif
#endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F14OnPciRegisterTable,
+ #endif
// the end.
NULL
};
#if GET_PATCHES == TRUE
#define F14_ON_UCODE_0B
#define F14_ON_UCODE_1A
- #define F14_ON_UCODE_25
+ #define F14_ON_UCODE_28
+ #define F14_ON_UCODE_101
// If a patch is required for recovery mode to function properly, add a
// conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
#undef F14_ON_UCODE_1A
#define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
#endif
- extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
- #undef F14_ON_UCODE_25
- #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028;
+ #undef F14_ON_UCODE_28
+ #define F14_ON_UCODE_28 &CpuF14MicrocodePatch05000028,
+
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101;
+ #undef F14_ON_UCODE_101
+ #define F14_ON_UCODE_101 &CpuF14MicrocodePatch05000101,
#endif
CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
{
+ F14_ON_UCODE_101
+ F14_ON_UCODE_28
F14_ON_UCODE_0B
F14_ON_UCODE_1A
- F14_ON_UCODE_25
NULL
};
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
BOOLEAN SmuSclkClockGatingEnable;///< Control SMU SCLK gating
- BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
+ BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
+ UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+ UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
+ UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
+ UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
+ UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
#define GNB_TYPE_KR FALSE
#define GNB_TYPE_TN FALSE
+#include "Gnb.h"
+#include "GnbPcie.h"
+
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
+#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
+ #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
+#endif
+
+#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
+ #define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
+#endif
+
+#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
+ #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
+#endif
+
+#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
+ #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
+#endif
+
+#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
+ #define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
+#else
+ #define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
+#endif
+
GNB_BUILD_OPTIONS GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATE_STUTTER_ONLY,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
- CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+ CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
+ CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
+ CFG_GNB_PCIE_LINK_L0_POOLING,
+ CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
+ CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
+ CFG_GNB_PCIE_TRAINING_ALGORITHM
};
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIE_POST_EALRY_INIT
+ #define OPTION_PCIE_POST_EALRY_INIT TRUE
+ #endif
+ #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+ OPTION_GNB_FEATURE PcieInitAtPostEarly;
+ #define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
+ #else
+ #define OPTION_PCIEINITATPOSTEARLY_ENTRY
+ #endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
+ OPTION_PCIEINITATPOSTEARLY_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXINITATPOST_ENTRY
{0, NULL}
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
+
+BOOLEAN MemMDefRetFalse (
+ IN MEM_MAIN_DATA_BLOCK *MMPtr
+ );
+
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
+
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT MEM_DATA_STRUCT *MemPtr,
+ IN UINT8 NodeID
+ );
+
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
* based upon the number of processor families that the BIOS will support.
*/
+ extern MEM_FLOW_CFG MemMFlowDef;
#if (OPTION_MEMCTLR_DR == TRUE)
extern MEM_FLOW_CFG MemMFlowDr;
#define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_DA == TRUE)
extern MEM_FLOW_CFG MemMFlowDA;
#define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_HY == TRUE)
extern MEM_FLOW_CFG MemMFlowHy;
#define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_OR == TRUE)
extern MEM_FLOW_CFG MemMFlowOr;
#define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_LN == TRUE)
extern MEM_FLOW_CFG MemMFlowLN;
#define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_C32 == TRUE)
extern MEM_FLOW_CFG MemMFlowC32;
#define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_ON == TRUE)
extern MEM_FLOW_CFG MemMFlowON;
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_Ni == TRUE)
extern MEM_FLOW_CFG MemMFlowDA;
#define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_RB == TRUE)
extern MEM_FLOW_CFG MemMFlowRb;
#define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
#endif
#if (OPTION_MEMCTLR_PH == TRUE)
extern MEM_FLOW_CFG MemMFlowPh;
#define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
#else
- extern MEM_FLOW_CFG MemMFlowDef;
#define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
#endif
#define MEM_FEATURE_ECCX8 MemMDefRet
#endif
- #if (OPTION_EMP == TRUE)
- extern OPTION_MEM_FEATURE_NB MemFInitEMP;
- #define MEM_FEATURE_EMP MemFInitEMP
- #else
- #define MEM_FEATURE_EMP MemFDefRet
- #endif
-
extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
#define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr
extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
#define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc
+ extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#if (OPTION_PARALLEL_TRAINING == TRUE)
extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining
#else
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
#endif
#define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
#endif
#if (OPTION_SW_DRAM_INIT == TRUE)
- extern MEM_TECH_FEAT MemTDramInitSw3;
+// extern MEM_TECH_FEAT MemTDramInitSw3;
#define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3
#else
#define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
#undef MEM_MAIN_FEATURE_TRAINING
#undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
#define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
#define MEM_FEATURE_TRAINING MemFStandardTraining
TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
TECH_TRAIN_MAX_RD_LAT_DDR3
};
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+// extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
#define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
+// extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
#else
#undef TECH_TRAIN_ENTER_HW_TRN_DDR3
NULL
};
CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
- #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
- #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
- #endif
+// #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
+// #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
+// #endif
/*---------------------------------------------------------------------------------------------------
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
*
*---------------------------------------------------------------------------------------------------
*/
- MEM_NB_SUPPORT MemRecNBInstalled[] = {
+ MEM_NB_SUPPORT* MemRecNBInstalled[] = {
NULL
};
/*----------------------------------------------------------------------
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
- OPTION_SSDT_FEATURE GenerateSsdt;
+// OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
- * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
+ * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
*/
/*
*****************************************************************************
VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
//ModuleHeaderSignature
// Remove 'DOM$' as temp solution before update BinUtil.exe ,
- '0000',
+ Int32FromChar ('0', '0', '0', '0'),
//ModuleIdentifier[8]
AGESA_ID,
//ModuleVersion[12]
#define OPTION_GFX_RECOVERY TRUE
#undef OPTION_C6_STATE
#define OPTION_C6_STATE TRUE
+ #undef OPTION_CPB
+ #define OPTION_CPB TRUE
#undef OPTION_IO_CSTATE
#define OPTION_IO_CSTATE TRUE
#undef OPTION_S3SCRIPT
#define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
#endif
+#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+ #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+#else
+ #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
+#endif
+
#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
#define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
#else
#endif
#endif
+#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
+ #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
+#else
+ #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
+ #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
+#else
+ #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+ #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+#else
+ #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+ #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+#else
+ #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+ #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+#else
+ #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
+#endif
/*---------------------------------------------------------------------------
* Processing the options: Third, perform the option cross checks
*--------------------------------------------------------------------------*/
CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
+ {{
+ CFG_LVDS_MISC_888_FPDI_MODE, // CfgLvdsMiscControl
+ CFG_LVDS_MISC_DL_CH_SWAP, // CfgLvdsMiscControl
+ CFG_LVDS_MISC_VSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
+ CFG_LVDS_MISC_HSYNC_ACTIVE_LOW, // CfgLvdsMiscControl
+ CFG_LVDS_MISC_BLON_ACTIVE_LOW, // CfgLvdsMiscControl
+ }},
+ CFG_PCIE_REFCLK_SPREAD_SPECTRUM, // CfgPcieRefClkSpreadSpectrum
0, //reserved...
};
AMD_LATE_RUN_AP_TASK_HANDLE
},
#endif
- { 0, NULL }
+ { 0, 0, NULL }
};
CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
+ MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode , CFG_LVDS_MISC_888_FPDI_MODE),
+ MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap , CFG_LVDS_MISC_DL_CH_SWAP),
+ MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
+ MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
+ MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
+ MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
#endif
NULL
};
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
- ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
+ ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
ImageEnd = ImageStart + 4;
// Locate/test image base that matches this component
- AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, AGESA_ID);
+ AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *)AGESA_ID);
if (AltImagePtr != NULL) {
//Invoke alternative Image
- ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
+ ImageEntry = (IMAGE_ENTRY) (AltImagePtr + AltImagePtr->EntryPointAddress);
Status = (*ImageEntry) (ConfigPtr);
}
}
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+AgesaGetIdsData (
+ IN UINTN Data,
+ IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
-#include "cpuLateInit.h"
+//#include "cpuLateInit.h"
+#include "cpuEnvInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
// Region above 1MB
// Variable MTTR region
// Get family specific cache Info
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
- BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
+ BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress);
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if (StdHeader->HeapBasePtr >= 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
- if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
- (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
+ if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) &&
+ (VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
break;
}
}
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
-; * @e \$Revision: 41505 $ @e \$Date: 2010-11-05 22:06:20 +0800 (Fri, 05 Nov 2010) $
+; * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
;
;*****************************************************************************
;
;----------------------------------------------------------------------------
;
+; LVDS Misc Control Field
+LVDS_MISC_CONTROL_FIELD STRUCT
+ FpdiMode UINT8 ?
+ ;IN UINT8 FpdiMode:1;
+ ;IN UINT8 DlChSwap:1;
+ ;IN UINT8 VsyncActiveLow:1;
+ ;IN UINT8 HsyncActiveLow:1;
+ ;IN UINT8 BLONActiveLow:1;
+ ;IN UINT8 Reserved:3;
+LVDS_MISC_CONTROL_FIELD ENDS
+
+; LVDS Misc Control
+LVDS_MISC_CONTROL UNION
+ Field LVDS_MISC_CONTROL_FIELD {}
+ Value UINT8 ?
+LVDS_MISC_CONTROL ENDS
+
; Configuration settings for GNB.
GNB_ENV_CONFIGURATION STRUCT
Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
; @li 6 = Use processor pin HPD6
LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+ LvdsMiscControl LVDS_MISC_CONTROL {} ; This item configures LVDS swap/Hsync/Vsync/BLON
+ PcieRefClkSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
GNB_ENV_CONFIGURATION ENDS
; GNB configuration info
CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
+ CfgLvdsMiscControl LVDS_MISC_CONTROL {}; THe LVDS Misc control
+ CfgPcieRefClkSpreadSpectrum UINT16 ? ; PCIe Reference Clock Spread Spectrum
Reserved BOOLEAN ? ; < reserved...
BUILD_OPT_CFG ENDS
PartNumber CHAR8 (19) DUP (?) ; < Part Number.
Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
ExtSize UINT32 ? ; < Extended Size.
+ ConfigSpeed UINT16 ? ; < Configured memory clock speed
TYPE17_DMI_INFO ENDS
; Memory DMI Type 17 and 20 - for memory use
EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with
; ///< the Memory Device structure to which this address
; ///< range is mapped.
+ ConfigSpeed UINT16 ? ; ///< Configured memory clock speed
MEM_DMI_INFO ENDS
; DMI Type 19 - Memory Array Mapped Address
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Lib
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
#
# Copyright (c) 2011, Advanced Micro Devices, Inc.
# All rights reserved.
-#
+#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
-#
+#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
#*****************************************************************************
# AGESA V5 Files
AGESA_INC += -I$(AGESA_ROOT)/Lib
AGESA_INC += -I$(AGESA_ROOT)/Legacy
AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
-AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
-AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14/ON
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON
-AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
-AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
-AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x14
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common
+AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
+AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
#define VOLATILE volatile
#define TRUE 1
#define FALSE 0
+// #undef CONST
#define CONST const
#define ROMDATA
#define CALLCONV
#ifndef NULL
#define NULL (void *)0
#endif
-#ifdef ROMDATA
-//#undef ROMDATA
-#endif
-//#define ROMDATA __attribute__ ((section("rom.data"))
#else
// -----------------------------------------------------------------------
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AP_TASK TaskPtr;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
- MsrRegister = 0;
+ MsrReg = 0;
- ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+ ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+ TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
CPUID_DATA CpuId;
CPU_LOGICAL_ID LogicalId;
if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
- LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrRegister, StdHeader);
- if ((MsrRegister & 0xffffffff) >= 0x010000BF) {
+ LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrReg, StdHeader);
+ if ((MsrReg & 0xffffffff) >= 0x010000BF) {
return TRUE;
}
}
)
{
UINT32 MsrAddress;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
- LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
- LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
- ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
- LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrReg)->StartupPstate) + PS_REG_BASE);
+ LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
+ LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrReg, StdHeader);
+ ((PSTATE_MSR *) &MsrReg)->NbVid = *(UINT8 *) NewNbVid;
+ LibAmdMsrWrite (PS_REG_BASE, &MsrReg, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
}
)
{
UINT32 MsrAddress;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
- LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->IddValue != 0) {
- if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
- ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
- LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->IddValue != 0) {
+ if ((((PSTATE_MSR *) &MsrReg)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
+ ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
+ LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader);
}
}
}
)
{
UINT32 MsrAddress;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
- LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- ((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
- ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
- LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MsrAddress, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
+ ((PSTATE_MSR *) &MsrReg)->NbDid = 1;
+ ((PSTATE_MSR *) &MsrReg)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
+ LibAmdMsrWrite (MsrAddress, &MsrReg, StdHeader);
}
}
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AP_TASK TaskPtr;
- MsrRegister = 0;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
- ((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
- ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
- ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
+ MsrReg = 0;
+ ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData;
+ ((INTPEND_MSR *) &MsrReg)->IoRd = 1;
+ ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 1;
+ ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+ TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
// Enable C1e
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
// Set OS Visible Workaround Status BIT1 to indicate that C1e
// is enabled.
- LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
- MsrRegister |= BIT1;
- LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader);
+ MsrReg |= BIT1;
+ LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AP_TASK TaskPtr;
- MsrRegister = 0;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
- ((INTPEND_MSR *) &MsrRegister)->IoRd = 0;
- ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
- ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1;
+ MsrReg = 0;
+ ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
+ ((INTPEND_MSR *) &MsrReg)->IoMsgData = PlatformConfig->C1ePlatformData2;
+ ((INTPEND_MSR *) &MsrReg)->IoRd = 0;
+ ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0;
+ ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 1;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+ TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
// Enable C1e
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
// Set OS Visible Workaround Status BIT1 to indicate that C1e
// is enabled.
- LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
- MsrRegister |= BIT1;
- LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_OSVW_Status, &MsrReg, StdHeader);
+ MsrReg |= BIT1;
+ LibAmdMsrWrite (MSR_OSVW_Status, &MsrReg, StdHeader);
}
UINT32 NbVid;
UINT32 PciRegister;
UINT32 ProductInfoRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
BOOLEAN PstateIsValid;
PstateIsValid = TRUE;
PciAddress->Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid;
} else {
NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
- LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader);
- MsrRegister |= BIT42;
- LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_BU_CFG2, &MsrReg, StdHeader);
+ MsrReg |= BIT42;
+ LibAmdMsrWrite (MSR_BU_CFG2, &MsrReg, StdHeader);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
// Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
- LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader);
- ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
- ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
- ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1;
- ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0;
- ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
- LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_INTPEND, &MsrReg, StdHeader);
+ ((INTPEND_MSR *) &MsrReg)->SmiOnCmpHalt = 0;
+ ((INTPEND_MSR *) &MsrReg)->C1eOnCmpHalt = 0;
+ ((INTPEND_MSR *) &MsrReg)->BmStsClrOnHltEn = 1;
+ ((INTPEND_MSR *) &MsrReg)->IntrPndMsgDis = 0;
+ ((INTPEND_MSR *) &MsrReg)->IntrPndMsg = 0;
+ ((INTPEND_MSR *) &MsrReg)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
+ LibAmdMsrWrite (MSR_INTPEND, &MsrReg, StdHeader);
// Set MSRC001_0015[HltXSpCycEn] = 1
- LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader);
- MsrRegister |= BIT12;
- LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_HWCR, &MsrReg, StdHeader);
+ MsrReg |= BIT12;
+ LibAmdMsrWrite (MSR_HWCR, &MsrReg, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
)
{
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
*FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
*FreqDivisor = 1;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid)));
PstateIsValid = TRUE;
}
return PstateIsValid;
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_LS_CFG, // MSR Address
0x0000000000000000, // OR Mask
(1 << 1) // NAND Mask
- }
+ }}
},
// MSR_BU_CFG (0xC0011023)
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_BU_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
- }
+ }}
},
// MSR_BU_CFG2 (0xC001102A)
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_C0 // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_BU_CFG2, // MSR Address
0x0004000000000000, // OR Mask
0x0004000000000000, // NAND Mask
- }
+ }}
}
};
)
{
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
*FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
*FreqDivisor = 1;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrReg)->CurNbVid)));
PstateIsValid = TRUE;
}
return PstateIsValid;
CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
CpuInfoPtr->TotalCoreNumber--;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
NumBoostStates = 0;
LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
UINT32 Core;
UINT32 AndMask;
UINT32 OrMask;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PCI_ADDR PciAddress;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
// Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
// P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
UINT32 Ignored;
UINT32 PsMaxVal;
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
UINT64 SavedMsr;
UINT64 CurrentLimitMsr;
PCI_ADDR PciAddress;
// Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&LogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
+ LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+ MsrReg |= BIT62;
+ LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
}
}
PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
// Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate !=
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ if (((COFVID_STS_MSR *) &MsrReg)->CurPstate !=
((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
GoToStep = STEP20;
} else {
// Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
// register pointed to by F3xDC[PstateMaxVal]+1
- LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader);
- LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+ LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrReg, StdHeader);
+ LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrReg, StdHeader);
// Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
// Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) {
+ LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+ MsrReg |= BIT62;
+ LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
}
}
// Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
+ LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+ MsrReg |= BIT62;
+ LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
}
}
// Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
// the sequence
if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 1) {
+ LibAmdMsrRead (NB_CFG, &MsrReg, StdHeader);
+ MsrReg |= BIT62;
+ LibAmdMsrWrite (NB_CFG, &MsrReg, StdHeader);
break;
}
}
UINT32 OrMask;
UINT32 PstateLimit;
PCI_ADDR PciAddress;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AP_TASK TaskPtr;
CPUID_DATA CpuidData;
AGESA_STATUS IgnoredSts;
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
- LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
UINT8 DisPsNum;
UINT8 CurrentPs;
UINT8 EnBsNum;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates;
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
+ LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
+ CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrReg)->CurPstate);
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
- LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
- LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
+ LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrReg, StdHeader);
+ LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrReg, StdHeader);
}
UINT32 AndMask;
UINT32 OrMask;
UINT32 ProcessorPackageType;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PLATFORM_FEATS Features;
OrMask = 0x00000000;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
- LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
+ LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrReg, StdHeader);
+ ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid;
+ ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuFid;
+ ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuDid;
PciAddress.Address.Register = POPUP_PSTATE_REG;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
+ ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrReg)->CpuVid;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// Set up Altvid slam time
UINT32 MsrAddr;
UINT32 NbVid;
UINT32 CpuVid;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
- NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
- CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+ LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == (UINT64) 1) {
+ NbVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->NbVid);
+ CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
if (NbVid != CpuVid) {
if (NbVid > CpuVid) {
NbVid = CpuVid;
}
- ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
- ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
- LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
+ ((PSTATE_MSR *) &MsrReg)->NbVid = NbVid;
+ ((PSTATE_MSR *) &MsrReg)->CpuVid = NbVid;
+ LibAmdMsrWrite (MsrAddr, &MsrReg, StdHeader);
}
}
}
UINT8 PminVidCode;
UINT32 MsrAddr;
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PCI_ADDR LocalPciAddress;
// Calculate Slam Time
// decimals.
// Get Pmin's index
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
- MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+ LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader);
+ MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE);
// Get Pmin's VID
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+ LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+ PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
// If SVI, we only care about CPU VID.
// If PVI, determine the higher voltage b/t NB and CPU
if (PviModeFlag) {
- NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+ NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
if (PminVidCode > NbVid) {
PminVidCode = NbVid;
}
UINT8 TempValue;
UINT32 CpuDid;
UINT32 CpuFid;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid);
- CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+ CpuDid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDid);
+ CpuFid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuFid);
switch (CpuDid) {
case 0:
PCI_ADDR PciAddress;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
Ignored = 0;
UINT32 Power;
PCI_ADDR PciAddress;
UINT32 TempVar_a;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AGESA_STATUS IgnoredSts;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
- IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
- IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+ CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
+ IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
+ IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
UINT32 PciRegister;
PCI_ADDR PciAddress;
CPUID_DATA CpuidData;
*SwPstateNumber = PState;
// Read PSTATE MSRs
- LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrReg, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
// Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
}
// Bits 39:32 (high 32 bits [7:0])
- *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
+ *IddVal = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
- *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
+ *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrReg)->IddDiv;
return (AGESA_SUCCESS);
}
UINT32 Socket;
UINT32 Module;
UINT32 Ignored;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
PciAddress.Address.Register = PW_CTL_MISC_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) {
- LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
- ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode;
- LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader);
+ ((COFVID_CTRL_MSR *) &MsrReg)->CpuVid = VidCode;
+ LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader);
F10WaitOutVoltageTransition (TRUE, StdHeader);
} else
return;
)
{
UINT32 VidCode;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) {
VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode;
} else {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid);
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrReg)->CurNbVid);
if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
--VidCode;
} else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
++VidCode;
}
}
- LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
- ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode;
- LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+ LibAmdMsrRead (MSR_COFVID_CTL, &MsrReg, StdHeader);
+ ((COFVID_CTRL_MSR *) &MsrReg)->NbVid = VidCode;
+ LibAmdMsrWrite (MSR_COFVID_CTL, &MsrReg, StdHeader);
if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
return 0;
UINT32 MsrAddr;
UINT32 OrMask;
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
BOOLEAN IsPviMode;
PCI_ADDR LocalPciAddress;
}
// Get P0's voltage
- LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader);
- P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+ LibAmdMsrRead (PS_REG_BASE, &MsrReg, StdHeader);
+ P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
// If SVI, we only care about CPU VID.
// If PVI, determine the higher voltage between NB and CPU
if (IsPviMode) {
- NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+ NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
if (P0VidCode > NbVid) {
P0VidCode = NbVid;
}
}
// Get Pmin's index
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
- MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+ LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrReg, StdHeader);
+ MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrReg)->PstateMaxVal) + PS_REG_BASE);
// Get Pmin's VID
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+ LibAmdMsrRead (MsrAddr, &MsrReg, StdHeader);
+ PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrReg)->CpuVid);
// If SVI, we only care about CPU VID.
// If PVI, determine the higher voltage b/t NB and CPU
if (IsPviMode) {
- NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+ NbVid = (UINT8) (((PSTATE_MSR *) &MsrReg)->NbVid);
if (PminVidCode > NbVid) {
PminVidCode = NbVid;
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
- LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
+ LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
return (AGESA_SUCCESS);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
- ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
- LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+ LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
+ ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
+ LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
if (WaitForTransition) {
do {
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
+ LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
+ } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
}
return (AGESA_SUCCESS);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
- LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
- if ((MsrRegister & 0x01000000) != 0) {
+ LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
+ if ((MsrReg & 0x01000000) != 0) {
return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
} else {
return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
UINT32 Core;
UINT32 NbFid;
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PCI_ADDR PciAddress;
AGESA_STATUS ReturnCode;
PciAddress.Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
+ LibAmdMsrRead (MSR_COFVID_STS, &MsrReg, StdHeader);
+ if (((COFVID_STS_MSR *) &MsrReg)->CurNbDid == 0) {
*FrequencyInMHz = ((NbFid + 4) * 200);
} else {
*FrequencyInMHz = (((NbFid + 4) * 200) / 2);
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PCI_ADDR PciAddress;
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
- LibAmdMsrRead (i, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ LibAmdMsrRead (i, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
UINT32 i;
UINT32 MaxEnabledPstate;
UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
- LibAmdMsrRead (i, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ LibAmdMsrRead (i, &MsrReg, StdHeader);
+ if (((PSTATE_MSR *) &MsrReg)->PsEnable == 1) {
break;
}
}
MaxEnabledPstate = i - MSR_PSTATE_0;
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
- MsrRegister = 0;
- ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
- ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
- (((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
+ MsrReg = 0;
+ ((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+ ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr != 0) &&
+ (((CSTATE_ADDRESS_MSR *) &MsrReg)->CstateAddr <= 0xFFF8));
TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+ TaskPtr.DataTransfer.DataPtr = &MsrReg;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
// Patch code 0500000B for 5000 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
-{
+{{
0x10,
0x20,
0x01,
0xe9,
0xb2,
0x6d
-};
+}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
// Patch code 0500001A for 5001 and equivalent
CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
-{
+{{
0x10,
0x20,
0x08,
0x73,
0x52,
0x3b
-};
+}};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
--- /dev/null
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Microcode patch.
+ *
+ * Fam14 Microcode Patch rev 05000028 for 5010 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU/FAMILY/0x14
+ * @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 05000028 for 5010 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028 =
+{{
+0x10,
+0x20,
+0x24,
+0x11,
+0x28,
+0x00,
+0x00,
+0x05,
+0x01,
+0x80,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x10,
+0x50,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x89,
+0x66,
+0x9f,
+0x9a,
+0x14,
+0x8a,
+0xcd,
+0xbb,
+0x71,
+0x6b,
+0x59,
+0xe0,
+0xf1,
+0xec,
+0x1d,
+0xe2,
+0xa1,
+0xcb,
+0xdd,
+0x85,
+0xd4,
+0x54,
+0x18,
+0x05,
+0x1f,
+0x71,
+0x70,
+0x1f,
+0xb5,
+0x6b,
+0x86,
+0xa2,
+0x37,
+0x5e,
+0x14,
+0x1b,
+0xdd,
+0xf4,
+0x40,
+0x31,
+0x90,
+0x8a,
+0xa3,
+0xc1,
+0x4a,
+0x5c,
+0xb8,
+0x36,
+0xf1,
+0xe8,
+0x7e,
+0x4c,
+0x2d,
+0xc0,
+0x51,
+0x92,
+0xd8,
+0xb4,
+0x9d,
+0x6c,
+0xa6,
+0xd1,
+0x3b,
+0x6c,
+0xed,
+0x8e,
+0x4a,
+0x2e,
+0xf4,
+0x33,
+0xbe,
+0xcf,
+0x57,
+0xf9,
+0xa2,
+0x24,
+0x28,
+0x81,
+0x63,
+0x04,
+0xeb,
+0x75,
+0x70,
+0x25,
+0x7d,
+0xa7,
+0xf2,
+0xdb,
+0x5e,
+0xa0,
+0x79,
+0x5d,
+0x3a,
+0xd5,
+0x60,
+0xbb,
+0x39,
+0x3c,
+0xe9,
+0x28,
+0x37,
+0xe7,
+0xd1,
+0xf0,
+0x74,
+0x1b,
+0x05,
+0xe7,
+0x7b,
+0x38,
+0xbe,
+0x30,
+0x15,
+0xe8,
+0x37,
+0x7a,
+0xc9,
+0xd1,
+0xc9,
+0x71,
+0xe3,
+0x56,
+0x0f,
+0xae,
+0x45,
+0xd9,
+0x26,
+0x43,
+0xcf,
+0x87,
+0x35,
+0x32,
+0xf9,
+0xb2,
+0x8c,
+0xed,
+0x80,
+0xbe,
+0xb7,
+0xa3,
+0x0e,
+0x43,
+0x6c,
+0xc1,
+0x9b,
+0x06,
+0x55,
+0x93,
+0xfe,
+0xdd,
+0x12,
+0x2b,
+0xcf,
+0x03,
+0xdd,
+0xa6,
+0x56,
+0xf2,
+0x7a,
+0x82,
+0xeb,
+0x81,
+0xf4,
+0x8a,
+0x43,
+0x5a,
+0xfe,
+0xd2,
+0x9d,
+0xb6,
+0x8e,
+0x62,
+0x6c,
+0x01,
+0x68,
+0x0a,
+0x65,
+0x9c,
+0xb5,
+0x50,
+0xdb,
+0xa8,
+0x6f,
+0xea,
+0x5d,
+0x79,
+0xce,
+0xee,
+0x66,
+0x7f,
+0xea,
+0x10,
+0x65,
+0x79,
+0x85,
+0xed,
+0x99,
+0x01,
+0xff,
+0xb0,
+0xa4,
+0xd1,
+0xc0,
+0xe5,
+0x6c,
+0x67,
+0x53,
+0x25,
+0x0f,
+0xbb,
+0xc6,
+0x27,
+0x93,
+0xfd,
+0x88,
+0x92,
+0xe6,
+0xed,
+0x4f,
+0xf4,
+0xfe,
+0xda,
+0xbf,
+0x3f,
+0x35,
+0x2e,
+0xad,
+0x6e,
+0xdc,
+0x0e,
+0xc5,
+0x60,
+0xc5,
+0x06,
+0xbf,
+0x9e,
+0x49,
+0x5f,
+0x4e,
+0xf6,
+0x19,
+0x0a,
+0x9a,
+0xa1,
+0x8b,
+0xe2,
+0xad,
+0x41,
+0x3d,
+0x6f,
+0x55,
+0x3d,
+0x68,
+0x71,
+0x66,
+0xbe,
+0x73,
+0xed,
+0x48,
+0xb1,
+0xfc,
+0xe8,
+0x7d,
+0x5a,
+0x6e,
+0x74,
+0x1e,
+0xa4,
+0x57,
+0xe6,
+0xee,
+0x90,
+0x44,
+0xfb,
+0x2d,
+0x68,
+0x96,
+0x39,
+0x4b,
+0x74,
+0x89,
+0x4c,
+0x84,
+0x48,
+0x42,
+0x55,
+0x05,
+0xf1,
+0x0a,
+0x53,
+0x2e,
+0x0b,
+0xe1,
+0x4a,
+0xf3,
+0x5c,
+0x9e,
+0x01,
+0xc5,
+0x8c,
+0x48,
+0x28,
+0xf3,
+0x73,
+0x59,
+0xf8,
+0x82,
+0x6d,
+0x4f,
+0xb4,
+0x65,
+0x85,
+0x19,
+0xee,
+0xad,
+0x0b,
+0x91,
+0x89,
+0xb6,
+0x26,
+0x89,
+0x05,
+0x95,
+0xf9,
+0xf2,
+0xf3,
+0x6a,
+0x89,
+0x0a,
+0x73,
+0x19,
+0x87,
+0x80,
+0x1e,
+0x26,
+0xea,
+0x87,
+0xd9,
+0xaa,
+0x07,
+0xae,
+0xb5,
+0x05,
+0xc6,
+0x2c,
+0x7a,
+0xc0,
+0xad,
+0x60,
+0x67,
+0x47,
+0xf4,
+0xd5,
+0xa9,
+0x21,
+0x73,
+0x5b,
+0xa1,
+0x7f,
+0x4f,
+0x93,
+0x76,
+0x41,
+0xac,
+0x7c,
+0x68,
+0x7c,
+0x30,
+0x6d,
+0x13,
+0xca,
+0xcd,
+0xee,
+0x32,
+0xcb,
+0x61,
+0x7f,
+0xe0,
+0xe6,
+0x69,
+0x07,
+0xa7,
+0x54,
+0xe7,
+0x20,
+0xd9,
+0x00,
+0x23,
+0x4d,
+0xcd,
+0xc7,
+0x7b,
+0x9f,
+0x33,
+0xb1,
+0x84,
+0x08,
+0x38,
+0x98,
+0x56,
+0x88,
+0x4e,
+0x06,
+0x53,
+0x57,
+0x52,
+0x9c,
+0xb2,
+0xe7,
+0x45,
+0x8a,
+0x0b,
+0x5f,
+0x30,
+0xde,
+0x1f,
+0x72,
+0xfa,
+0x5e,
+0xd2,
+0xca,
+0xdc,
+0xe8,
+0xab,
+0xd5,
+0xe9,
+0x34,
+0xd9,
+0x95,
+0xf4,
+0xa1,
+0x21,
+0xff,
+0xd1,
+0xda,
+0xfd,
+0xc4,
+0x82,
+0x72,
+0x04,
+0xb2,
+0x88,
+0x64,
+0x19,
+0x3a,
+0xf9,
+0x16,
+0x61,
+0x37,
+0xda,
+0xdf,
+0xb5,
+0xe7,
+0x24,
+0x60,
+0xf1,
+0x06,
+0x2e,
+0x7b,
+0xb3,
+0xdd,
+0x56,
+0x47,
+0x25,
+0xe5,
+0x59,
+0xbf,
+0xe5,
+0xdd,
+0xd5,
+0x9a,
+0xa9,
+0x98,
+0x86,
+0x90,
+0xe4,
+0x57,
+0xa8,
+0x20,
+0xfa,
+0xd4,
+0xb6,
+0x9d,
+0x8c,
+0x70,
+0x98,
+0x20,
+0xf5,
+0x18,
+0xbd,
+0x99,
+0x7c,
+0x2a,
+0x80,
+0x8a,
+0x5d,
+0x0b,
+0x51,
+0x8c,
+0x9c,
+0x09,
+0x54,
+0x42,
+0x17,
+0xbf,
+0x66,
+0x0e,
+0xcd,
+0x4e,
+0x94,
+0x72,
+0x2b,
+0x87,
+0x0e,
+0xe7,
+0xf4,
+0x75,
+0x60,
+0xf5,
+0xa5,
+0x0b,
+0x03,
+0xc4,
+0x6f,
+0xf8,
+0x94,
+0x4a,
+0xbd,
+0x03,
+0xfb,
+0xb6,
+0x80,
+0xa3,
+0xf7,
+0x7a,
+0x09,
+0x4c,
+0x34,
+0x0b,
+0xee,
+0x51,
+0xda,
+0x4e,
+0x29,
+0x59,
+0xdc,
+0x4c,
+0xd9,
+0x0c,
+0x61,
+0x8f,
+0xf8,
+0xb6,
+0xe4,
+0xf7,
+0x78,
+0x95,
+0x1e,
+0x8e,
+0x9f,
+0x66,
+0x22,
+0x1f,
+0x65,
+0xf6,
+0xf4,
+0xee,
+0x82,
+0x45,
+0xa3,
+0x52,
+0x1f,
+0x23,
+0x4b,
+0x81,
+0xf1,
+0x75,
+0x9c,
+0xdb,
+0xb9,
+0x76,
+0xaf,
+0x5c,
+0xa9,
+0x15,
+0x3d,
+0x28,
+0x10,
+0xc9,
+0x8c,
+0x4f,
+0x42,
+0x95,
+0x5a,
+0x0e,
+0x81,
+0x5f,
+0xe8,
+0x96,
+0x4f,
+0x8f,
+0x6c,
+0x16,
+0xd0,
+0x41,
+0x1c,
+0x7b,
+0x90,
+0x3b,
+0xf5,
+0x51,
+0x55,
+0x82,
+0x68,
+0xc0,
+0x78,
+0xb0,
+0x11,
+0x49,
+0x22,
+0x8a,
+0x98,
+0x42,
+0x8d,
+0xe7,
+0x70,
+0x31,
+0x36,
+0xb9,
+0x36,
+0x12,
+0x99,
+0x86,
+0x4c,
+0x0b,
+0x31,
+0xd9,
+0xa9,
+0x7c,
+0xbb,
+0x2e,
+0x7d,
+0x9a,
+0x9d,
+0x14,
+0x22,
+0x0e,
+0xfe,
+0xd3,
+0x72,
+0xfd,
+0x4d,
+0x84,
+0x2c,
+0x5f,
+0x49,
+0x04,
+0x6d,
+0x52,
+0x66,
+0x7b,
+0x46,
+0x91,
+0xec,
+0xea,
+0x93,
+0x5e,
+0x8e,
+0xc8,
+0x64,
+0xaf,
+0xf8,
+0xe8,
+0x0b,
+0x7d,
+0x77,
+0xa8,
+0x63,
+0x2e,
+0xad,
+0xc5,
+0xf7,
+0xc5,
+0xfe,
+0x2b,
+0x91,
+0x82,
+0x11,
+0xd6,
+0xbe,
+0xf8,
+0x3f,
+0x32,
+0x30,
+0x67,
+0x74,
+0xff,
+0x3a,
+0x01,
+0x0d,
+0x2f,
+0xce,
+0x87,
+0x7a,
+0x85,
+0xb6,
+0xf4,
+0xf0,
+0x1d,
+0x3f,
+0x8e,
+0x3d,
+0x8e,
+0x2f,
+0xf0,
+0x64,
+0x72,
+0x50,
+0x68,
+0x3d,
+0x08,
+0x64,
+0xcb,
+0xbe,
+0xfd,
+0x4c,
+0x17,
+0x73,
+0xba,
+0xa4,
+0x1a,
+0x05,
+0x5b,
+0x0f,
+0x4a,
+0x51,
+0x1b,
+0x2f,
+0x58,
+0x2d,
+0x39,
+0x7f,
+0x2a,
+0x2a,
+0x77,
+0xc8,
+0x69,
+0xa6,
+0xd1,
+0x1a,
+0x84,
+0xbc,
+0xb7,
+0x6e,
+0x48,
+0x62,
+0x07,
+0x9e,
+0xe2,
+0x91,
+0x91,
+0x44,
+0x9c,
+0xa4,
+0xfc,
+0xa4,
+0xc0,
+0x4b,
+0x47,
+0x30,
+0x5a,
+0x00,
+0xf5,
+0xbb,
+0x3d,
+0x6c,
+0x5c,
+0xed,
+0xe3,
+0x08,
+0xa0,
+0x94,
+0xd6,
+0x1b,
+0xf7,
+0xf8,
+0xb5,
+0xd0,
+0x79,
+0x75,
+0xf7,
+0x93,
+0x77,
+0xc7,
+0x0c,
+0x0e,
+0xff,
+0xbd,
+0xde,
+0xc6,
+0xbb,
+0x29,
+0x51,
+0x3a,
+0x41,
+0xbe,
+0x2c,
+0x7d,
+0xe2,
+0x54,
+0x60,
+0x54,
+0xd1,
+0x73,
+0xa8,
+0x6a,
+0x53,
+0xa5,
+0x8e,
+0xd6,
+0xb7,
+0x3b,
+0xc6,
+0x22,
+0xba,
+0x3b,
+0x19,
+0x23,
+0xf2,
+0xab,
+0x2d,
+0xa0,
+0x1f,
+0x57,
+0x81,
+0x7a,
+0x89,
+0x11,
+0xef,
+0x57,
+0x5e,
+0xf8,
+0x3f,
+0x8c,
+0xf9,
+0x85,
+0xc1,
+0xbb,
+0xe2,
+0x78,
+0xa6,
+0x66,
+0xb2,
+0x1b,
+0xf6,
+0xfe,
+0x15,
+0xb8,
+0xc3,
+0xbc,
+0xb2,
+0x32,
+0x6b,
+0x88,
+0x7a,
+0xe5,
+0x18,
+0x6e,
+0x90,
+0xb3,
+0x63,
+0xe4,
+0x14,
+0x35,
+0x86,
+0xe1,
+0x76,
+0x43,
+0xd0,
+0x35,
+0x80,
+0xbd,
+0x90,
+0x2a,
+0x9f,
+0x84,
+0xa6,
+0x24,
+0xe2,
+0x00,
+0x14,
+0xb3,
+0x67,
+0x66,
+0x89,
+0x77,
+0xae,
+0x61,
+0xf4,
+0x78,
+0xfa,
+0xab,
+0xc4,
+0xec,
+0xfe,
+0x97,
+0x03,
+0xed,
+0xa2,
+0x98,
+0xa0,
+0xad,
+0x2e,
+0x4f,
+0xea,
+0x82,
+0x43,
+0xf3,
+0xee,
+0x7a,
+0xa4,
+0xff,
+0x48,
+0x8f,
+0xca,
+0x9e,
+0x09,
+0xb5,
+0xb9,
+0xcc,
+0x43,
+0x61,
+0xfe,
+0xe8,
+0xd2,
+0x6d,
+0x36,
+0x75,
+0xa5,
+0xf3,
+0x62,
+0x27,
+0xd9,
+0xf9,
+0xab,
+0xea,
+0x7e,
+0x49,
+0x97,
+0x91,
+0x63,
+0x86,
+0x4b,
+0x42,
+0x43,
+0xa8,
+0x76,
+0xe8,
+0xd9,
+0x02,
+0x1f,
+0x6d,
+0xff,
+0x94,
+0xfb,
+0xc6,
+0x91,
+0x7e,
+0x00,
+0xad,
+0xee,
+0xb5,
+0x92,
+0x4d,
+0x83,
+0x87,
+0x65,
+0xa2,
+0xff,
+0xb5,
+0x8e,
+0x86,
+0xd6,
+0xcf,
+0x08,
+0xae,
+0x5b,
+0xcd,
+0x8c,
+0x09,
+0xe0,
+0xa3,
+0x3b,
+0x97,
+0xdf,
+0x4f,
+0x54,
+0x0f,
+0x12,
+0x71,
+0xa6,
+0xec,
+0x9a,
+0xde,
+0xc6,
+0xf6,
+0xf5,
+0x69,
+0x2a,
+0xdd,
+0x76,
+0x61,
+0xd8,
+0xf0,
+0x71,
+0x77,
+0xec,
+0x44,
+0x51,
+0x47,
+0x8c,
+0xb3,
+0x05,
+0x03,
+0x07,
+0xcd,
+0x8d,
+0x24,
+0x9e,
+0x54,
+0x14,
+0xc5,
+0xa8,
+0x97,
+0x97,
+0x47,
+0x40,
+0xdd,
+0xab,
+0x58,
+0x76,
+0xd7,
+0xae,
+0xf1,
+0x7a,
+0xba,
+0xc8,
+0xae,
+0x13,
+0x45,
+0x6b,
+0xd7,
+0xbd,
+0xa9,
+0x1a,
+0x12,
+0x82,
+0x61,
+0xe6,
+0x23,
+0xb3,
+0xf1,
+0xc0,
+0xf6,
+0x33,
+0x31,
+0xc8,
+0xbc,
+0xcf,
+0x31,
+0xc8,
+0xc9,
+0xed,
+0x8a,
+0xc8,
+0x05,
+0xd7,
+0xfc,
+0x78,
+0xd8,
+0xf3,
+0xb3,
+0x9a,
+0x57,
+0x15,
+0x65,
+0x4a,
+0x29,
+0xc7,
+0x4b,
+0x27,
+0xfe,
+0x7e,
+0xf9,
+0xc0,
+0x19,
+0x32,
+0xc1,
+0xe1,
+0xb2,
+0xfa,
+0x50,
+0xd8,
+0x8e,
+0x75,
+0x15,
+0xc4,
+0xc4,
+0xdf,
+0x49,
+0x69,
+0xdb,
+0xfa,
+0x62,
+0x56,
+0x40,
+0x3c,
+0xa9,
+0xf2,
+0xb1,
+0x57,
+0xc2,
+0x07,
+0x6d,
+0x34,
+0x94,
+0x3a,
+0xfb,
+0xdd,
+0xc3,
+0x23,
+0x1f,
+0x71,
+0xa7,
+0x2d,
+0x51,
+0x24,
+0xd7,
+0xcb,
+0x72,
+0x3d,
+0xd4,
+0x30,
+0x07,
+0x91,
+0x53,
+0xb0,
+0x9b,
+0x09,
+0x1a,
+0x79,
+0x86,
+0x4d,
+0x05,
+0xcc,
+0x1f,
+0x09,
+0x40,
+0x39,
+0xfd,
+0xf7,
+0x17,
+0x66,
+0x9f,
+0x3a,
+0xe9,
+0xca,
+0x97,
+0x5c,
+0xc6,
+0xc8,
+0xae,
+0x49,
+0x1a,
+0xdc,
+0xc0,
+0x21,
+0xd6,
+0xf6,
+0x47,
+0x5f,
+0x53,
+0xe9,
+0xfd,
+0x46,
+0x14,
+0x86,
+0x4d,
+0xc1,
+0xaf,
+0x5c,
+0xef,
+0x00,
+0x25,
+0x0c,
+0xc1,
+0x1f,
+0x40,
+0xc9,
+0x0a,
+0xe6,
+0x0e,
+0xec,
+0xa8,
+0xf6,
+0x95,
+0x4f,
+0x22,
+0x36,
+0x94,
+0x19,
+0xc1,
+0x7f,
+0x82,
+0xa5,
+0xb1,
+0xfc,
+0x75,
+0x11,
+0x1c,
+0x4f,
+0x27,
+0xf3,
+0x5b,
+0xa9,
+0xd2,
+0xc2,
+0x78,
+0xed,
+0x44,
+0x64,
+0x76,
+0xcc,
+0x29,
+0x36,
+0x13,
+0x77,
+0xbe,
+0xe0,
+0xbc,
+0x1e,
+0x47,
+0x22,
+0x5a,
+0x92,
+0xc3,
+0x29,
+0x51,
+0xb5,
+0xe1,
+0x90,
+0x07,
+0xac,
+0x1c,
+0x33,
+0xa0,
+0x50,
+0x6e,
+0xd1,
+0xa6,
+0x8f,
+0x0a,
+0xe8,
+0x11,
+0x95,
+0x0d,
+0xfb,
+0x69,
+0x88,
+0x1d,
+0x8f,
+0xde,
+0x28,
+0x4f,
+0xaf,
+0x5f,
+0x8b,
+0xb1,
+0xc2,
+0x7f,
+0x0a,
+0xc8,
+0x5f,
+0xe7,
+0x9f,
+0x13,
+0x9d,
+0xc7,
+0x6b,
+0x7f,
+0x42,
+0x53,
+0x93,
+0xc4,
+0xd0,
+0xe3,
+0x3b,
+0xc9,
+0x39,
+0x58,
+0x7e,
+0x89,
+0x57,
+0xe6,
+0x61,
+0x9c,
+0xc6,
+0xcc,
+0x0d,
+0x6d,
+0xbd,
+0x62,
+0x69,
+0x38,
+0xc1,
+0x20,
+0x86,
+0x56,
+0x62,
+0x59,
+0xbd,
+0x13,
+0x7d,
+0xb0,
+0x56,
+0x2e,
+0xa8,
+0x38,
+0xf9,
+0x1f,
+0xb5,
+0xdc,
+0x9d,
+0x8c,
+0xa2,
+0x06,
+0xb0,
+0x3c,
+0x73,
+0x84,
+0x69,
+0xbd,
+0xfb,
+0x16,
+0x54,
+0xe9,
+0x19,
+0xb7,
+0x8e,
+0x01,
+0x23,
+0xc0,
+0xd2,
+0x79,
+0x9d,
+0x2c,
+0xde,
+0x50,
+0x18,
+0xba,
+0x0b,
+0xf4,
+0x4d,
+0x16,
+0x3b,
+0x54,
+0x26,
+0x2e,
+0x9b,
+0x30,
+0x22,
+0x3f,
+0x0f,
+0x52,
+0xcc,
+0x74,
+0xa2,
+0x64,
+0x0e,
+0x3e,
+0x4e,
+0x10,
+0x6d,
+0x5d,
+0xb7,
+0x3d,
+0xe7,
+0x31,
+0x97,
+0x96,
+0x19,
+0xdc,
+0x0e,
+0xd5,
+0x0b,
+0xc3,
+0x64,
+0xf6,
+0xd1,
+0xe6,
+0xdd,
+0xd2,
+0x21,
+0x2f,
+0xfd,
+0x0d,
+0xbb,
+0xe8,
+0x78,
+0xec,
+0x1f,
+0xbe,
+0x47,
+0x69,
+0x1d,
+0x76,
+0x6a,
+0x65,
+0x5c,
+0x10,
+0x2d,
+0xdc,
+0x54,
+0x0f,
+0xa5,
+0x7f,
+0x30,
+0x06,
+0x61,
+0x60,
+0xea,
+0xae,
+0xc3,
+0x17,
+0xb5,
+0x1f,
+0xcf,
+0xbe,
+0xa9,
+0x62,
+0x0a,
+0x8b,
+0x52,
+0x85,
+0xd2,
+0x12,
+0x73,
+0x64,
+0x7d,
+0xbe,
+0x84,
+0xc0,
+0xdc,
+0x9b,
+0xc6,
+0x5a,
+0x1a,
+0x3b,
+0xf4,
+0x1b,
+0xc0,
+0x9c,
+0x30,
+0xca,
+0x72,
+0x57,
+0xcc,
+0xca,
+0x6b,
+0x45,
+0x8e,
+0xd3,
+0xf1,
+0x61,
+0x55,
+0xc0,
+0xc2,
+0x13,
+0x08,
+0x0c,
+0x75,
+0x0b,
+0xbd,
+0x8d,
+0xe3,
+0xa0,
+0x76,
+0x73,
+0x66,
+0x9a,
+0x6f,
+0xa1,
+0x3c,
+0x19,
+0x12,
+0x75,
+0x1b,
+0xa9,
+0xc4,
+0x0f,
+0xbe,
+0xbc,
+0xbb,
+0x09,
+0x15,
+0x4b,
+0x3a,
+0x8b,
+0xc5,
+0x45,
+0x2e,
+0x91,
+0x1f,
+0x02,
+0xdb,
+0xa4,
+0x8b,
+0x4f,
+0xd9,
+0xd2,
+0xcd,
+0x57,
+0xdb,
+0x59,
+0x87,
+0x10,
+0xe7,
+0xde,
+0x22,
+0xec,
+0x2b,
+0x48,
+0xd3,
+0x21,
+0xc8,
+0x15,
+0xa3,
+0x25,
+0x31,
+0xf0,
+0x4f,
+0xf1,
+0x4b,
+0x73,
+0x73,
+0x09,
+0x67,
+0x80,
+0x3b,
+0x86,
+0xa2,
+0xc4,
+0x55,
+0xd5,
+0x89,
+0x87,
+0x9f,
+0x43,
+0x02,
+0x0e,
+0xe8,
+0xcc,
+0xa4,
+0xd4,
+0xc1,
+0x3c,
+0x84,
+0x52,
+0x6b,
+0x0f,
+0x53,
+0x89,
+0x04,
+0x7d,
+0xd0,
+0xed,
+0x83,
+0x2f,
+0x09,
+0xc4,
+0x3e,
+0xd6,
+0xb9,
+0xd0,
+0xa7,
+0x13,
+0x6b,
+0x85,
+0x99,
+0x22,
+0x6f,
+0xca,
+0x59,
+0xa0,
+0xdb,
+0x71,
+0x19,
+0x1f,
+0x37,
+0x00,
+0xe2,
+0x7b,
+0x46,
+0x81,
+0xd7,
+0x8e,
+0xdc,
+0x35,
+0x25,
+0x0f,
+0x8d,
+0x14,
+0xbd,
+0xfb,
+0x0e,
+0x14,
+0xbe,
+0x15,
+0x64,
+0xa4,
+0x55,
+0xad,
+0xc5,
+0xa3,
+0xd3,
+0xef,
+0x97,
+0x2a,
+0xa0,
+0x42,
+0xf7,
+0xb4,
+0x3e,
+0xc1,
+0x07,
+0xff,
+0x5c,
+0xe6,
+0x32,
+0x54,
+0x5b,
+0x71,
+0x32,
+0x24,
+0x82,
+0x21,
+0xf5,
+0xff,
+0x27,
+0x1b,
+0xbf,
+0x21,
+0x05,
+0x50,
+0x04,
+0x89,
+0x75,
+0xa4,
+0xdb,
+0x46,
+0x59,
+0xfc,
+0xc6,
+0xe5,
+0x06,
+0xe6,
+0x94,
+0x28,
+0x3e,
+0x22,
+0x6a,
+0x23,
+0x37,
+0x4c,
+0xc5,
+0xa1,
+0x88,
+0xe3,
+0xc1,
+0x8e,
+0x41,
+0xd0,
+0x01,
+0x1b,
+0x93,
+0x26,
+0xc8,
+0x26,
+0x78,
+0x78,
+0x77,
+0x51,
+0x59,
+0x7c,
+0x45,
+0x0e,
+0x8b,
+0xa7,
+0x99,
+0xc3,
+0x5e,
+0xb8,
+0xd5,
+0x25,
+0x78,
+0x4b,
+0xb0,
+0xdd,
+0x99,
+0xc7,
+0x9b,
+0xfc,
+0xb9,
+0x00,
+0x4e,
+0x3a,
+0x88,
+0xbd,
+0x94,
+0xf2,
+0x84,
+0x79,
+0x53,
+0x44,
+0x23,
+0x7c,
+0x17,
+0x4b,
+0xab,
+0xed,
+0xac,
+0x86,
+0x58,
+0x1b,
+0x94,
+0x16,
+0x8d,
+0xe8,
+0xb0,
+0x55,
+0x5e,
+0x11,
+0xc3,
+0x10,
+0x2d,
+0x53,
+0x7c,
+0x70,
+0xbc,
+0xd6,
+0x5b,
+0x23,
+0x3f,
+0x8b,
+0x57,
+0x23,
+0x8f,
+0xf5,
+0xdb,
+0x84,
+0x88,
+0x82,
+0x75,
+0xb0,
+0xa9,
+0xc6,
+0x90,
+0x0a,
+0xe7,
+0x68,
+0x5b,
+0x23,
+0xf0,
+0x08,
+0x46,
+0x43,
+0xe7,
+0x66,
+0x10,
+0xb5,
+0xe7,
+0x02,
+0xc8,
+0x8c,
+0x16,
+0x5e,
+0x0e,
+0x21,
+0xf8,
+0xc5,
+0xf9,
+0xee
+}};
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
--- /dev/null
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Microcode patch.
+ *
+ * Fam14 Microcode Patch rev 05000101 for 5020 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU/FAMILY/0x14
+ * @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Encrypt Patch code 05000101 for 5020 and equivalent
+
+CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101 =
+{{
+ 0x11,
+ 0x20,
+ 0x06,
+ 0x04,
+ 0x01,
+ 0x01,
+ 0x00,
+ 0x05,
+ 0x01,
+ 0x80,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x20,
+ 0x50,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0xaa,
+ 0xaa,
+ 0xaa,
+ 0x01,
+ 0xe9,
+ 0xee,
+ 0x42,
+ 0x6b,
+ 0x45,
+ 0xbd,
+ 0xcf,
+ 0x76,
+ 0xf0,
+ 0x6d,
+ 0x38,
+ 0xf1,
+ 0x7e,
+ 0x5e,
+ 0xb7,
+ 0x22,
+ 0x7d,
+ 0xdb,
+ 0x04,
+ 0xff,
+ 0xa4,
+ 0xb6,
+ 0x6c,
+ 0x5d,
+ 0x03,
+ 0x3d,
+ 0x35,
+ 0x7d,
+ 0x41,
+ 0x02,
+ 0x97,
+ 0x28,
+ 0xc9,
+ 0x02,
+ 0xd6,
+ 0x84,
+ 0xb6,
+ 0x3d,
+ 0xe6,
+ 0x2f,
+ 0x30,
+ 0x3f,
+ 0xc6,
+ 0x8c,
+ 0x5a,
+ 0xe3,
+ 0xbf,
+ 0x50,
+ 0x92,
+ 0xd7,
+ 0x1c,
+ 0x86,
+ 0xde,
+ 0xb9,
+ 0x48,
+ 0x63,
+ 0x02,
+ 0xa2,
+ 0xe6,
+ 0x80,
+ 0x7a,
+ 0x73,
+ 0x4f,
+ 0xe8,
+ 0xf7,
+ 0xee,
+ 0x3c,
+ 0xfc,
+ 0x8c,
+ 0xf3,
+ 0x9b,
+ 0x34,
+ 0x84,
+ 0x37,
+ 0x99,
+ 0x4a,
+ 0x8b,
+ 0x7d,
+ 0xbb,
+ 0xa8,
+ 0x30,
+ 0xf0,
+ 0x2f,
+ 0xad,
+ 0xac,
+ 0x74,
+ 0x14,
+ 0x18,
+ 0xa6,
+ 0x49,
+ 0x70,
+ 0x2d,
+ 0x75,
+ 0xe1,
+ 0x7e,
+ 0x97,
+ 0xa6,
+ 0xd6,
+ 0xc0,
+ 0xc7,
+ 0x7d,
+ 0x4f,
+ 0x1a,
+ 0x69,
+ 0xbf,
+ 0xb6,
+ 0xd5,
+ 0x5e,
+ 0xb8,
+ 0x66,
+ 0x63,
+ 0xd7,
+ 0xed,
+ 0x5c,
+ 0x07,
+ 0x02,
+ 0xb7,
+ 0x9e,
+ 0xc8,
+ 0x41,
+ 0x19,
+ 0x1f,
+ 0x72,
+ 0x02,
+ 0x5c,
+ 0xa7,
+ 0x58,
+ 0xd2,
+ 0x30,
+ 0x42,
+ 0x54,
+ 0x4f,
+ 0xd4,
+ 0xc7,
+ 0xc7,
+ 0x5e,
+ 0x35,
+ 0x5e,
+ 0x79,
+ 0x9a,
+ 0x82,
+ 0x31,
+ 0xa9,
+ 0xe3,
+ 0x56,
+ 0x15,
+ 0x63,
+ 0x29,
+ 0xe6,
+ 0xfc,
+ 0x8a,
+ 0xa6,
+ 0x50,
+ 0x9b,
+ 0xec,
+ 0xe1,
+ 0x1c,
+ 0x1d,
+ 0xef,
+ 0xcb,
+ 0x6f,
+ 0x08,
+ 0x4d,
+ 0x8a,
+ 0x5e,
+ 0xa8,
+ 0xb6,
+ 0x97,
+ 0x6c,
+ 0x97,
+ 0x32,
+ 0x0b,
+ 0x8a,
+ 0x26,
+ 0x44,
+ 0xce,
+ 0xdd,
+ 0xbb,
+ 0xdd,
+ 0xa3,
+ 0x53,
+ 0xc1,
+ 0x22,
+ 0xfd,
+ 0xf6,
+ 0xb2,
+ 0x5b,
+ 0x94,
+ 0x6e,
+ 0x47,
+ 0x48,
+ 0xae,
+ 0xc8,
+ 0xfb,
+ 0x5d,
+ 0x43,
+ 0x29,
+ 0xd2,
+ 0x37,
+ 0xd6,
+ 0xc0,
+ 0x3c,
+ 0x00,
+ 0xb0,
+ 0x8f,
+ 0xa7,
+ 0x4b,
+ 0x9d,
+ 0x33,
+ 0xb3,
+ 0x17,
+ 0xfb,
+ 0x12,
+ 0x0e,
+ 0x52,
+ 0xe3,
+ 0xd5,
+ 0xfe,
+ 0xf9,
+ 0xf4,
+ 0x25,
+ 0xf3,
+ 0x91,
+ 0xe1,
+ 0x9a,
+ 0x26,
+ 0x5a,
+ 0x47,
+ 0xfe,
+ 0xb9,
+ 0xb8,
+ 0xc9,
+ 0x12,
+ 0x74,
+ 0xca,
+ 0x50,
+ 0x54,
+ 0x1e,
+ 0x57,
+ 0x39,
+ 0x40,
+ 0xec,
+ 0x5e,
+ 0x71,
+ 0x07,
+ 0xc4,
+ 0x72,
+ 0x58,
+ 0xb1,
+ 0xb8,
+ 0xf9,
+ 0x30,
+ 0x39,
+ 0x77,
+ 0x8b,
+ 0x7c,
+ 0xaf,
+ 0x08,
+ 0xdf,
+ 0x27,
+ 0xae,
+ 0x42,
+ 0xe7,
+ 0x45,
+ 0xf0,
+ 0x05,
+ 0x9a,
+ 0xfa,
+ 0x30,
+ 0x3f,
+ 0xaf,
+ 0x8b,
+ 0xf0,
+ 0xcf,
+ 0xab,
+ 0x48,
+ 0x96,
+ 0x65,
+ 0x8e,
+ 0xde,
+ 0x3f,
+ 0x9f,
+ 0x65,
+ 0x42,
+ 0x96,
+ 0x6a,
+ 0x19,
+ 0xb6,
+ 0xb9,
+ 0xd5,
+ 0x53,
+ 0x0c,
+ 0x21,
+ 0xe9,
+ 0xd7,
+ 0xf6,
+ 0xd1,
+ 0xc8,
+ 0x59,
+ 0x17,
+ 0xdb,
+ 0x77,
+ 0x91,
+ 0x19,
+ 0xb9,
+ 0xb9,
+ 0xb6,
+ 0x3a,
+ 0x65,
+ 0xbe,
+ 0x65,
+ 0x79,
+ 0x77,
+ 0x83,
+ 0xc4,
+ 0x9f,
+ 0xae,
+ 0xc5,
+ 0x76,
+ 0x29,
+ 0x39,
+ 0x44,
+ 0x2f,
+ 0x06,
+ 0x6d,
+ 0x08,
+ 0xbb,
+ 0x33,
+ 0x27,
+ 0x4e,
+ 0x50,
+ 0x43,
+ 0x9f,
+ 0x88,
+ 0x28,
+ 0xb6,
+ 0x57,
+ 0x8e,
+ 0x53,
+ 0x15,
+ 0x20,
+ 0xb0,
+ 0xf8,
+ 0x78,
+ 0x24,
+ 0x32,
+ 0xf8,
+ 0xf7,
+ 0x45,
+ 0x4b,
+ 0x05,
+ 0xa4,
+ 0xe0,
+ 0xbe,
+ 0xfe,
+ 0xc5,
+ 0x70,
+ 0xd3,
+ 0xbe,
+ 0x70,
+ 0xd7,
+ 0xa2,
+ 0xf6,
+ 0x33,
+ 0x4f,
+ 0x57,
+ 0x34,
+ 0xbc,
+ 0x36,
+ 0x3e,
+ 0x78,
+ 0x92,
+ 0xfc,
+ 0xcd,
+ 0x4e,
+ 0xe0,
+ 0x64,
+ 0x69,
+ 0x4f,
+ 0x49,
+ 0x07,
+ 0x07,
+ 0x32,
+ 0xba,
+ 0x52,
+ 0x01,
+ 0xcb,
+ 0xb7,
+ 0x8f,
+ 0x92,
+ 0x4c,
+ 0x0f,
+ 0x6d,
+ 0x27,
+ 0x8c,
+ 0x9c,
+ 0x0a,
+ 0x53,
+ 0x5d,
+ 0x70,
+ 0xd8,
+ 0xb2,
+ 0x2f,
+ 0xe5,
+ 0x42,
+ 0x10,
+ 0x0f,
+ 0x71,
+ 0x90,
+ 0x71,
+ 0xea,
+ 0x9c,
+ 0x3d,
+ 0xa4,
+ 0x7f,
+ 0x1a,
+ 0xcc,
+ 0x1b,
+ 0xd3,
+ 0x75,
+ 0x6f,
+ 0x3a,
+ 0xaa,
+ 0xa7,
+ 0xaf,
+ 0x97,
+ 0x2c,
+ 0xf4,
+ 0x16,
+ 0x03,
+ 0xe0,
+ 0x0c,
+ 0xfc,
+ 0xe8,
+ 0x8b,
+ 0x42,
+ 0x5f,
+ 0x4e,
+ 0x6b,
+ 0xc1,
+ 0x99,
+ 0x4a,
+ 0x7f,
+ 0x50,
+ 0x45,
+ 0x81,
+ 0x51,
+ 0x2c,
+ 0xab,
+ 0x1e,
+ 0x90,
+ 0x78,
+ 0xf5,
+ 0xb5,
+ 0x41,
+ 0xf0,
+ 0x9d,
+ 0xd1,
+ 0x7e,
+ 0x98,
+ 0x16,
+ 0x66,
+ 0xba,
+ 0xa3,
+ 0xa3,
+ 0xf5,
+ 0x69,
+ 0xa3,
+ 0x5d,
+ 0x64,
+ 0x2d,
+ 0x1f,
+ 0x07,
+ 0x5a,
+ 0x84,
+ 0x62,
+ 0x6d,
+ 0xa2,
+ 0xa7,
+ 0xbb,
+ 0x12,
+ 0x18,
+ 0x33,
+ 0x17,
+ 0x57,
+ 0x5f,
+ 0x0a,
+ 0x11,
+ 0x6a,
+ 0x39,
+ 0x61,
+ 0x9f,
+ 0x77,
+ 0x9e,
+ 0xcc,
+ 0xe6,
+ 0x74,
+ 0xee,
+ 0x42,
+ 0x16,
+ 0x34,
+ 0xf0,
+ 0x22,
+ 0xe5,
+ 0xf6,
+ 0xef,
+ 0xc7,
+ 0xfe,
+ 0x40,
+ 0xed,
+ 0xbd,
+ 0xa6,
+ 0xe4,
+ 0x38,
+ 0x5a,
+ 0x46,
+ 0x98,
+ 0x63,
+ 0x24,
+ 0xac,
+ 0x1a,
+ 0x42,
+ 0x04,
+ 0x50,
+ 0x92,
+ 0x77,
+ 0x22,
+ 0x8e,
+ 0xfc,
+ 0x25,
+ 0xcc,
+ 0x70,
+ 0x9c,
+ 0x47,
+ 0x79,
+ 0xca,
+ 0x98,
+ 0x58,
+ 0x27,
+ 0x21,
+ 0x99,
+ 0x93,
+ 0x13,
+ 0xdd,
+ 0x0b,
+ 0xe1,
+ 0x1f,
+ 0xd3,
+ 0x9b,
+ 0x71,
+ 0xe2,
+ 0xac,
+ 0xd5,
+ 0x04,
+ 0xf2,
+ 0x99,
+ 0x0e,
+ 0x02,
+ 0x40,
+ 0x59,
+ 0xff,
+ 0x0b,
+ 0x80,
+ 0x3f,
+ 0x44,
+ 0x3e,
+ 0xd1,
+ 0xc7,
+ 0x53,
+ 0x0b,
+ 0x49,
+ 0x47,
+ 0xc4,
+ 0xdf,
+ 0x98,
+ 0x4b,
+ 0xc9,
+ 0x64,
+ 0xd2,
+ 0x2e,
+ 0xfd,
+ 0x3e,
+ 0x29,
+ 0xa3,
+ 0xea,
+ 0x9a,
+ 0x61,
+ 0xee,
+ 0xac,
+ 0xc2,
+ 0x01,
+ 0x37,
+ 0x81,
+ 0x25,
+ 0x9f,
+ 0x52,
+ 0x61,
+ 0x63,
+ 0xf7,
+ 0xbe,
+ 0x9d,
+ 0x6c,
+ 0x53,
+ 0x22,
+ 0xcb,
+ 0x28,
+ 0xba,
+ 0xcb,
+ 0xc1,
+ 0xc2,
+ 0xf9,
+ 0x37,
+ 0xa2,
+ 0xd9,
+ 0xdc,
+ 0x72,
+ 0x10,
+ 0xf7,
+ 0xea,
+ 0xf4,
+ 0x00,
+ 0x8d,
+ 0xc4,
+ 0xfd,
+ 0xe2,
+ 0x53,
+ 0xf3,
+ 0xe9,
+ 0x2c,
+ 0xa6,
+ 0x84,
+ 0xe9,
+ 0xf8,
+ 0xdf,
+ 0xe8,
+ 0xcf,
+ 0xed,
+ 0xce,
+ 0x8b,
+ 0xc9,
+ 0xef,
+ 0x8f,
+ 0xcf,
+ 0x17,
+ 0xe2,
+ 0x13,
+ 0xa4,
+ 0xfa,
+ 0x82,
+ 0xb8,
+ 0x9b,
+ 0x9e,
+ 0xd3,
+ 0x14,
+ 0xed,
+ 0x33,
+ 0x67,
+ 0xdc,
+ 0x88,
+ 0x4e,
+ 0x46,
+ 0x3d,
+ 0xe1,
+ 0x1a,
+ 0xe7,
+ 0x18,
+ 0xd8,
+ 0xe9,
+ 0xc1,
+ 0xe3,
+ 0x71,
+ 0x3a,
+ 0x10,
+ 0x9e,
+ 0x47,
+ 0xa9,
+ 0x27,
+ 0xfe,
+ 0x7e,
+ 0x9f,
+ 0x06,
+ 0x55,
+ 0x1b,
+ 0xa2,
+ 0xbd,
+ 0x40,
+ 0xc3,
+ 0xc8,
+ 0x6b,
+ 0xe3,
+ 0x4b,
+ 0xff,
+ 0x95,
+ 0x73,
+ 0xeb,
+ 0xff,
+ 0xe9,
+ 0x26,
+ 0xc6,
+ 0x5a,
+ 0x2f,
+ 0xc4,
+ 0x5e,
+ 0x45,
+ 0xf4,
+ 0xd9,
+ 0x4e,
+ 0x88,
+ 0x0a,
+ 0xaf,
+ 0x29,
+ 0xfb,
+ 0x09,
+ 0x29,
+ 0xe5,
+ 0x86,
+ 0xb7,
+ 0x87,
+ 0x5f,
+ 0xea,
+ 0x4b,
+ 0xc4,
+ 0x42,
+ 0x88,
+ 0x3b,
+ 0xfc,
+ 0x34,
+ 0x57,
+ 0x3d,
+ 0xf4,
+ 0xef,
+ 0xee,
+ 0x14,
+ 0x28,
+ 0x7b,
+ 0x6c,
+ 0x05,
+ 0x41,
+ 0xe9,
+ 0x28,
+ 0xd8,
+ 0xd5,
+ 0xba,
+ 0x71,
+ 0x7a,
+ 0x52,
+ 0x89,
+ 0x2f,
+ 0x86,
+ 0x38,
+ 0x32,
+ 0x9f,
+ 0xbd,
+ 0x3c,
+ 0xa0,
+ 0x89,
+ 0x5c,
+ 0xb5,
+ 0x8d,
+ 0xb9,
+ 0x90,
+ 0x6c,
+ 0xb2,
+ 0xd5,
+ 0x59,
+ 0x73,
+ 0xa4,
+ 0x30,
+ 0xa9,
+ 0xf3,
+ 0x58,
+ 0xfb,
+ 0xc6,
+ 0x3c,
+ 0x0b,
+ 0x45,
+ 0xac,
+ 0x7d,
+ 0x72,
+ 0x32,
+ 0xa6,
+ 0x30,
+ 0x76,
+ 0x3a,
+ 0xde,
+ 0xf6,
+ 0x98,
+ 0xfc,
+ 0xca,
+ 0x69,
+ 0xbf,
+ 0xa9,
+ 0xf0,
+ 0x17,
+ 0x7a,
+ 0xc4,
+ 0x54,
+ 0x49,
+ 0x8e,
+ 0x91,
+ 0xa6,
+ 0x59,
+ 0xab,
+ 0x2b,
+ 0x84,
+ 0xb3,
+ 0x90,
+ 0xab,
+ 0xf8,
+ 0xf0,
+ 0x7d,
+ 0x6d,
+ 0xa3,
+ 0x33,
+ 0xb5,
+ 0x7d,
+ 0xe0,
+ 0x4b,
+ 0x9e,
+ 0x39,
+ 0x67,
+ 0x92,
+ 0x1a,
+ 0x56,
+ 0xa9,
+ 0x9c,
+ 0x95,
+ 0x34,
+ 0xd7,
+ 0x1d,
+ 0x0b,
+ 0x45,
+ 0x9d,
+ 0xa5,
+ 0x82,
+ 0x39,
+ 0x36,
+ 0x35,
+ 0x31,
+ 0xe3,
+ 0x73,
+ 0xf7,
+ 0x79,
+ 0xda,
+ 0x0b,
+ 0x0d,
+ 0xea,
+ 0x6b,
+ 0x8a,
+ 0xff,
+ 0xc0,
+ 0x2a,
+ 0x3f,
+ 0x7a,
+ 0x9c,
+ 0x9e,
+ 0xbd,
+ 0x53,
+ 0x65,
+ 0x1c,
+ 0x8c,
+ 0xed,
+ 0xb5,
+ 0x45,
+ 0x85,
+ 0xa4,
+ 0xfb,
+ 0xa9,
+ 0xb0,
+ 0xf3,
+ 0x3c,
+ 0xe5,
+ 0xc2,
+ 0xb5,
+ 0xb0,
+ 0xf2,
+ 0x7f,
+ 0xf1,
+ 0x2d,
+ 0xa1,
+ 0xe7,
+ 0x2f,
+ 0xa3,
+ 0x67,
+ 0xf4,
+ 0xd6,
+ 0x4b,
+ 0xa7,
+ 0xb5,
+ 0xb9,
+ 0xc3,
+ 0x28,
+ 0x80,
+ 0x52,
+ 0xd2,
+ 0x44,
+ 0x18,
+ 0x20,
+ 0xca,
+ 0x58,
+ 0x74,
+ 0x11,
+ 0x23,
+ 0x53,
+ 0x79,
+ 0x10,
+ 0xd5,
+ 0xf3,
+ 0x85,
+ 0xda,
+ 0x31,
+ 0x1c,
+ 0x4e,
+ 0x42,
+ 0x6c,
+ 0x16,
+ 0x9f,
+ 0x4d,
+ 0xfa,
+ 0x2d,
+ 0x24,
+ 0x26,
+ 0xcd,
+ 0xc1,
+ 0x74,
+ 0x3c,
+ 0x06,
+ 0xe0,
+ 0x1d,
+ 0xcf,
+ 0xee,
+ 0x55,
+ 0x6a,
+ 0xa2,
+ 0x23,
+ 0x00,
+ 0x0a,
+ 0x69,
+ 0x4a,
+ 0x9a,
+ 0xd1,
+ 0x58,
+ 0xfe,
+ 0xe3,
+ 0x25,
+ 0x13,
+ 0xef,
+ 0xde,
+ 0x87,
+ 0x5b,
+ 0x25,
+ 0xa9,
+ 0xba,
+ 0x3b,
+ 0x9d,
+ 0xd0,
+ 0xb2,
+ 0xbb,
+ 0xc4,
+ 0x17,
+ 0x72,
+ 0xe4,
+ 0xeb,
+ 0x02,
+ 0x8f,
+ 0x08,
+ 0x4a,
+ 0x57,
+ 0xee,
+ 0x58,
+ 0x3f,
+ 0x7a,
+ 0x24,
+ 0xef,
+ 0x8b,
+ 0xe3,
+ 0xbb,
+ 0xeb,
+ 0x7b,
+ 0x5a,
+ 0x02,
+ 0x24,
+ 0x74,
+ 0xfb,
+ 0xe1,
+ 0x03,
+ 0xe4,
+ 0x8c,
+ 0x3e,
+ 0x7b,
+ 0xe8,
+ 0x5f,
+ 0x38,
+ 0x0d,
+ 0x78,
+ 0x3d,
+ 0x89,
+ 0xff,
+ 0xa6,
+ 0x17,
+ 0xb0,
+ 0xdd,
+ 0x80,
+ 0x3b,
+ 0x60,
+ 0x62,
+ 0x81,
+ 0x7b,
+ 0x55,
+ 0xc7,
+ 0xc6,
+ 0x69,
+ 0xda,
+ 0xf7,
+ 0x17,
+ 0xa3,
+ 0x2f,
+ 0xf9,
+ 0x00,
+ 0x77,
+ 0x4b,
+ 0x3f,
+ 0xfd,
+ 0x94,
+ 0x08,
+ 0x10,
+ 0x35,
+ 0xb6,
+ 0x3d,
+ 0xa1,
+ 0x1d,
+ 0x8f,
+ 0x0e,
+ 0xcc,
+ 0xe5,
+ 0xe7,
+ 0x19,
+ 0x86,
+ 0x13,
+ 0xea,
+ 0x5f,
+ 0x08,
+ 0x7a,
+ 0x4f,
+ 0x59,
+ 0x72,
+ 0x59,
+ 0xa5,
+ 0xc1,
+ 0x93,
+ 0x60,
+ 0x46,
+ 0x7d,
+ 0x99,
+ 0xf7,
+ 0xff,
+ 0x85,
+ 0x9b,
+ 0x63,
+ 0x15,
+ 0x7f,
+ 0xb3,
+ 0xab,
+ 0xfb,
+ 0x49,
+ 0xd9,
+ 0xcf,
+ 0xdd,
+ 0xe7,
+ 0x6a,
+ 0x9b,
+ 0xeb,
+ 0x97,
+ 0x34,
+ 0x08,
+ 0x11,
+ 0xa9,
+ 0x3e,
+ 0x49,
+ 0x21,
+ 0xe5,
+ 0x74,
+ 0xf0,
+ 0x6e,
+ 0x9a,
+ 0x47,
+ 0x51,
+ 0xc0,
+ 0x3f,
+ 0x5f,
+ 0xa3,
+ 0xf0,
+ 0xf8,
+ 0x37,
+ 0x3e,
+ 0xc7,
+ 0xb2,
+ 0xd9,
+ 0x6f,
+ 0xc9,
+ 0x15,
+ 0x9d,
+ 0x3f,
+ 0xa3,
+ 0x00,
+ 0xec,
+ 0x1b,
+ 0xec,
+ 0x03,
+ 0xd7,
+ 0x4b,
+ 0x45,
+ 0x0a,
+ 0xb6,
+ 0xbd,
+ 0xac,
+ 0x5f,
+ 0xdf,
+ 0x47,
+ 0x0c,
+ 0x3a,
+ 0xd6,
+ 0x71,
+ 0xaf,
+ 0x5f,
+ 0x73,
+ 0xbd,
+ 0x31,
+ 0xf9,
+ 0xa6,
+ 0x41,
+ 0x27,
+ 0x6a,
+ 0x01,
+ 0x22,
+ 0xc5,
+ 0x1c,
+ 0x9f,
+ 0x24,
+ 0x88,
+ 0xd2,
+ 0xa5,
+ 0x7b,
+ 0x03,
+ 0xd5,
+ 0x91,
+ 0x50,
+ 0x1a,
+ 0xfc,
+ 0x40,
+ 0x32,
+ 0x3d,
+ 0x05,
+ 0x2f,
+ 0xda,
+ 0x67,
+ 0x04,
+ 0x0e,
+ 0x9b,
+ 0x6b,
+ 0xfd,
+ 0xa5,
+ 0xba,
+ 0xe3,
+ 0x85,
+ 0x23,
+ 0x7c,
+ 0x35,
+ 0x70,
+ 0x06,
+ 0x38,
+ 0x15,
+ 0x4f,
+ 0x29,
+ 0x98,
+ 0xaa,
+ 0x83,
+ 0xc0,
+ 0xf2,
+ 0xd3,
+ 0x29,
+ 0x78,
+ 0xbd,
+ 0x7c,
+ 0x58,
+ 0x15,
+ 0xb0,
+ 0x15,
+ 0x13,
+ 0x46,
+ 0x47,
+ 0xa8,
+ 0x09,
+ 0xec,
+ 0x79,
+ 0x40,
+ 0x62,
+ 0xd4,
+ 0xf3,
+ 0x05,
+ 0xc7,
+ 0x49,
+ 0x75,
+ 0x9f,
+ 0x16,
+ 0xf7,
+ 0x2d,
+ 0xd8,
+ 0x11,
+ 0xed,
+ 0x4a,
+ 0x0e,
+ 0xe4,
+ 0x41,
+ 0xa1,
+ 0xe6,
+ 0x20,
+ 0x09,
+ 0x44,
+ 0x77,
+ 0xbb,
+ 0xaa,
+ 0x2b,
+ 0xaf,
+ 0x4c,
+ 0x89,
+ 0x89,
+ 0x30,
+ 0x71,
+ 0xf2,
+ 0xe4,
+ 0x57,
+ 0xd3,
+ 0xa1,
+ 0x08,
+ 0x6a,
+ 0x92,
+ 0xcc,
+ 0xa1,
+ 0x30,
+ 0x16,
+ 0xe1,
+ 0xb0,
+ 0x7a,
+ 0x84,
+ 0xfb,
+ 0xd6,
+ 0x68,
+ 0xee,
+ 0x34,
+ 0xd6,
+ 0x61,
+ 0x62,
+ 0x2d,
+ 0xde,
+ 0x9c,
+ 0x08,
+ 0xdb,
+ 0x45,
+ 0x47,
+ 0x8f,
+ 0xc6,
+ 0xf9,
+ 0x26,
+ 0xfd,
+ 0xc2,
+ 0xdc,
+ 0xc2,
+ 0xfe,
+ 0xcd,
+ 0x2b,
+ 0xde,
+ 0x66,
+ 0x95,
+ 0x36,
+ 0x63,
+ 0x42,
+ 0x8f,
+ 0x72,
+ 0x52,
+ 0x8b,
+ 0x5a,
+ 0x6c,
+ 0x1f,
+ 0x8c,
+ 0x90,
+ 0x50,
+ 0xf8,
+ 0xec,
+ 0x9c,
+ 0xcb,
+ 0xb2,
+ 0xfa,
+ 0x29,
+ 0x57,
+ 0xaa,
+ 0x99,
+ 0x66,
+ 0x49,
+ 0xac,
+ 0x87,
+ 0x76,
+ 0xfd,
+ 0xa9,
+ 0x44,
+ 0x7e,
+ 0x40,
+ 0x66,
+ 0x0e,
+ 0xcc,
+ 0x74,
+ 0x75,
+ 0x21,
+ 0xa7,
+ 0xae,
+ 0xe0,
+ 0xeb,
+ 0x06,
+ 0x59,
+ 0xf6,
+ 0x05,
+ 0xd9,
+ 0x05,
+ 0xde,
+ 0x91,
+ 0x64,
+ 0xb5,
+ 0x38,
+ 0x13,
+ 0x68,
+ 0x1a,
+ 0xd2,
+ 0x84,
+ 0x5c,
+ 0x5f,
+ 0x06,
+ 0x41,
+ 0x5b,
+ 0x2e,
+ 0x8d,
+ 0xa7,
+ 0x6f,
+ 0x04,
+ 0x86,
+ 0x93,
+ 0xf3,
+ 0xca,
+ 0xee,
+ 0x1f,
+ 0xe3,
+ 0xc6,
+ 0x31,
+ 0x1b,
+ 0xaf,
+ 0xa0,
+ 0x89,
+ 0xa1,
+ 0xb2,
+ 0x30,
+ 0x37,
+ 0x3d,
+ 0x4d,
+ 0x92,
+ 0x9e,
+ 0x77,
+ 0x20,
+ 0xe5,
+ 0xe9,
+ 0xb7,
+ 0x64,
+ 0xbe,
+ 0x4e,
+ 0x08,
+ 0x79,
+ 0x8d,
+ 0xe6,
+ 0x24,
+ 0x1b,
+ 0x26,
+ 0x62,
+ 0x18,
+ 0xc5,
+ 0x27,
+ 0xb0,
+ 0x47,
+ 0x18,
+ 0x51,
+ 0xf4,
+ 0xb8,
+ 0x1a,
+ 0x7b,
+ 0xda,
+ 0xf1,
+ 0xa2,
+ 0x34,
+ 0x6e,
+ 0xa8,
+ 0x75,
+ 0x61,
+ 0x79,
+ 0x99,
+ 0x2d,
+ 0x49,
+ 0x79,
+ 0xe8,
+ 0x85,
+ 0x6e,
+ 0xc8,
+ 0x36,
+ 0xd7,
+ 0xba,
+ 0x3d,
+ 0x67,
+ 0xeb,
+ 0x20,
+ 0x36,
+ 0x42,
+ 0x6f,
+ 0xe8,
+ 0x5a,
+ 0xde,
+ 0x34,
+ 0xa9,
+ 0xce,
+ 0xac,
+ 0x4d,
+ 0xeb,
+ 0x77,
+ 0x7a,
+ 0x1f,
+ 0x93,
+ 0xd4,
+ 0xdf,
+ 0x32,
+ 0x43,
+ 0x8f,
+ 0x81,
+ 0x43,
+ 0xc9,
+ 0xa1,
+ 0xc9,
+ 0xc5,
+ 0xe6,
+ 0x81,
+ 0xb7,
+ 0xc4,
+ 0x10,
+ 0x09,
+ 0x74,
+ 0xa8,
+ 0xa9,
+ 0xc3,
+ 0x36,
+ 0x25,
+ 0x91,
+ 0x7f,
+ 0xfc,
+ 0xb6,
+ 0x78,
+ 0xae,
+ 0x12,
+ 0xa3,
+ 0x47,
+ 0xe0,
+ 0xde,
+ 0x3f,
+ 0xd9,
+ 0xad,
+ 0x1e,
+ 0x7b,
+ 0xda,
+ 0xab,
+ 0xe3,
+ 0x6e,
+ 0xeb,
+ 0xeb,
+ 0x86,
+ 0xad,
+ 0x8a,
+ 0x44,
+ 0x90,
+ 0x0d,
+ 0x34,
+ 0x80,
+ 0x00,
+ 0x6a,
+ 0x6b,
+ 0x62,
+ 0x31,
+ 0xb3,
+ 0xa8,
+ 0x10,
+ 0x8a,
+ 0x06,
+ 0x94,
+ 0x97,
+ 0x88,
+ 0x3e,
+ 0x5d,
+ 0x0c,
+ 0xff,
+ 0xee,
+ 0xd7,
+ 0x22,
+ 0x6b,
+ 0x6e,
+ 0x8a,
+ 0xf1,
+ 0xa1,
+ 0x1c,
+ 0x59,
+ 0x2c,
+ 0x3f,
+ 0x99,
+ 0xcf,
+ 0xea,
+ 0x1b,
+ 0x11,
+ 0x23,
+ 0x96,
+ 0x80,
+ 0x21,
+ 0x58,
+ 0xff,
+ 0xc4,
+ 0x6a,
+ 0xb0,
+ 0xd1,
+ 0x7d,
+ 0xd4,
+ 0xe7,
+ 0x1a,
+ 0x68,
+ 0xd7,
+ 0x00
+}};
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
\ No newline at end of file
--- /dev/null
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family 14 Ontario CPB Initialization
+ *
+ * Enables core performance boost.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU/Family/0x14/ON
+ * @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF14PowerMgmt.h"
+#include "GnbRegistersON.h"
+#include "NbSmuLib.h"
+#include "NbSmuLib.h"
+#include "cpuFeatures.h"
+#include "cpuCpb.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G1_PEICC)
+
+#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for checking whether or not CPB is supported.
+ *
+ * @param[in] CpbServices The current CPU's family services.
+ * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in] Socket Zero based socket number to check.
+ * @param[in] StdHeader Config handle for library and services.
+ *
+ * @retval TRUE CPB is supported.
+ * @retval FALSE CPB is not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F14OnIsCpbSupported (
+ IN CPB_FAMILY_SERVICES *CpbServices,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN UINT32 Socket,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ PCI_ADDR PciAddress;
+ CPB_CTRL_REGISTER CpbControl;
+ CPU_LOGICAL_ID CpuFamilyRevision;
+
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
+ return FALSE;
+ } else {
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+ return (BOOLEAN) (CpbControl.NumBoostStates != 0);
+ }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * BSC entry point for enabling Core Performance Boost.
+ *
+ * Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
+ *
+ * @param[in] CpbServices The current CPU's family services.
+ * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in] EntryPoint Current CPU feature dispatch point.
+ * @param[in] Socket Zero based socket number to check.
+ * @param[in] StdHeader Config handle for library and services.
+ *
+ * @retval AGESA_SUCCESS Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F14OnInitializeCpb (
+ IN CPB_FAMILY_SERVICES *CpbServices,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN UINT64 EntryPoint,
+ IN UINT32 Socket,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ PCI_ADDR PciAddress;
+ CPB_CTRL_REGISTER CpbControl;
+ LPMV_SCALAR2_REGISTER LpmvScalar2;
+ SMUx0B_x8580_STRUCT SMUx0Bx8580;
+
+ if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
+ // F4x14C [25:24] ApmCstExtPol = 1
+ PciAddress.AddressValue = LPMV_SCALAR2_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
+ LpmvScalar2.ApmCstExtPol = 1;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &LpmvScalar2, StdHeader);
+ // F4x15C [1:0] BoostSrc = 1
+ // F4x15C [29] BoostEnAllCores = 1
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+ CpbControl.BoostSrc = 1;
+ CpbControl.BoostEnAllCores = 1;
+ IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
+ LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
+ } else if ((EntryPoint & CPU_FEAT_INIT_LATE_END) != 0) {
+ // Ensure that the recommended settings have been programmed into SMUx0B_x8580, then
+ // interrupt the SMU with service index 12h.
+ NbSmuRcuRegisterRead (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, StdHeader);
+ SMUx0Bx8580.Field.PdmPeriod = 0x1388;
+ SMUx0Bx8580.Field.PdmParamLoc = 0;
+ SMUx0Bx8580.Field.PdmCacEn = 1;
+ SMUx0Bx8580.Field.PdmUnit = 1;
+ SMUx0Bx8580.Field.PdmEn = 1;
+ NbSmuRcuRegisterWrite (SMUx0B_x8580_ADDRESS, &SMUx0Bx8580.Value, 1, TRUE, StdHeader);
+ NbSmuServiceRequest (0x12, TRUE, StdHeader);
+ }
+
+ return AGESA_SUCCESS;
+}
+
+CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport =
+{
+ 0,
+ F14OnIsCpbSupported,
+ F14OnInitializeCpb
+};
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x14
- * @e \$Revision: 36418 $ @e \$Date: 2010-08-18 17:00:58 +0800 (Wed, 18 Aug 2010) $
+ * @e \$Revision: 48589 $ @e \$Date: 2011-03-10 09:27:00 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14OnMicrocodeEquivalenceTable (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **OnEquivalenceTablePtr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
{
0x5000, 0x5000,
0x5001, 0x5001,
- 0x5010, 0x5010
+ 0x5010, 0x5010,
+ 0x5020, 0x5020
};
// Unencrypted equivalent
{
0x5000, 0x5800,
0x5001, 0x5801,
- 0x5010, 0x5810
+ 0x5010, 0x5810,
+ 0x5020, 0x5820
};
*----------------------------------------------------------------------------------------
*/
VOID
+GetF14OnEarlyInitOnCoreTable (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
F14OnLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
{
*Table = F14OnEarlyInitOnCoreTable;
- F14EarlySampleCoreSupport.F14GetEarlyInitTableHook (Table, StdHeader);
+ F14EarlySampleCoreSupport.F14GetEarlyInitTableHook ((const VOID **)Table, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14OnLogicalIdAndRev (
+ OUT CONST CPU_LOGICAL_ID_XLAT **OnIdPtr,
+ OUT UINT8 *NumberOfElements,
+ OUT UINT64 *LogicalFamily,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
{
0x5010,
AMD_F14_ON_B0
+ },
+ {
+ 0x5020,
+ AMD_F14_ON_C0
}
};
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14OnMicroCodePatchesStruct (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **OnUcodePtr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
--- /dev/null
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Ontario PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU/FAMILY/0x14/ON
+ * @e \$Revision: 46389 $ @e \$Date: 2011-01-31 22:22:49 -0500 (Mon, 31 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+// P C I T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14OnPciRegisters[] =
+{
+// Function 4
+
+// D18F4x104 - TDP Lock Accumulator
+// bits[1:0] TdpLockDivVal = 1
+// bits[13:2] TdpLockDivRate = 0x190
+// bits[16:15] TdpLockDivValCpu = 1
+// bits[28:17] TdpLockDivRateCpu = 0x190
+ {
+ PciRegister,
+ {
+ AMD_FAMILY_14, // CpuFamily
+ AMD_F14_ON_Cx // CpuRevision
+ },
+ {AMD_PF_ALL}, // platformFeatures
+ {{
+ MAKE_SBDFO (0, 0, 24, FUNC_4, 0x104), // Address
+ 0x03208641, // regData
+ 0x1FFFBFFF, // regMask
+ }}
+ },
+};
+
+CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable = {
+ PrimaryCores,
+ (sizeof (F14OnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+ F14OnPciRegisters,
+};
*----------------------------------------------------------------------------------------
*/
UINT32
+F14GetApCoreNumber (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+CORE_ID_POSITION
+F14CpuAmdCoreIdPositionInInitialApicId (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
STATIC
RoundedDivision (
IN UINT32 Dividend,
UINT32 TargetNumerator;
UINT32 TargetDenominator;
BOOLEAN ReturnStatus;
+ BOOLEAN WaitForTransition;
PCI_ADDR PciAddress;
D18F3xD4_STRUCT Cptc0;
D18F3xDC_STRUCT Cptc2;
// F14 only supports NB P0 and NB P1
ASSERT (TargetNbPstate < 2);
+ WaitForTransition = FALSE;
ReturnStatus = TRUE;
// Get D18F3xD4[MainPllOpFreqId] frequency
// Apply the appropriate P0 frequency
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
+ if (Cptc2.Field.NbPs0NclkDiv != EncodedNbPs0NclkDiv) {
+ WaitForTransition = TRUE;
Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv;
LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
+ }
NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv);
// Determine NB P1 settings if necessary
NbP1Cof = 0;
}
*CurrentNbFreq = NbP0Cof;
+ if (WaitForTransition) {
+ // Ensure that the frequency has settled before returning to memory code.
+ PciAddress.AddressValue = CPTC2_PCI_ADDR;
+ do {
+ LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
+ } while (Cptc2.Field.NclkFreqDone != 1);
+ }
} else {
// Get NB P0 COF
PciAddress.AddressValue = CPTC2_PCI_ADDR;
NbPsCfgLow.Field.NbPsForceSel = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
- // Wait for the transition to complete.
- PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
- do {
- LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
- } while (NbPsCtrlSts.Field.NbPs1Act != 1);
-
+ WaitForTransition = TRUE;
*CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv);
} else {
// No NB P-states. Return FALSE, and set current frequency to P0.
// Request transition to P0
NbPsCfgLow.Field.NbPsForceSel = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
+ WaitForTransition = TRUE;
}
}
- }
-
+ if (WaitForTransition) {
// Ensure that the frequency has settled before returning to memory code.
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
+ PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
do {
- LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
- } while (Cptc2.Field.NclkFreqDone != 1);
+ LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
+ } while (NbPsCtrlSts.Field.NbPs1Act != TargetNbPstate);
+ }
+ }
return ReturnStatus;
}
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14BrandIdString1 (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **BrandString1Ptr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetF14BrandIdString2 (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **BrandString2Ptr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
- * @e \$Revision: 40034 $ @e \$Date: 2010-10-19 04:03:22 +0800 (Tue, 19 Oct 2010) $
+ * @e \$Revision: 45203 $ @e \$Date: 2011-01-13 12:36:39 -0700 (Thu, 13 Jan 2011) $
*
*/
/*
CONST CHAR8 ROMDATA str_AMD_C[] = "AMD C-";
CONST CHAR8 ROMDATA str_AMD_E[] = "AMD E-";
CONST CHAR8 ROMDATA str_AMD_G_T[] = "AMD G-T";
+CONST CHAR8 ROMDATA str_AMD_Z[] = "AMD Z-";
// String2
CONST CHAR8 ROMDATA str___Processor[] = " Processor";
CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
CONST CHAR8 ROMDATA str_N_Processor[] = "N Processor";
CONST CHAR8 ROMDATA str_R_Processor[] = "R Processor";
+CONST CHAR8 ROMDATA str_E_Processor[] = "E Processor";
+CONST CHAR8 ROMDATA str_0D_APU[] = "0D APU with Radeon(tm) HD Graphics";
+CONST CHAR8 ROMDATA str_0_APU[] = "0 APU with Radeon(tm) HD Graphics";
+CONST CHAR8 ROMDATA str_5_APU[] = "5 APU with Radeon(tm) HD Graphics";
+CONST CHAR8 ROMDATA str_APU[] = " APU with Radeon(tm) HD Graphics";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
{2, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
{1, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
{2, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
+ {2, 0, 3, ON_SOCKET_FT1, str_AMD_Z, sizeof (str_AMD_Z)},
{1, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)},
{2, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)}
}; //Cores, page, index, socket, stringstart, stringlength
{1, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
{2, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
{1, 0, 0x09, ON_SOCKET_FT1, str_R_Processor, sizeof (str_R_Processor)},
+ {2, 0, 0x09, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
+ {1, 0, 0x0A, ON_SOCKET_FT1, str_0_APU, sizeof (str_0_APU)},
+ {2, 0, 0x0A, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
+ {1, 0, 0x0B, ON_SOCKET_FT1, str_5_APU, sizeof (str_5_APU)},
+ {2, 0, 0x0B, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
+ {1, 0, 0x0C, ON_SOCKET_FT1, str_APU, sizeof (str_APU)},
+ {2, 0, 0x0C, ON_SOCKET_FT1, str_E_Processor, sizeof (str_E_Processor)},
+ {1, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
+ {2, 0, 0x0D, ON_SOCKET_FT1, str_0D_APU, sizeof (str_0D_APU)},
{1, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
{2, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
}; //Cores, page, index, socket, stringstart, stringlength
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14CacheInfo (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **CacheInfoPtr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
+VOID
+DmiF14GetInfo (
+ IN OUT CPU_TYPE_INFO *CpuInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT8
+DmiF14GetVoltage (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT16
+DmiF14GetMaxSpeed (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT16
+DmiF14GetExtClock (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+DmiF14GetMemInfo (
+ IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
{
UINT8 MaxVid;
UINT8 Voltage;
+ UINT8 NumberBoostStates;
UINT64 MsrData;
+ PCI_ADDR TempAddr;
+ CPU_LOGICAL_ID CpuFamilyRevision;
+ CPB_CTRL_REGISTER CpbCtrl;
// Voltage = 0x80 + (voltage at boot time * 10)
- LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
- MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
- if (MaxVid == 0) {
- LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
- MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+ TempAddr.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, TempAddr, &CpbCtrl, StdHeader); // F4x15C
+ NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+ } else {
+ NumberBoostStates = 0;
}
+ LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader);
+ MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+
if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
Voltage = 0;
} else {
IN AMD_CONFIG_PARAMS *StdHeader
)
{
+ UINT8 NumBoostStates;
UINT32 P0Frequency;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
+ CPU_LOGICAL_ID CpuFamilyRevision;
FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
- FamilyServices->GetPstateFrequency (FamilyServices, (UINT8) 0x00, &P0Frequency, StdHeader);
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_4, 0x15C);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+ NumBoostStates = (UINT8) ((PciData >> 2) & 7);
+ } else {
+ NumBoostStates = 0;
+ }
+
+ FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
return ((UINT16) P0Frequency);
}
* Processor Family Table
*
* Note: 'x' means we don't care this field
+ * 046h = "AMD C-Series Processor"
+ * 047h = "AMD E-Series Processor"
+ * 048h = "AMD S-Series Processor"
+ * 049h = "AMD G-Series Processor"
* 002h = "Unknown"
*-------------------------------------------------------------------------------------*/
CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
// PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
{0, 0, 'x', 1, 0x46},
{0, 0, 'x', 2, 0x47},
+ {0, 0, 'x', 4, 0x49},
{'x', 'x', 'x', 'x', 0x02}
};
--- /dev/null
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Optimizations for lower power consumption
+ *
+ * Sets some registers for tablet parts at AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU/Family/F14
+ * @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF14PowerMgmt.h"
+#include "cpuF14LowPowerInit.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 14h model 0 - 0xF core 0 entry point for programming registers for lower
+ * power consumption.
+ *
+ * Set up D18F6x94[CpuPstateThrEn, CpuPstateThr], and D18F4x134[IntRateCC6DecrRate
+ * according to the BKDG.
+ *
+ * @param[in] FamilySpecificServices The current Family Specific Services.
+ * @param[in] CpuEarlyParams Service parameters
+ * @param[in] StdHeader Config handle for library and services.
+ *
+ */
+VOID
+F14OptimizeForLowPowerInit (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 NumBoostStates;
+ UINT32 LocalPciRegister;
+ BOOLEAN OptimizeForLowPower;
+ BOOLEAN IsRevC;
+ PCI_ADDR PciAddress;
+ CPU_LOGICAL_ID CpuFamilyRevision;
+
+ PciAddress.AddressValue = PRODUCT_INFO_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+ if ((((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->LowPowerDefault == 1) &&
+ (CpuEarlyParams->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife)) {
+ OptimizeForLowPower = TRUE;
+ } else {
+ OptimizeForLowPower = FALSE;
+ }
+
+ // Get F4x15C [4:2] NumBoostStates
+ // Get IsRevC
+ NumBoostStates = 0;
+ IsRevC = FALSE;
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
+ IsRevC = TRUE;
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+ NumBoostStates = (UINT8) ((CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates;
+ }
+
+ // F6x94[2:0] CpuPstateThr
+ PciAddress.AddressValue = NB_PSTATE_CFG_HIGH_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+ if (OptimizeForLowPower) {
+ ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 0;
+ } else {
+ if (NumBoostStates == 0) {
+ ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 1;
+ } else {
+ ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThr = 2;
+ }
+ }
+ // F6x94[3] CpuPstateThrEn = 1
+ ((NB_PSTATE_CFG_HIGH_REGISTER *) &LocalPciRegister)->CpuPstateThrEn = 1;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+ // F4x134[31:27] IntRateCC6DecrRate
+ PciAddress.AddressValue = CSTATE_MON_CTRL3_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+ ((CSTATE_MON_CTRL3_REGISTER *) &LocalPciRegister)->IntRateCC6DecrRate = (OptimizeForLowPower || IsRevC) ? 0x18 : 0x8;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+}
--- /dev/null
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_14 Optimizations for Low Power
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU/Family/F14
+ * @e \$Revision: 45578 $ @e \$Date: 2011-01-18 19:20:41 -0500 (Tue, 18 Jan 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _F14_LOW_POWER_INIT_H_
+#define _F14_LOW_POWER_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F14OptimizeForLowPowerInit (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _F14_LOW_POWER_INIT_H_
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
- * @e \$Revision: 37263 $ @e \$Date: 2010-09-01 21:58:26 +0800 (Wed, 01 Sep 2010) $
+ * @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
// M S R T a b l e s
// ----------------------
+// MC0_CTL_MASK (0xC0010044)
+// bit[6] = 1, erratum #628
+ {
+ MsrRegister,
+ {
+ AMD_FAMILY_14, // CpuFamily
+ AMD_F14_ON_ALL // CpuRevision
+ },
+ {AMD_PF_ALL}, // platformFeatures
+ {{
+ MSR_MC0_CTL_MASK, // MSR Address
+ 0x0000000000000040, // OR Mask
+ 0x0000000000000040, // NAND Mask
+ }}
+ },
// MSR_TOM2 (0xC001001D)
// bits[63:0] - TOP_MEM2 = 0
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_TOM2, // MSR Address
0x0000000000000000, // OR Mask
0xFFFFFFFFFFFFFFFF, // NAND Mask
- }
+ }}
},
// MSR_SYS_CFG (0xC0010010)
// bit[21] - MtrrTom2En = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_SYS_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
- }
+ }}
},
// MSR_CPUID_EXT_FEATS (0xC0011005)
// bit[41] - OSVW = 0
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_CPUID_EXT_FEATS, // MSR Address
0x0000000000000000, // OR Mask
0x0000020000000000, // NAND Mask
- }
+ }}
},
// MSR_OSVW_ID_Length (0xC0010140)
// bit[15:0] = 4
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_OSVW_ID_Length, // MSR Address
0x0000000000000004, // OR Mask
0x000000000000FFFF, // NAND Mask
- }
+ }}
},
// MSR_HWCR (0xC0010015)
// Do not set bit[24] = 1, it will be set in AmdInitPost.
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_MC0_CTL, // MSR Address
0xFFFFFFFFFFFFFFFF, // OR Mask
0xFFFFFFFFFFFFFFFF, // NAND Mask
- }
+ }}
},
// MSR_LS_CFG (0xC0011020)
// bit[36] Reserved = 1, workaround for erratum #530
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_LS_CFG, // MSR Address
0x0000001002000000, // OR Mask
0x0000001002000000, // NAND Mask
- }
+ }}
},
// MSR_DC_CFG (0xC0011022)
// bit[57:56] Reserved = 2
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MSR_DC_CFG, // MSR Address
0x0200000000000000, // OR Mask
0x0300000000000000, // NAND Mask
- }
+ }}
}
};
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
0x002E0800, // regData
0x006E0800, // regMask
- }
+ }}
},
// Function 2 - DRAM Controller
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0xB8), // Address
0x00000000, // regData
0xF000F000, // regMask
- }
+ }}
},
// D18F2xBC
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0xBC), // Address
0x00000000, // regData
0xC0000000, // regMask
- }
+ }}
},
// D18F2x118 - Memory Controller Configuration Low
// bits[7:6], MctPriHiWr = 10b
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
0x00000080, // regData
0x000000C0, // regMask
- }
+ }}
},
// D18F2x11C - Memory Controller Configuration High
// bits[24:22], PrefConf = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x11C), // Address
0x00400000, // regData
0x01C00000, // regMask
- }
+ }}
},
// Function 3 - Misc. Control
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address
0x00000100, // regData
0x00000100, // regMask
- }
+ }}
},
// D18F3x44 - MCA NB Configuration
// bit[27] NbMcaToMstCpuEn = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
0x0A300040, // regData
0x0A303E40, // regMask
- }
+ }}
},
// D18F3x84 - ACPI Power State Control High
// bit[18] Smaf6DramMemClkTri = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
0x00060006, // regData
0x00060006, // regMask
- }
+ }}
},
// D18F3x8C - NB Configuration High
// bit[26] EnConvertToNonIsoc = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
0x04000000, // regData
0x04000000, // regMask
- }
+ }}
},
// D18F3xA0 - Power Control Miscellaneous
// bit[9] SviHighFreqSel = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x00000200, // regData
0x00000200, // regMask
- }
+ }}
},
// D18F3xA4 - Reported Temperature Control
// bits[12:8] PerStepTimeDn = 0xF
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
0x00000FEF, // regData
0x00001FFF, // regMask
- }
+ }}
},
// D18F3xD4 - Clock Power Timing Control 0
// bits[11:8] ClkRampHystSel = 0xF
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x00024F00, // regData
0x0002FF00, // regMask
- }
+ }}
},
// D18F3xDC - Clock Power Timing Control 2
// bits[29:27] NbClockGateHyst = 3
-// bit[30] NbClockGateEn = 1
+// bit[30] NbClockGateEn = 0 - erratum #596
// bit[31] CnbCifClockGateEn = 1
{
PciRegister,
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0xD8000000, // regData
+ 0x98000000, // regData
0xF8000000, // regMask
- }
+ }}
},
// D18F3x180 - Extended NB MCA Configuration
// bit[2] WDTCntSel[3] = 0
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
0x00200020, // regData
0x00200024, // regMask
- }
+ }}
},
// D18F3x188 - NB Extended Configuration
// bit[21] EnCpuSerWrBehindIoRd = 0
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x1B000000, // regData
0xFFA00000, // regMask
- }
+ }}
},
// Function 4 - Extended Misc. Control
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
0x00000000, // regData
0x00000707, // regMask
- }
+ }}
},
// D18F4x124 - C-state Monitor Control 1
// bit[15] TimerTickIntvlScale = 1
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
0x05138000, // regData
0x07FF8000, // regMask
- }
+ }}
},
// D18F4x134 - C-state Monitor Control 3
// bits[3:0] IntRatePkgC6MaxDepth = 0
// bits[19:16] IntRateCC6MaxDepth = 5
// bits[23:20] IntRateCC6Threshold = 4
// bits[26:24] IntRateCC6BurstLen = 5
-// bits[31:27] IntRateCC6DecrRate = 0x08
{
PciRegister,
{
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address
- 0x45455100, // regData
- 0xFFFFFFFF, // regMask
- }
+ 0x05455100, // regData
+ 0x07FFFFFF, // regMask
+ }}
},
// D18F4x13C - SMAF Code DID 1
// bits[4:0] Smaf4Did = 0x0F
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address
0x000F000F, // regData
0x001F001F, // regMask
- }
+ }}
},
// D18F4x1A4 - C-state Monitor Mask
// bits[7:0] IntRateMonMask = 0xFC
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address
0xFFFFFFFC, // regData
0xFFFFFFFF, // regMask
- }
+ }}
},
// D18F4x1A8 - CPU State Power Management Dynamic Control 0
// bits[4:0] SingleHaltCpuDid = 0x1E
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address
0x009003FE, // regData
0x00F083FF, // regMask
- }
+ }}
},
// D18F4x1AC - CPU State Power Management Dynamic Control 1
// bits[9:5] C6Did = 0x1F
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address
0x300003E0, // regData
0x300003E0, // regMask
- }
+ }}
},
// D18F6x50 - Configuration Register Access Control
// bit[1] CfgAccAddrMode = 0
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address
0x00000000, // regData
0x00000002, // regMask
- }
+ }}
},
// D18F6x54 - DRAM Arbitration Control FEQ Collision
// bits[7:0] FeqLoPrio = 0x20
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address
0x00081020, // regData
0x80FFFFFF, // regMask
- }
+ }}
},
// D18F6x58 - DRAM Arbitration Control Display Collision
// bits[7:0] DispLoPrio = 0x40
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address
0x00102040, // regData
0xFFFFFFFF, // regMask
- }
+ }}
},
// D18F6x5C - DRAM Arbitration Control FEQ Write Protect
// bits[7:0] FeqLoPrio = 0x20
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address
0x00081020, // regData
0x80FFFFFF, // regMask
- }
+ }}
},
// D18F6x60 - DRAM Arbitration Control Display Write Protect
// bits[7:0] DispLoPri = 0x20
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address
0x00081020, // regData
0xFFFFFFFF, // regMask
- }
+ }}
},
// D18F6x64 - DRAM Arbitration Control FEQ Read Protect
// bits[7:0] FeqLoPrio = 0x10
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address
0x00040810, // regData
0x80FFFFFF, // regMask
- }
+ }}
},
// D18F6x68 - DRAM Arbitration Control Display Read Protect
// bits[7:0] DispLoPrio = 0x10
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address
0x00040810, // regData
0xFFFFFFFF, // regMask
- }
+ }}
},
// D18F6x6C - DRAM Arbitration Control FEQ Fairness Timer
// bits[7:0] FeqLoPrio = 0x80
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address
0x00204080, // regData
0x00FFFFFF, // regMask
- }
+ }}
},
// D18F6x70 - DRAM Arbitration Control Display Fairness Timer
// bits[7:0] DispLoPrio = 0x80
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address
0x00204080, // regData
0xFFFFFFFF, // regMask
- }
+ }}
},
// D18F6x74 - Dram Idle Page Close Limit
// bits[40] IdleLimit = 0x1E
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x74), // Address
0x0000001E, // regData
0x0000001F, // regMask
- }
+ }}
},
// D18F6x78 - Dram Prioritization and Arbitration Control
// bits[1:0] DispDbePrioEn = 3
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address
0x00000037, // regData
0x0000007F, // regMask
- }
+ }}
},
// D18F6x90 - NB P-state Config Low
// As part of BIOS Requirements for NB P-state Initialization
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address
0x50000000, // regData
0x70000000, // regMask
- }
+ }}
},
// D18F6x94 - NB P-state Config High
-// bits[2:0] CpuPstateThr = 1
-// bit[3] CpuPstateThrEn = 1
// bits[25:23] NbPsC0Timer = 4
{
PciRegister,
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address
- 0x02000009, // regData
- 0x0380000F, // regMask
- }
+ 0x02000000, // regData
+ 0x03800000, // regMask
+ }}
},
// D18F6x9C - NCLK Reduction Control
// bits[6:0] NclkRedDiv = 0x60
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address
0x000001E0, // regData
0x000001FF, // regMask
- }
+ }}
}
};
AMD_FAMILY_14, // CpuFamily
AMD_F14_ALL // CpuRevision
},
- AMD_PF_ALL, // platformFeatures
- {
+ {AMD_PF_ALL}, // platformFeatures
+ {{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
0x00000100, // regData
0x0000010F, // regMask
- }
+ }}
}
};
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
- * @e \$Revision: 39744 $ @e \$Date: 2010-10-15 02:18:02 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 46951 $ @e \$Date: 2011-02-11 12:37:59 -0700 (Fri, 11 Feb 2011) $
*
*/
/*
*/
#include "AGESA.h"
#include "amdlib.h"
-#include "cpuCacheInit.h"
#include "cpuF14PowerMgmt.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerCheck.h"
-#include "cpuF14Utilities.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE
/*---------------------------------------------------------------------------------------*/
/**
- * Family 14h core 0 entry point for performing the family 14h Processor-
+ * Family 14h Ontario core 0 entry point for performing the family 14h Ontario Processor-
* Systemboard Power Delivery Check.
*
* The steps are as follows:
- * 1. Starting with P0, loop through all P-states until a passing state is
+ * 1. Starting with hardware P0, loop through all P-states until a passing state is
* found. A passing state is one in which the current required by the
* CPU is less than the maximum amount of current that the system can
* provide to the CPU. If P0 is under the limit, no further action is
* necessary.
* 2. If at least one P-State is under the limit & at least one P-State is
* over the limit, the BIOS must:
- * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
+ * a. Program D18F4x15C[BoostSrc]=0.
* b. If the processor's current P-State is disabled by the power check,
* then the BIOS must request a transition to an enabled P-state
* using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
* 1. D18F3x64[HtcPstateLimit]
* 2. D18F3xDC[PstateMaxVal]
* 3. If all P-States are over the limit, the BIOS must:
- * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
+ * a. Program D18F4x15C[BoostSrc]=0.
* b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then
* write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
* MSRC001_0063[CurPstate] to reflect the new value.
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT8 DisPsNum;
+ UINT8 DisHwPsNum;
+ UINT8 DisSwPsNum;
UINT8 PsMaxVal;
UINT8 Pstate;
+ UINT8 PstateLimit;
+ UINT8 NumberBoostStates;
UINT32 ProcIddMax;
- UINT32 PciRegister;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
- UINT32 PstateLimit;
PCI_ADDR PciAddress;
- UINT64 MsrRegister;
+ UINT64 LocalMsrRegister;
+ BOOLEAN ThermalPstateEn;
+ NB_CAPS_REGISTER NbCaps;
+ HTC_REGISTER HtcReg;
+ CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2;
+ CPB_CTRL_REGISTER CpbCtrl;
+ CPU_LOGICAL_ID CpuFamilyRevision;
AP_TASK TaskPtr;
AGESA_STATUS IgnoredSts;
PWRCHK_ERROR_DATA ErrorData;
ASSERT (Core == 0);
+ // save ThermalPstateEn
+ // TRUE if the P-state indicated by D18F3x64[HtcPstateLimit] is enabled;
+ // FALSE otherwise.
+ PciAddress.AddressValue = HTC_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
+ LibAmdMsrRead (PS_REG_BASE + HtcReg.HtcPstateLimit, &LocalMsrRegister, StdHeader);
+ if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+ ThermalPstateEn = TRUE;
+ } else {
+ ThermalPstateEn = FALSE;
+ }
+
// get the Max P-state value
for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
- LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader);
+ if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
break;
}
}
ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
- DisPsNum = 0;
+ // get NumberBoostStates
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
+ NumberBoostStates = 0;
+ } else {
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
+ NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+ }
+
+ // update PstateMaxVal if warranted by HtcPstateLimit
+ PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+ if (NbCaps.HtcCapable == 1) {
+ if (HtcReg.HtcTmpLmt != 0) {
+ PciAddress.AddressValue = CPTC2_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+ if (HtcReg.HtcPstateLimit > ClkPwrTimingCtrl2.PstateMaxVal) {
+ ClkPwrTimingCtrl2.PstateMaxVal = HtcReg.HtcPstateLimit;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+ }
+ }
+ }
+
+ DisHwPsNum = 0;
for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
PutEventLog (AGESA_WARNING,
CPU_EVENT_PM_PSTATE_OVERCURRENT,
Socket, Pstate, 0, 0, StdHeader);
- DisPsNum++;
+ DisHwPsNum++;
} else {
break;
}
}
}
+ // get the number of software Pstate that is disabled by delivery check
+ if (NumberBoostStates < DisHwPsNum) {
+ DisSwPsNum = DisHwPsNum - NumberBoostStates;
+ } else {
+ DisSwPsNum = 0;
+ }
// If all P-state registers are disabled, move P[PsMaxVal] to P0
// and transition to P0, then wait for CurPstate = 0
- ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+ ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisHwPsNum);
// We only need to log this event on the BSC
if (ErrorData.AllowablePstateNumber == 0) {
Socket, 0, 0, 0, StdHeader);
}
- if (DisPsNum != 0) {
+ if (DisHwPsNum != 0) {
+ // Program F4x15C[BoostSrc] = 0
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
+ CpbCtrl.BoostSrc = 0;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
+ }
+
TaskPtr.FuncAddress.PfApTaskI = F14PmPwrCheckCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
TaskPtr.DataTransfer.DataPtr = &ErrorData;
// Final Step
// D18F3x64[HtPstatelimit] -= disPsNum
// D18F3xDC[PstateMaxVal]-= disPsNum
-
PciAddress.AddressValue = HTC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
- PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
+ LibAmdPciRead (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
+ PciAddress.AddressValue = NB_CAPS_PCI_ADDR; // D18F3xE8
+ LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+ if (ThermalPstateEn || HtcReg.HtcTmpLmt == 0 || NbCaps.HtcCapable == 0) {
+ PstateLimit = (UINT8) HtcReg.HtcPstateLimit;
+ if (PstateLimit > DisHwPsNum) {
+ PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
} else {
- PstateLimit = 0;
+ PstateLimit = NumberBoostStates;
}
- ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit = PstateLimit;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
+ HtcReg.HtcPstateLimit = PstateLimit;
+ PciAddress.AddressValue = HTC_PCI_ADDR;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &HtcReg, StdHeader); // D18F3x64
PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
- PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
+ LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
+ PstateLimit = (UINT8) ClkPwrTimingCtrl2.PstateMaxVal;
+ if (PstateLimit > DisHwPsNum) {
+ PstateLimit = (UINT8) (PstateLimit - DisSwPsNum);
} else {
- PstateLimit = 0;
+ PstateLimit = NumberBoostStates;
+ }
+ ClkPwrTimingCtrl2.PstateMaxVal = PstateLimit;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); // D18F3xDC
}
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PstateLimit;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
}
}
)
{
UINT8 i;
- UINT8 PsMaxVal;
- UINT8 DisPsNum;
- UINT8 CurrentPs;
- UINT64 MsrRegister;
+ UINT8 HardwarePsMaxVal;
+ UINT8 DisHwPsNum;
+ UINT8 DisSwPsNum;
+ UINT8 CurrentSoftwarePs;
+ UINT8 CurrentHardwarePs;
+ UINT8 NumberBoostStates;
+ UINT64 LocalMsrRegister;
+ CPU_LOGICAL_ID CpuFamilyRevision;
+ PCI_ADDR PciAddress;
+ CPB_CTRL_REGISTER CpbCtrl;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
- DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+ HardwarePsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+ DisHwPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
+ LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader);
+ CurrentSoftwarePs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate);
+
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) != 0) {
+ NumberBoostStates = 0;
+ } else {
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &CpbCtrl, StdHeader); // D18F4x15C
+ NumberBoostStates = (UINT8) CpbCtrl.NumBoostStates;
+ }
+
+ CurrentHardwarePs = CurrentSoftwarePs + NumberBoostStates;
+
+ if (NumberBoostStates < DisHwPsNum) {
+ DisSwPsNum = DisHwPsNum - NumberBoostStates;
+ } else {
+ DisSwPsNum = 0;
+ }
if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
// Step 1
// Transition to Pstate Max if not there already
- if (CurrentPs != PsMaxVal) {
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
+ if (CurrentHardwarePs != HardwarePsMaxVal) {
+ FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
+ CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
}
// Step 2
- // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+ // If CurrentSoftwarePs is not P0, copy CurrentSoftwarePs contents to Software P0 and switch
// to P0.
- if (PsMaxVal != 0) {
- F14PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
+ if (CurrentSoftwarePs != 0) {
+ F14PmPwrChkCopyPstate (NumberBoostStates, CurrentSoftwarePs, StdHeader);
+ LibAmdMsrRead ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
+ ((PSTATE_MSR *) &LocalMsrRegister)->PsEnable = 1;
+ LibAmdMsrWrite ((PS_REG_BASE + NumberBoostStates), &LocalMsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
}
} else {
// Step 1
// Transition to a valid Pstate if current Pstate has been disabled
- if (CurrentPs < DisPsNum) {
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
- CurrentPs = DisPsNum;
+ if (CurrentHardwarePs < DisHwPsNum) {
+ FamilySpecificServices->TransitionPstate (FamilySpecificServices, (HardwarePsMaxVal - NumberBoostStates), (BOOLEAN) TRUE, StdHeader);
+ CurrentSoftwarePs = HardwarePsMaxVal - NumberBoostStates;
}
+ if (DisSwPsNum != 0) {
// Step 2
// Move enabled Pstates up and disable the remainder
- for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
- F14PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
+ for (i = 0; (i + DisHwPsNum) <= HardwarePsMaxVal; ++i) {
+ F14PmPwrChkCopyPstate ((i + NumberBoostStates), (i + DisHwPsNum), StdHeader);
}
-
// Step 3
// Transition to current COF/VID at shifted location
- CurrentPs = (CurrentPs - DisPsNum);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
+ CurrentSoftwarePs = (CurrentSoftwarePs - DisSwPsNum);
+ FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSoftwarePs, (BOOLEAN) TRUE, StdHeader);
+ }
+ }
+
+ if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+ // only software P0 should be enabled.
+ i = NumberBoostStates + 1;
+ } else {
+ if (DisSwPsNum == 0) {
+ // No software Pstate is disabed, set i = HardwarePsMaxVal + 1 to skip below 'while loop'.
+ i = HardwarePsMaxVal + 1;
+ } else {
+ // get the first software Pstate that should be disabled.
+ i = HardwarePsMaxVal - DisSwPsNum + 1;
}
- i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
- if (i == 0) {
- i++;
}
- while (i <= PsMaxVal) {
+ while (i <= HardwarePsMaxVal) {
FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
i++;
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 LocalMsrRegister;
- LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
- LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
+ LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader);
+ LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader);
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
*
*/
/*
} PSTATE_MSR;
+/* COFVID Control Register 0xC0010070 */
+#define MSR_COFVID_CTL 0xC0010070
+
+/// COFVID Control MSR Register
+typedef struct {
+ UINT64 CpuDid:4; ///< CPU core divisor identifier
+ UINT64 CpuDidMSD:5; ///< CPU core frequency identifier
+ UINT64 CpuVid:7; ///< CPU core VID
+ UINT64 PstateId:3; ///< P-state identifier
+ UINT64 IgnoreFidVidDid:1; ///< Ignore FID, VID, and DID
+ UINT64 :44; ///< Reserved
+} COFVID_CTRL_MSR;
+
+
/* COFVID Status Register 0xC0010071 */
#define MSR_COFVID_STS 0xC0010071
UINT32 :16; ///< Reserved
} CLK_PWR_TIMING_CTRL3_REGISTER;
+/* Local hardware thermal control register D18F3x138 */
+#define LHTC_REG 0x138
+#define LHTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, LHTC_REG))
+
+/// Local Hardware Thermal Control PCI Register
+typedef struct {
+ UINT32 LHtcEn:1; ///< Local HTC Enable
+ UINT32 :7; ///< Reserved
+ UINT32 LHtcAct:2; ///< Local HTC Active State
+ UINT32 :2; ///< Reserved
+ UINT32 LHtcActSts:2; ///< Local HTC Active Status
+ UINT32 :2; ///< Reserved
+ UINT32 LHtcTmpLmt:7; ///< Local HTC temperature limit
+ UINT32 LHtcSlewSel:1; ///< Local HTC slew-controlled temp select
+ UINT32 LHtcHystLmt:4; ///< Local HTC hysteresis
+ UINT32 LHtcPstateLimit:3; ///< Local HTC P-state limit select
+ UINT32 LHtcLock:1; ///< HTC lock
+} LHTC_REGISTER;
+
+/* Product Information Register D18F3x1FC */
+#define PRODUCT_INFO_REG 0x1FC
+#define PRODUCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRODUCT_INFO_REG))
+
+/// Product Information PCI Register
+typedef struct {
+ UINT32 :2; ///< Reserved
+ UINT32 LowPowerDefault:1; ///< Low Power Default
+ UINT32 :29; ///< Reserved
+} PRODUCT_INFO_REGISTER;
+
/* C-state Control 1 Register D18F4x118 */
#define CSTATE_CTRL1_REG 0x118
} CSTATE_CTRL2_REGISTER;
+/* C-state Monitor Control 3 Register D18F4x134 */
+#define CSTATE_MON_CTRL3_REG 0x134
+#define CSTATE_MON_CTRL3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_MON_CTRL3_REG))
+
+/// C-state Monitor Control 3 Register
+typedef struct {
+ UINT32 IntRatePkgC6MaxDepth:4; ///< Interrupt rate monitor PC6 maximum counter depth
+ UINT32 IntRatePkgC6Threshold:4; ///< Interrupt rate monitor PC6 threshold
+ UINT32 IntRatePkgC6BurstLen:3; ///< Interrupt rate monitor PC6 burst length
+ UINT32 IntRatePkgC6DecrRate:5; ///< Interrupt rate monitor PC6 decrement rate
+ UINT32 IntRateCC6MaxDepth:4; ///< Interrupt rate monitor CC6 maximum counter depth
+ UINT32 IntRateCC6Threshold:4; ///< Interrupt rate monitor CC6 threshold
+ UINT32 IntRateCC6BurstLen:3; ///< Interrupt rate monitor CC6 burst length
+ UINT32 IntRateCC6DecrRate:5; ///< Interrupt rate monitor CC6 decrement rate
+} CSTATE_MON_CTRL3_REGISTER;
+
+/* LPMV Scalar 2 Register D18F4x14C */
+#define LPMV_SCALAR2_REG 0x14C
+#define LPMV_SCALAR2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, LPMV_SCALAR2_REG))
+
+/// LPMV Scalar 2 Register
+typedef struct {
+ UINT32 :24; ///< Reserved
+ UINT32 ApmCstExtPol:2; ///< Number of boosted states
+ UINT32 :6; ///< Reserved
+} LPMV_SCALAR2_REGISTER;
+
/* Core Performance Boost Control Register D18F4x15C */
#define CPB_CTRL_REG 0x15C
#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
- * @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
+ * @e \$Revision: 45626 $ @e \$Date: 2011-01-19 09:58:02 -0700 (Wed, 19 Jan 2011) $
*
*/
/*
#include "cpuF14SoftwareThermal.h"
#include "cpuF14PowerPlane.h"
#include "cpuF14PowerCheck.h"
+#include "cpuF14LowPowerInit.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14SysPmTable (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **SysPmTblPtr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
F14PmPwrPlaneInit // Function Pointer
},
+ // Step x - Optimizations for lower power
+ // Execute both cold & warm
+ {
+ 0, // ExeFlags
+ F14OptimizeForLowPowerInit // Function Pointer
+ },
+
// Step 2 - Current Delivery Check
// Execute both cold & warm
{
{
0, // ExeFlags
F14PmThermalInit // Function Pointer
- },
+ }
};
#include "cpuFamilyTranslation.h"
#include "cpuServices.h"
#include "cpuF14PowerMgmt.h"
+#include "cpuF14PowerPlane.h"
#include "OptionFamily14hEarlySample.h"
#include "NbSmuLib.h"
#include "GnbRegistersON.h"
)
{
UINT32 SystemSlewRate;
- UINT32 PciRegister;
+ UINT32 PciReg;
UINT32 WaitTime;
UINT32 VSRampSlamTime;
PCI_ADDR PciAddress;
// Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
PciAddress.AddressValue = CPTC1_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampSlamTime = VSRampSlamTime;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+ ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciReg)->VSRampSlamTime = VSRampSlamTime;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
// Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+ ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
+ ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
UINT32 PstateCurrent;
UINT32 NextPstateCurrent;
UINT32 NextPstateCurrentRaw;
- UINT32 PciRegister;
+ UINT32 PciReg;
UINT32 PreviousVid;
UINT32 CurrentVid;
UINT64 PstateMsr;
}
}
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (IsPsiEnabled) {
- ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVid = CurrentVid;
- ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 1;
+ ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVid = CurrentVid;
+ ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 1;
} else {
- ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 0;
+ ((POWER_CTRL_MISC_REGISTER *) &PciReg)->PsiVidEn = 0;
}
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
// Set up NBPSI_L for VDDNB
PciAddress.AddressValue = CPTC3_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
- ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVid = 0;
- ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 1;
+ ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVid = 0;
+ ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 1;
} else {
- ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 0;
+ ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciReg)->NbPsiVidEn = 0;
}
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
- * @e \$Revision: 37010 $ @e \$Date: 2010-08-28 03:10:12 +0800 (Sat, 28 Aug 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+F14GetPstateTransLatency (
+ IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+ IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
+ IN PCI_ADDR *PciAddress,
+ OUT UINT32 *TransitionLatency,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+F14GetPstateFrequency (
+ IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+ IN UINT8 StateNumber,
+ OUT UINT32 *FrequencyInMHz,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+F14GetPstatePower (
+ IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+ IN UINT8 StateNumber,
+ OUT UINT32 *PowerInMw,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+F14GetPstateMaxState (
+ IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+ OUT UINT32 *MaxPStateNumber,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+F14GetPstateRegisterInfo (
+ IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+ IN UINT32 PState,
+ OUT BOOLEAN *PStateEnabled,
+ IN OUT UINT32 *IddVal,
+ IN OUT UINT32 *IddDiv,
+ OUT UINT32 *SwPstateNumber,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
UINT32 CpuDidLSD;
UINT32 CpuDidMSD;
UINT32 CoreClkDivisor;
- UINT32 PciRegister;
- UINT64 MsrRegister;
+ UINT32 PciReg;
+ UINT64 MsrReg;
BOOLEAN FrequencyCalculated;
BOOLEAN ClockDivisorCalculated;
PCI_ADDR PciAddress;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
- CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidLSD);
- CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidMSD);
+ CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidLSD);
+ CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuDidMSD);
FrequencyCalculated = FALSE;
ClockDivisorCalculated = FALSE;
if (!FrequencyCalculated) {
// Get D18F3xD4[MainPllOpFreqId] frequency
PciAddress.AddressValue = CPTC0_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
- if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
- MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
+ if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
+ MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
} else {
MainPllFid = 0;
}
UINT32 IddDiv;
UINT32 V_x10000;
UINT32 Power;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
- IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
- IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+ CpuVid = (UINT32) (((PSTATE_MSR *) &MsrReg)->CpuVid);
+ IddValue = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddValue);
+ IddDiv = (UINT32) (((PSTATE_MSR *) &MsrReg)->IddDiv);
if (CpuVid >= 0x7C) {
V_x10000 = 0;
)
{
UINT64 MsrValue;
+ UINT32 PciReg;
+ PCI_ADDR PciAddress;
+
+ // For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // D18F4x15C
//
// Read PstateMaxVal [6:4] from MSR C001_0061
// So, we will know the max pstate state in this socket.
//
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
- *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal);
+ *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (((CPB_CTRL_REGISTER *) &PciReg)->NumBoostStates);
return (AGESA_SUCCESS);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 LocalMsrReg;
+ UINT32 LocalPciReg;
+ PCI_ADDR PciAddress;
+ CPU_LOGICAL_ID CpuFamilyRevision;
ASSERT (PState < NM_PS_REG);
// Read PSTATE MSRs
- LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &LocalMsrReg, StdHeader);
+
+ *SwPstateNumber = PState;
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+ if (((PSTATE_MSR *) &LocalMsrReg)->PsEnable == 1) {
// PState enable = bit 63
*PStateEnabled = TRUE;
+ // For F14 CPU, skip boosted p-state. The boosted p-state number = D18F4x15C[NumBoostStates].
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & (AMD_F14_ON_Ax | AMD_F14_ON_Bx)) == 0) {
+ // ON_Ax & ON_Bx don't have boosted p-state function
+ PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciReg, StdHeader); // D18F4x15C
+ //
+ // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
+ //
+ if (PState < ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates) {
+ *PStateEnabled = FALSE;
+ } else {
+ *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &LocalPciReg)->NumBoostStates;
+ }
+ }
} else {
*PStateEnabled = FALSE;
}
- *SwPstateNumber = PState;
// Bits 39:32 (high 32 bits [7:0])
- *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
+ *IddVal = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddValue;
// Bits 41:40 (high 32 bits [9:8])
- *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
+ *IddDiv = (UINT32) ((PSTATE_MSR *) &LocalMsrReg)->IddDiv;
return (AGESA_SUCCESS);
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 46836 $ @e \$Date: 2011-02-10 12:22:59 -0700 (Thu, 10 Feb 2011) $
*
*/
/*
*/
#include "AGESA.h"
#include "amdlib.h"
-#include "cpuCacheInit.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF14PowerMgmt.h"
+#include "cpuF14SoftwareThermal.h"
#include "Filecode.h"
#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 PciRegister;
+ UINT32 NbCaps;
+ UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
+ CPU_LOGICAL_ID CpuFamilyRevision;
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
+ LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader);
+ if (((NB_CAPS_REGISTER *) &NbCaps)->HtcCapable == 1) {
PciAddress.AddressValue = HTC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((HTC_REGISTER *) &PciRegister)->HtcTmpLmt != 0) {
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+ if (((HTC_REGISTER *) &LocalPciRegister)->HtcTmpLmt != 0) {
// Enable HTC
- ((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ ((HTC_REGISTER *) &LocalPciRegister)->HtcEn = 1;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
+
+ GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+ if ((CpuFamilyRevision.Revision & AMD_F14_ON_Cx) != 0) {
+ PciAddress.AddressValue = LHTC_PCI_ADDR;
+ LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+ if (((NB_CAPS_REGISTER *) &NbCaps)->LHtcCapable == 1) {
+ if (((LHTC_REGISTER *) &LocalPciRegister)->LHtcTmpLmt != 0) {
+ // Enable local HTC
+ ((LHTC_REGISTER *) &LocalPciRegister)->LHtcEn = 1;
+ }
+ }
+ LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+ }
}
IN UINT8 EnabledCores
);
+BOOLEAN
+F14GetNbPstateInfo (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN PCI_ADDR *PciAddress,
+ IN UINT32 NbPstate,
+ OUT UINT32 *FreqNumeratorInMHz,
+ OUT UINT32 *FreqDivisor,
+ OUT UINT32 *VoltageInuV,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+F14IsNbPstateEnabled (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+F14GetProcIddMax (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN UINT8 Pstate,
+ OUT UINT32 *ProcIddMax,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT8
+F14GetNumberOfCoresForBrandstring (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
- LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ((PSTATE_MSR *) &MsrReg)->PsEnable = 0;
+ LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
return (AGESA_SUCCESS);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
- ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
- LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+ LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrReg, StdHeader);
+ ASSERT (((PSTATE_MSR *) &MsrReg)->PsEnable == 1);
+ LibAmdMsrRead (MSR_PSTATE_CTL, &MsrReg, StdHeader);
+ ((PSTATE_CTRL_MSR *) &MsrReg)->PstateCmd = (UINT64) StateNumber;
+ LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrReg, StdHeader);
if (WaitForTransition) {
do {
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
+ LibAmdMsrRead (MSR_PSTATE_STS, &MsrReg, StdHeader);
+ } while (((PSTATE_STS_MSR *) &MsrReg)->CurPstate != (UINT64) StateNumber);
}
return (AGESA_SUCCESS);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 MsrRegister;
+ UINT64 MsrReg;
PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
- LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
- if ((MsrRegister & 0x01000000) != 0) {
+ LibAmdMsrRead (0xC0010015, &MsrReg, StdHeader);
+ if ((MsrReg & 0x01000000) != 0) {
return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
} else {
return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 PciRegister;
+ UINT32 PciReg;
UINT32 MainPllFid;
PCI_ADDR PciAddress;
PciAddress.AddressValue = CPTC0_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
- if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
- MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
+ if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqIdEn == 1) {
+ MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciReg)->MainPllOpFreqId;
} else {
MainPllFid = 0;
}
)
{
UINT32 NbVid;
- UINT32 PciRegister;
+ UINT32 PciReg;
UINT32 MainPllFreq;
BOOLEAN PstateIsValid;
if (NbPstate == 0) {
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CPTC2_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0NclkDiv;
- NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid;
+ LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
+ *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0NclkDiv;
+ NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciReg)->NbPs0Vid;
} else {
PciAddress->Address.Function = FUNC_6;
PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1NclkDiv;
- NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1Vid;
+ LibAmdPciRead (AccessWidth32, *PciAddress, &PciReg, StdHeader);
+ *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1NclkDiv;
+ NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPs1Vid;
}
*VoltageInuV = (1550000 - (12500 * NbVid));
PstateIsValid = TRUE;
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT32 PciRegister;
+ UINT32 PciReg;
PCI_ADDR PciAddress;
PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPsCap == 1));
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+ return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciReg)->NbPsCap == 1));
}
/*---------------------------------------------------------------------------------------*/
)
{
UINT32 NodeRelativeCoreNum;
- UINT32 PciRegister;
+ UINT32 PciReg;
PCI_ADDR PciAddress;
BOOLEAN LaunchFlag;
switch (NodeRelativeCoreNum) {
case 1:
PciAddress.Address.Register = HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
- PciRegister |= HT_TRANS_CTRL_CPU1_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader);
+ if ((PciReg & HT_TRANS_CTRL_CPU1_EN) == 0) {
+ PciReg |= HT_TRANS_CTRL_CPU1_EN;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &PciReg, StdHeader);
LaunchFlag = TRUE;
} else {
LaunchFlag = FALSE;
{
UINT32 IddDiv;
UINT32 CmpCap;
- UINT32 PciRegister;
+ UINT32 PciReg;
UINT32 MsrAddress;
UINT64 PstateMsr;
BOOLEAN IsPstateEnabled;
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCap);
+ LibAmdPciRead (AccessWidth32, PciAddress, &PciReg, StdHeader); // F3xE8
+ CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciReg)->CmpCap);
CmpCap++;
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
*----------------------------------------------------------------------------------------
*/
+VOID
+GetF14WheaInitData (
+ IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+ OUT CONST VOID **F14WheaInitDataPtr,
+ OUT UINT8 *NumberOfElements,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
// CPU_LOGICAL_ID.Family equates
// Family 10h equates
-#define AMD_FAMILY_10_RB 0x0000000000000001
-#define AMD_FAMILY_10_BL 0x0000000000000002
-#define AMD_FAMILY_10_DA 0x0000000000000004
-#define AMD_FAMILY_10_HY 0x0000000000000008
-#define AMD_FAMILY_10_PH 0x0000000000000010
+#define AMD_FAMILY_10_RB 0x0000000000000001ull
+#define AMD_FAMILY_10_BL 0x0000000000000002ull
+#define AMD_FAMILY_10_DA 0x0000000000000004ull
+#define AMD_FAMILY_10_HY 0x0000000000000008ull
+#define AMD_FAMILY_10_PH 0x0000000000000010ull
#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)
#define AMD_FAMILY_GH (AMD_FAMILY_10)
// Family 12h equates
-#define AMD_FAMILY_12_LN 0x0000000000000020
+#define AMD_FAMILY_12_LN 0x0000000000000020ull
#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
// Family 14h equates
-#define AMD_FAMILY_14_ON 0x0000000000000040
+#define AMD_FAMILY_14_ON 0x0000000000000040ull
#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
// Family 15h equates
-#define AMD_FAMILY_15_OR 0x0000000000000080
+#define AMD_FAMILY_15_OR 0x0000000000000100ull
#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
// Family 16h equates
-#define AMD_FAMILY_16 0x0000000000000100
-#define AMD_FAMILY_WF (AMD_FAMILY_16)
+#define AMD_FAMILY_16 0x0000000000000800ull
+#define AMD_FAMILY_WF (AMD_FAMILY_16)
// Family Unknown
-#define AMD_FAMILY_UNKNOWN 0x8000000000000000
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
// Family Group equates
#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16)
// Family 10h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 10h RB steppings
-#define AMD_F10_RB_C0 0x0000000000000001
-#define AMD_F10_RB_C1 0x0000000000000002
-#define AMD_F10_RB_C2 0x0000000000000004
-#define AMD_F10_RB_C3 0x0000000000000008
+#define AMD_F10_RB_C0 0x0000000000000001ull
+#define AMD_F10_RB_C1 0x0000000000000002ull
+#define AMD_F10_RB_C2 0x0000000000000004ull
+#define AMD_F10_RB_C3 0x0000000000000008ull
// Family 10h BL steppings
-#define AMD_F10_BL_C2 0x0000000000000010
-#define AMD_F10_BL_C3 0x0000000000000020
+#define AMD_F10_BL_C2 0x0000000000000010ull
+#define AMD_F10_BL_C3 0x0000000000000020ull
// Family 10h DA steppings
-#define AMD_F10_DA_C2 0x0000000000000040
-#define AMD_F10_DA_C3 0x0000000000000080
+#define AMD_F10_DA_C2 0x0000000000000040ull
+#define AMD_F10_DA_C3 0x0000000000000080ull
// Family 10h HY SCM steppings
-#define AMD_F10_HY_SCM_D0 0x0000000000000100
-#define AMD_F10_HY_SCM_D1 0x0000000000000400
+#define AMD_F10_HY_SCM_D0 0x0000000000000100ull
+#define AMD_F10_HY_SCM_D1 0x0000000000000400ull
// Family 10h HY MCM steppings
-#define AMD_F10_HY_MCM_D0 0x0000000000000200
-#define AMD_F10_HY_MCM_D1 0x0000000000000800
+#define AMD_F10_HY_MCM_D0 0x0000000000000200ull
+#define AMD_F10_HY_MCM_D1 0x0000000000000800ull
// Family 10h PH steppings
-#define AMD_F10_PH_E0 0x0000000000001000
+#define AMD_F10_PH_E0 0x0000000000001000ull
// Family 10h Unknown stepping
-#define AMD_F10_UNKNOWN 0x8000000000000000
+#define AMD_F10_UNKNOWN 0x8000000000000000ull
// Family 10h Miscellaneous equates
#define AMD_F10_C0 (AMD_F10_RB_C0)
// -------------------------------------
// Family 12h LN steppings
-#define AMD_F12_LN_A0 0x0000000000000001
-#define AMD_F12_LN_A1 0x0000000000000002
-#define AMD_F12_LN_B0 0x0000000000000004
+#define AMD_F12_LN_A0 0x0000000000000001ull
+#define AMD_F12_LN_A1 0x0000000000000002ull
+#define AMD_F12_LN_B0 0x0000000000000004ull
// Family 12h Unknown stepping
-#define AMD_F12_UNKNOWN 0x8000000000000000
+#define AMD_F12_UNKNOWN 0x8000000000000000ull
#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1)
#define AMD_F12_LN_Bx (AMD_F12_LN_B0)
-#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
+#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
// Family 14h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 14h ON steppings
-#define AMD_F14_ON_A0 0x0000000000000001
-#define AMD_F14_ON_A1 0x0000000000000002
-#define AMD_F14_ON_B0 0x0000000000000004
+#define AMD_F14_ON_A0 0x0000000000000001ull
+#define AMD_F14_ON_A1 0x0000000000000002ull
+#define AMD_F14_ON_B0 0x0000000000000004ull
+#define AMD_F14_ON_C0 0x0000000000000008ull
+ // Family 14h KR steppings
+#define AMD_F14_KR_A0 0x0000000000000100ull
+#define AMD_F14_KR_A1 0x0000000000000200ull
+#define AMD_F14_KR_B0 0x0000000000000400ull
// Family 14h Unknown stepping
-#define AMD_F14_UNKNOWN 0x8000000000000000
+#define AMD_F14_UNKNOWN 0x8000000000000000ull
#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1)
#define AMD_F14_ON_Bx (AMD_F14_ON_B0)
+#define AMD_F14_ON_Cx (AMD_F14_ON_C0)
+#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
-#define AMD_F14_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_UNKNOWN)
+#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
// Family 15h OROCHI steppings
-#define AMD_F15_OR_A0 0x0000000000000001
+#define AMD_F15_OR_A0 0x0000000000000001ull
+#define AMD_F15_OR_A1 0x0000000000000002ull
+#define AMD_F15_OR_B0 0x0000000000000004ull
+ // Family 15h TN steppings
+#define AMD_F15_TN_A0 0x0000000000000100ull
// Family 15h Unknown stepping
-#define AMD_F15_UNKNOWN 0x8000000000000000
+#define AMD_F15_UNKNOWN 0x8000000000000000ull
-#define AMD_F15_OR_Ax (AMD_F15_OR_A0)
+#define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1)
+#define AMD_F15_OR_Bx AMD_F15_OR_B0
+#define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx)
+#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
+#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
-#define AMD_F15_ALL (AMD_F15_OR_Ax | AMD_F15_UNKNOWN)
+#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
// Family 16h CPU_LOGICAL_ID.Revision equates
// TBD
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
- GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
+ GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
- GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
+ GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
NextRegister = FamilySpecificServices->RegisterList;
while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
ASSERT (RegisterEntryIndex <
IsEnabled = TRUE;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, StdHeader)) {
IsEnabled = FALSE;
break;
{
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Load any required microcode patches on both normal boot and resume from S3.
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, &C6FamilyServices, StdHeader);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
+ GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, (const VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
}
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &C6FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (const VOID **)&C6FamilyServices, StdHeader);
if (C6FamilyServices != NULL) {
// run code on all APs
TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n");
- GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->InitializeC6 (FamilyServices,
*((UINT64 *) EntryPoint),
&CpuEarlyParams->PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
);
+
+AGESA_STATUS
+InitializeCacheFlushOnHaltFeature (
+ IN UINT64 EntryPoint,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
{
CPU_CFOH_FAMILY_SERVICES *FamilyServices;
- GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader);
}
IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize);
RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
// Process each request entry 0 to 2
for (i = 0; i < 3; i++) {
AGESA_STATUS IgnoredStatus;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
// CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space"
ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode);
if (CacheInfoPtr->CarExeType == InfiniteExe) {
// Set down core register
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
+ GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (const VOID **)&FamilySpecificServices, StdHeader);
if (FamilySpecificServices != NULL) {
for (Module = 0; Module < NumberOfModules; Module++) {
RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader);
if (PlatformConfig->CpbMode == CpbModeAuto) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
IsEnabled = TRUE;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader);
IN UINT8 SizeInByte
);
+AGESA_STATUS
+GetDmiInfoStub (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT DMI_INFO **DmiTable
+ );
+
+AGESA_STATUS
+GetDmiInfoMain (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT DMI_INFO **DmiTable
+ );
+
+AGESA_STATUS
+ReleaseDmiBufferStub (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+ReleaseDmiBuffer (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
UINT16 NumberOfDimm;
UINT32 SocketNum;
UINT64 MsrData;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
BOOLEAN FamilyNotFound;
AGESA_STATUS Flag;
AGESA_STATUS CalledStatus;
// TYPE 19
DmiBufferPtr->T19.StartingAddr = 0;
- LibAmdMsrRead (TOP_MEM2, &MsrRegister, StdHeader);
- if (MsrRegister == 0) {
- LibAmdMsrRead (TOP_MEM, &MsrRegister, StdHeader);
- DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
- } else if (MsrRegister != 0) {
- DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
+ LibAmdMsrRead (TOP_MEM2, &MsrReg, StdHeader);
+ if (MsrReg == 0) {
+ LibAmdMsrRead (TOP_MEM, &MsrReg, StdHeader);
+ DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrReg >> 10);
+ } else if (MsrReg != 0) {
+ DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrReg >> 10);
}
DmiBufferPtr->T19.PartitionWidth = 0xFF;
{
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Socket;
UINT32 Core;
UINT32 NumberOfSockets;
*NeedLeveling = FALSE;
LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
}
}
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
}
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 AddressValue;
+ VOID *AddressValue;
- AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
+ AddressValue = (VOID *)GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
*Address = (UINT64 *)(AddressValue);
}
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);
+ GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&CpuServices, StdHeader);
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
HtHostFeats.HtHostValue = 0;
if (IsEnabled) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if ((FamilyServices == NULL) || !FamilyServices->IsHtAssistSupported (FamilyServices, Socket, StdHeader)) {
IsEnabled = FALSE;
break;
// cache is still enabled.
for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices[Socket], StdHeader);
+ GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (const VOID **)&FamilyServices[Socket], StdHeader);
} else {
FamilyServices[Socket] = NULL;
}
UINT32 CR0Data;
HT_ASSIST_FAMILY_SERVICES *FamilyServices;
- GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader);
+ GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (const VOID **)&FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookDisableCache (FamilyServices, &ApExeParams->StdHeader);
CR0Data &= ~(0x60000000);
LibAmdWriteCpuReg (0, CR0Data);
- GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader);
+ GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (const VOID **)&FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
if (GetNumberOfProcessors (StdHeader) == 1) {
GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
- GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader);
}
IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n");
if (IsWarmReset (StdHeader)) {
- GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, &IoCstateServices, StdHeader);
+ GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, (const VOID **)&IoCstateServices, StdHeader);
if (IoCstateServices != NULL) {
if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) {
IsSupported = TRUE;
{
IO_CSTATE_FAMILY_SERVICES *FamilyServices;
- GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->InitializeIoCstate (FamilyServices,
*((UINT64 *) EntryPoint),
&CpuEarlyParams->PlatformConfig,
IsSupported = FALSE;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
IsSupported = TRUE;
{
LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;
- GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->EnableLowPwrPstate (FamilyServices,
&CpuEarlyParams->PlatformConfig,
*((UINT64 *) EntryPoint),
} else {
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (const VOID **)&FamilyServices, StdHeader);
if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {
IsEnabled = FALSE;
break;
{
MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
- GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
FamilyServices->InitializeMsgBasedC1e (FamilyServices,
*((UINT64 *) EntryPoint),
&CpuEarlyParams->PlatformConfig,
*----------------------------------------------------------------------------
*/
+AGESA_STATUS
+PStateGatherStub (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
+ );
+
+AGESA_STATUS
+PStateGatherMain (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
ASSERT (IsBsp (StdHeader, &IgnoredSts));
FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
PopulatedSockets = 1;
FamilyServices = NULL;
PStateEnabled = FALSE;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
//
IN AMD_CONFIG_PARAMS *StdHeader
);
+AGESA_STATUS
+PStateLevelingStub (
+ IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+PStateLevelingMain (
+ IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+CorePstateRegModify (
+ IN VOID *CpuAmdPState,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/**
*---------------------------------------------------------------------------------------
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
PutCoreInPState0 (PStateBufferPtr, StdHeader);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+ if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilySpecificServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL)
FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader);
}
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
CorePstateRegModify (CpuAmdPState, StdHeader);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+ if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
return;
}
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
}
STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct =
{
- 'S','S','D','T',
+ {'S','S','D','T'},
0,
1,
0,
- 'A','M','D',' ',' ',' ',
- 'P','O','W','E','R','N','O','W',
+ {'A','M','D',' ',' ',' '},
+ {'P','O','W','E','R','N','O','W'},
1,
- 'A','M','D',' ',
+ {'A','M','D',' '},
1
};
*----------------------------------------------------------------------------
*/
+UINT32
+CalAcpiTablesSize (
+ IN S_CPU_AMD_PSTATE *AmdPstatePtr,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+GenerateSsdtStub (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT VOID **SsdtPtr
+ );
+
+UINT32
+CreateAcpiTablesStub (
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN PSTATE_LEVELING *PStateLevelingBuffer,
+ IN OUT VOID **SsdtPtr,
+ IN UINT8 LocalApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+CreatePStateAcpiTables (
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN PSTATE_LEVELING *PStateLevelingBuffer,
+ IN OUT VOID **SsdtPtr,
+ IN UINT8 LocalApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+CreateCStateAcpiTables (
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN PSTATE_LEVELING *PStateLevelingBuffer,
+ IN OUT VOID **SsdtPtr,
+ IN UINT8 LocalApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/**
*---------------------------------------------------------------------------------------
*
MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem;
if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
- GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader);
// If we're supporting multiple families, only proceed when IO Cstate family services are available
if (IoCstateFamilyServices != NULL) {
CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader);
}
ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__;
ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z'))
- ASSERT ((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z') || \
- (PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9') || \
+ ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \
+ ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \
(PlatformConfig->ProcessorScopeName1 == '_'))
ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0;
// Calculate PCI address for socket only
GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus);
TransAndBusMastLatency = 0;
- GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL)
FamilyServices->GetPstateLatency ( FamilyServices,
PStateLevelingBuffer,
pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables;
// Get Total Cores Per Node
if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) {
- GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader);
+ GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, (const VOID **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL)
if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) &&
FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) {
ObjSize = 0;
if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
- GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, (const VOID **)&IoCstateFamilyServices, StdHeader);
// If we're supporting multiple families, only proceed when IO Cstate family services are available
if (IoCstateFamilyServices != NULL) {
IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader);
STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct =
{
- 'S','L','I','T',
+ {'S','L','I','T'},
0,
1,
0,
- 'A','M','D',' ',' ',' ',
- 'A','G','E','S','A',' ',' ',' ',
+ {'A','M','D',' ',' ',' '},
+ {'A','G','E','S','A',' ',' ',' '},
1,
- 'A','M','D',' ',
+ {'A','M','D',' '},
1
};
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+
+AGESA_STATUS
+GetAcpiSlitStub (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT VOID **SlitPtr
+ );
+
+AGESA_STATUS
+GetAcpiSlitMain (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT VOID **SlitPtr
+ );
+
VOID
STATIC
AcpiSlitHBufferFind (
IN UINT8 **SocketTopologyPtr
);
+AGESA_STATUS
+ReleaseSlitBufferStub (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+ReleaseSlitBuffer (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
-
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct =
{
- 'S','R','A','T',
+ {'S','R','A','T'},
0,
2,
0,
- 'A','M','D',' ',' ',' ',
- 'A','G','E','S','A',' ',' ',' ',
+ {'A','M','D',' ',' ',' '},
+ {'A','G','E','S','A',' ',' ',' '},
1,
- 'A','M','D',' ',
+ {'A','M','D',' '},
1,
1,
{0, 0, 0, 0, 0, 0, 0, 0}
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+GetAcpiSratStub (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **SratPtr
+ );
+
+AGESA_STATUS
+GetAcpiSratMain (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **SratPtr
+ );
+
UINT8
STATIC
*MakeApicEntry (
if (GetNumberOfProcessors (StdHeader) == 1) {
GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
- GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &SwFamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&SwFamilyServices, StdHeader);
if (SwFamilyServices != NULL) {
IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader);
}
IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n");
if (IsWarmReset (StdHeader)) {
- GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
}
IN AMD_WHEA_INIT_DATA *WheaInitDataPtr
);
+AGESA_STATUS
+GetAcpiWheaStub (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **WheaMcePtr,
+ IN OUT VOID **WheaCmcPtr
+ );
+
+AGESA_STATUS
+GetAcpiWheaMain (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **WheaMcePtr,
+ IN OUT VOID **WheaCmcPtr
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
return AGESA_ERROR;
}
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetWheaInitData (FamilySpecificServices, &WheaInitDataPtr, &Entries, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (const VOID **)&WheaInitDataPtr, &Entries, StdHeader);
ASSERT (WheaInitDataPtr->HestBankNum <= BankNum);
{
DEVICE_DESCRIPTORS Device;
UINT16 i;
- UINT64 StartAddress;
- UINT64 EndAddress;
+ VOID *StartAddress;
+ VOID *EndAddress;
VOID *OrMask;
- StartAddress = (UINT64) DeviceList;
+ StartAddress = DeviceList;
Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
break;
}
}
- EndAddress = (UINT64) OrMask;
+ EndAddress = (VOID *) OrMask;
*ActualBufferSize = (UINT32) (EndAddress - StartAddress);
}
*----------------------------------------------------------------------------------------
*/
+VOID
+SetRegistersFromTablesAtEarly (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
TABLE_ENTRY_FIELDS *Entries;
ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL));
- ASSERT (Selector < TableEntryTypeMax);
+ ASSERT (Selector < TableCoreSelectorMax);
NextTable = *RegisterTableHandle;
if (NextTable == NULL) {
}
// Get some family, model specific performance type info.
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
// Is the Northbridge P-State feature enabled
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->NextLinkHasHtPhyFeats (
FamilySpecificServices,
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) {
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
// Check if the actual processor count and SystemDegree are in either range.
ProcessorCount = GetNumberOfProcessors (StdHeader);
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0);
IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuFamilyRevision, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
Link = 0;
while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
//
// Get some specific platform type info, VC...etc.
//
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
ASSERT (FamilySpecificServices != NULL);
FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader);
PlatformFeatures.PlatformValue = 0;
GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader);
- GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, StdHeader);
+ GetCpuServicesFromLogicalId (&CpuLogicalId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
// Build a non-sparse table of implementer methods, so we don't have to keep searching.
// It is a bug to not include a descriptor for a type that is in the table (but the
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
);
typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER;
+/// Interrupt Descriptor Table entry
+typedef struct {
+ UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
+ UINT16 Selector; ///< Interrupt handler routine's selector
+ UINT8 Rsvd; ///< Reserved
+ UINT8 Flags; ///< Interrupt flags
+ UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
+ UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
+ UINT32 Rsvd64; ///< Reserved
+} IDT_DESCRIPTOR;
+
+/// Structure needed to load the IDTR using the lidt instruction
+//typedef struct {
+// UINT16 Limit; ///< Interrupt Descriptor Table size
+// UINT64 Base; ///< Interrupt Descriptor Table base address
+//} IDT_BASE_LIMIT;
+
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
IN AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+LocalApicInitialization (
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+LocalApicInitializationAtEarly (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
DescSize = 8;
}
- HandlerOffset = (UINT64) NmiHandler;
- NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF;
- NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16);
+ HandlerOffset = (UINT64)&NmiHandler;
+ NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF);
+ NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF);
GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);
NmiIdtDescPtr->Flags = SEG_DESC_PRESENT | SEG_DESC_TYPE_INT32;
NmiIdtDescPtr->Rsvd = 0;
{
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) {
while (Core-- > 0) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
UINT32 CacheEnDis;
CPU_SPECIFIC_SERVICES *FamilyServices;
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
// CacheEnDis is a family specific flag, that lets the code to decide whether to
// keep the cache control bits set or cleared.
UINT32 Socket;
UINT32 Core;
UINT32 BscSocket;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 NumberOfSockets;
UINT32 NumberOfCores;
UINT32 Ignored;
AgesaStatus = AGESA_SUCCESS;
- // Get the BscSocket, BscCore and NumberOfSockets in the system
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ // Get the BscSocket, BscCoreNum and NumberOfSockets in the system
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
// Setup TaskPtr struct to execute routine on APs
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
} else {
ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader);
*----------------------------------------------------------------------------------------
*/
+VOID
+SetBrandIdRegistersAtEarly (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
SocketTablePtr = NULL;
SocketTableEntry = NULL;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
// Step1: Allocate 48 bytes from Heap space
AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH;
AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE;
}
// Step5: Search for String1 (there can be only 1)
- FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
+ FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
&& (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
// Step9: Search for String2
SuffixStatus = 0;
- FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
+ FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (const VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
&& (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
IN AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+McaInitialization (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+McaInitializationAtEarly (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*------------------------------------------------------------------------------------*/
+
+VOID
+AmdCpuEarlyInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+ );
+
/**
* Initializer routine that will be invoked by AmdCpuEarly to initialize the input
* structure for the Cpu Init @ Early routine.
IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
EarlyTableOnCore = NULL;
- FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, &EarlyTableOnCore, &CpuEarlyParams, StdHeader);
+ FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (const S_PERFORM_EARLY_INIT_ON_CORE **) &EarlyTableOnCore, &CpuEarlyParams, StdHeader);
if (EarlyTableOnCore != NULL) {
GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader);
for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) {
// Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization.
// Use '0' as a dummy heap index value.
GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader);
- GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader);
+ GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader);
FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader);
ApHeapIndex = 1;
while (NodeNum < MAX_NODES &&
GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) {
- GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader);
+ GetCpuServicesOfSocket (SocketNum, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader);
if (NodeNum == 0) {
StartCore = (UINT8) PrimaryCore + 1;
NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements;
SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable;
for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) {
- SubFamilyIdPtr[j] (&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader);
+ SubFamilyIdPtr[j] ((const CPU_LOGICAL_ID_XLAT **)&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader);
ASSERT (CpuLogicalIdAndRevPtr != NULL);
for (k = 0; k < LogicalIdEntries; k++) {
if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) {
{
GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable,
Socket,
- FunctionTable,
+ (const VOID **)FunctionTable,
StdHeader);
if (*FunctionTable == NULL) {
*FunctionTable = &cpuNullServices;
)
{
GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable,
- FunctionTable,
+ (const VOID **)FunctionTable,
StdHeader);
if (*FunctionTable == NULL) {
*FunctionTable = &cpuNullServices;
{
GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable,
LogicalId,
- FunctionTable,
+ (const VOID **)FunctionTable,
StdHeader);
if (*FunctionTable == NULL) {
*FunctionTable = &cpuNullServices;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
- UINT32 PciRegister;
+ UINT32 PciReg;
AGESA_STATUS AgesaStatus;
PCI_ADDR Reg;
if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
Reg.Address.Function = PciAddress->Address.Function;
Reg.Address.Register = PciAddress->Address.Register;
- LibAmdPciRead (AccessWidth32, Reg, &PciRegister, StdHeader);
- PciRegister &= Mask;
- PciRegister |= Data;
- LibAmdPciWrite (AccessWidth32, Reg, &PciRegister, StdHeader);
+ LibAmdPciRead (AccessWidth32, Reg, &PciReg, StdHeader);
+ PciReg &= Mask;
+ PciReg |= Data;
+ LibAmdPciWrite (AccessWidth32, Reg, &PciReg, StdHeader);
}
}
}
CORE_ID_POSITION InitApicIdCpuIdLo;
CPU_SPECIFIC_SERVICES *FamilyServices;
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
// Read CPUID ebx[31:24] to get initial APICID
*ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info;
} else if (!IamBsp) {
// If this is an AP, the hardware register should be good.
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
*ApMailboxInfo = ApMailboxes.ApMailInfo.Info;
AP_MAILBOXES ApMailboxes;
CPU_SPECIFIC_SERVICES *FamilyServices;
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
// Get mailbox from hardware.
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
LibAmdMsrRead (TSC, &InitialTsc, StdHeader);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
NumberOfTicks = Microseconds * TscRateInMhz;
do {
Result = MaxComputeUnitMapping;
IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
// Get data block from heap
)
{
UINT8 EncodedSize;
- UINT64 MsrRegister;
+ UINT64 MsrReg;
// Make sure that Standard header is valid
ASSERT (StdHeader != NULL);
if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) {
EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize);
- MsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2));
- LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader);
+ MsrReg = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2));
+ LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
}
}
*----------------------------------------------------------------------------------------
*/
+VOID
+GetCommonEarlyInitOnCoreTable (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
UINT8 ApicId;
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
AGESA_STATUS CalledStatus;
AGESA_STATUS IgnoredStatus;
AGESA_STATUS AgesaStatus;
AgesaStatus = AGESA_SUCCESS;
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredStatus);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus);
NumberOfSockets = GetPlatformNumberOfSockets ();
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);
AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);
CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+LoadMicrocodePatchAtEarly (
+ IN CPU_SPECIFIC_SERVICES *FamilyServices,
+ IN AMD_CPU_EARLY_PARAMS *EarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
// Get the patch pointer
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (const VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader);
IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader);
//
// find the equivalent ID for microcode purpose using the equivalence table
//
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices,
- &MicrocodeEquivalenceTable,
+ (const VOID **) &MicrocodeEquivalenceTable,
&EquivalencyEntries,
StdHeader);
IN AMD_CONFIG_PARAMS *StdHeader
);
+AGESA_STATUS
+GetPstateGatherDataAddressAtPost (
+ OUT UINT64 **Ptr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+SyncAllApMtrrToBsc (
+ IN VOID *MtrrTable,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- UINT64 AddressValue;
+ VOID *AddressValue;
- AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
+ AddressValue = (VOID *)P_STATE_DATA_GATHER_TEMP_ADDR;
- *Ptr = (UINT64 *)(AddressValue);
+ *Ptr = AddressValue;
return AGESA_SUCCESS;
}
UINT16 i;
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
ASSERT (IsBsp (StdHeader, &IgnoredSts));
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
//
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
+ GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (const VOID **)&FamilyServices, StdHeader);
if (FamilyServices != NULL) {
FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader);
}
AP_TASK TaskPtr;
UINT32 BscSocket;
UINT32 Ignored;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Core;
UINT32 Socket;
UINT32 NumberOfSockets;
ASSERT (IsBsp (StdHeader, &IgnoredSts));
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+ IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredSts);
NumberOfSockets = GetPlatformNumberOfSockets ();
SetTscFreqSel (StdHeader);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
+ if ((Socket != BscSocket) || (Core != BscCoreNum)) {
ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
}
}
SYS_PM_TBL_STEP *FamilyTablePtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &FamilyTablePtr, &MyNumberOfSteps, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&FamilyTablePtr, &MyNumberOfSteps, StdHeader);
if (*(UINT8 *)Step < MyNumberOfSteps) {
if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) {
{
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader);
}
IN AMD_CONFIG_PARAMS *StdHeader
);
+AGESA_STATUS
+GetEarlyPmErrorsMulti (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
{
UINT32 BscSocket;
UINT32 BscModule;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT8 Socket;
UINT32 NumberOfSockets;
AGESA_STATUS DummyStatus;
NumberOfSockets = GetPlatformNumberOfSockets ();
- IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus);
+ IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (Socket != BscSocket) {
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &Ignored, &NumberOfSteps, StdHeader);
+ GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&Ignored, &NumberOfSteps, StdHeader);
if (NumberOfSteps > *NumSystemSteps) {
*NumSystemSteps = NumberOfSteps;
}
NbPstateDisabled = FALSE;
for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
+ GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) {
break;
AtLeast1RequiresUpdate = FALSE;
for (Socket = 0; Socket < NumberOfSockets; Socket++) {
if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
+ GetCpuServicesOfSocket (Socket, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) {
break;
UINT16 i;
UINT32 BscSocket;
UINT32 BscModule;
- UINT32 BscCore;
+ UINT32 BscCoreNum;
UINT32 Socket;
UINT32 NumberOfSockets;
AP_TASK TaskPtr;
EventLogEntry.DataParam4 = 0;
NumberOfSockets = GetPlatformNumberOfSockets ();
- IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus);
+ IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus);
TaskPtr.FuncAddress.PfApTaskI = GetNextEvent;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT);
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+GetEarlyPmErrorsSingle (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
SYS_PM_TBL_STEP *Ignored;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &Ignored, NumSystemSteps, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (const VOID **)&Ignored, NumSystemSteps, StdHeader);
}
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
*SystemNbCofsMatch = TRUE;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
*NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
PlatformConfig,
&PciAddress,
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
+ * @e \$Revision: 48588 $ @e \$Date: 2011-03-10 08:57:36 -0700 (Thu, 10 Mar 2011) $
*
*/
/*
#define MSR_SYS_CFG 0xC0010010 // SYSCFG - F15 Shared
#define MSR_TOM2 0xC001001D // TOP_MEM2 - F15 Shared
+#define MSR_MC0_CTL_MASK 0xC0010044 // MC0 Control Mask
+#define MSR_MC1_CTL_MASK 0xC0010045 // MC1 Control Mask
+#define MSR_MC2_CTL_MASK 0xC0010046 // MC2 Control Mask
#define MSR_MC4_CTL_MASK 0xC0010048 // MC4 Control Mask
#define MSR_CPUID_FEATS 0xC0011004 // CPUID Features
REG_EDX ///< EDX
} CPUID_REG;
-/// MSR table entry for DSM workaround
-typedef struct {
- UINT32 Address; ///< MSR address to program
- UINT64 Nand; ///< Bitwise NAND mask to apply during read-modify-write
- UINT64 Or; ///< Bitwise OR mask to apply during read-modify-write
-} MSR_DSM_ENTRY;
-
-/// Interrupt Descriptor Table entry
-typedef struct {
- UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
- UINT16 Selector; ///< Interrupt handler routine's selector
- UINT8 Rsvd; ///< Reserved
- UINT8 Flags; ///< Interrupt flags
- UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
- UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
- UINT32 Rsvd64; ///< Reserved
-} IDT_DESCRIPTOR;
-
+/// Structure needed to load the IDTR using the lidt instruction
typedef struct {
UINT16 Limit; ///< Interrupt Descriptor Table size
UINT64 Base; ///< Interrupt Descriptor Table base address
} IDT_BASE_LIMIT;
+
#endif // _CPU_REGISTERS_H_
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
}
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
FamilySpecificServices = NULL;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
switch (StdHeader->Func) {
break;
}
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
if (Request.StateBits >= PostStage) {
return AGESA_FATAL;
}
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
HeapBufferPtr = (UINT8 *) StdHeader->HeapBasePtr;
// Check whether the heap manager is already initialized
* @return Heap base address of the executing core's heap.
*
*/
-UINT64
-HeapGetBaseAddress (
+VOID
+*HeapGetBaseAddress (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
HEAP_MANAGER *HeapManager;
BUFFER_NODE *CurrentFreeSpaceNode;
BUFFER_NODE *PreviousFreeSpaceNode;
- BUFFER_NODE *InsertFreeSpaceNode;
+ BUFFER_NODE *FreeSpaceInsertNode;
BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
HeapManager = (HEAP_MANAGER *) BaseAddress;
OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset;
CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- InsertFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode);
+ FreeSpaceInsertNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode);
while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) &&
- (CurrentFreeSpaceNode->BufferSize < InsertFreeSpaceNode->BufferSize)) {
+ (CurrentFreeSpaceNode->BufferSize < FreeSpaceInsertNode->BufferSize)) {
OffsetOfPreviousNode = OffsetOfCurrentNode;
OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode;
CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
}
- InsertFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode;
+ FreeSpaceInsertNode->OffsetOfNextNode = OffsetOfCurrentNode;
if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode;
} else {
if (IsBsp (StdHeader, &IgnoredStatus)) {
ReturnPtr = AMD_HEAP_START_ADDRESS;
} else {
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilyServices, StdHeader);
ASSERT (FamilyServices != NULL);
SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader);
#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF
#define AMD_HEAP_SIZE_PER_CORE 0x010000
#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFF
-#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800 & ((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800))
+#define AMD_HEAP_MTRR_MASK (0xFFFFFFFFFFFFF800ull & (((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800))
#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
#define AMD_TEMP_TOM 0x20000000 // Set TOM to 512 MB (temporary value)
} HEAP_MANAGER;
/// AGESA Buffer Handles (These are reserved)
-typedef enum {
+typedef enum _AGESA_BUFFER_HANDLE {
AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
IN AMD_CONFIG_PARAMS *StdHeader
);
-UINT64
-HeapGetBaseAddress (
+VOID
+*HeapGetBaseAddress (
IN AMD_CONFIG_PARAMS *StdHeader
);
#include "cpuServices.h"
#include "CommonInits.h"
#include "GnbInterface.h"
+//#include "GnbInitAtEarly.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+AmdEarlyPlatformConfigInit (
+ IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AllocateExecutionCacheInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+ );
+
+AGESA_STATUS
+AmdInitEarlyInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ );
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
#include "Ids.h"
#include "cpuEnvInit.h"
#include "heapManager.h"
+#include "CreateStruct.h"
#include "GnbInterface.h"
#include "CommonInits.h"
#include "S3SaveState.h"
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+AmdLatePlatformConfigInit (
+ IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AmdInitLateInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT AMD_LATE_PARAMS *LateParamsPtr
+ );
+
+AGESA_STATUS
+AmdInitLateDestructor (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_LATE_PARAMS *LateParamsPtr
+ );
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
#include "Ids.h"
#include "cpuFeatures.h"
#include "CommonInits.h"
+#include "CreateStruct.h"
#include "GnbInterface.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
#include "cpuServices.h"
#include "cpuPostInit.h"
#include "AdvancedApi.h"
+#include "CreateStruct.h"
#include "heapManager.h"
#include "CommonInits.h"
#include "cpuServices.h"
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+AmdPostPlatformConfigInit (
+ IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+AmdInitResetExecutionCacheAllocateInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+ );
+
+AGESA_STATUS
+AmdInitResetConstructor (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_RESET_PARAMS *AmdResetParams
+ );
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuPostInit.h"
+#include "CreateStruct.h"
#include "CommonInits.h"
#include "cpuFeatures.h"
CODE_GROUP (G1_PEICC)
#include "AGESA.h"
#include "Ids.h"
#include "Options.h"
+#include "CreateStruct.h"
#include "Filecode.h"
CODE_GROUP (G3_DXE)
RDATA_GROUP (G3_DXE)
#include "cpuFeatures.h"
#include "S3SaveState.h"
#include "CommonInits.h"
+#include "CreateStruct.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
ASSERT (S3LateParams != NULL);
BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
- S3LateParams->StdHeader.HeapBasePtr = (UINT64) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
+ S3LateParams->StdHeader.HeapBasePtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL);
IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
#include "S3.h"
#include "mfs3.h"
#include "CommonInits.h"
+#include "CreateStruct.h"
#include "Filecode.h"
#include "heapManager.h"
#include "Topology.h"
BufferPointer = AllocParams.BufferPtr;
AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]);
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = NULL;
+ ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = 0;
((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize;
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = NULL;
+ ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = 0;
((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize;
if (HeapSize != 0) {
*/
#include "AGESA.h"
#include "Ids.h"
+#include "CommonInits.h"
#include "Filecode.h"
#include "heapManager.h"
CODE_GROUP (G1_PEICC)
#include "AGESA.h"
#include "Ids.h"
+#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) {
// APs must transfer their system core number from the mailbox to
// a local register while it is still valid.
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &InterfaceParams->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &InterfaceParams->StdHeader);
FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader);
}
InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET;
/// Do NOT include a config params header!
OUT PF_AGESA_FUNCTION AgesaFunction; ///< The constructor function
OUT PF_AGESA_DESTRUCTOR AgesaDestructor; ///< The destructor function.
- IN AGESA_BUFFER_HANDLE BufferHandle; ///< The buffer handle id for the service.
+ IN UINT32 BufferHandle; ///< The buffer handle id for the service.
} FUNCTION_PARAMS_INFO;
/**
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+S3SaveStateExtendTableLenth (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
+ );
+
/*----------------------------------------------------------------------------------------*/
/**
* Initialize S3 Script framework
{
switch (Op) {
case SAVE_STATE_IO_WRITE_OPCODE:
- return "IO WR";
+ return (CHAR8*)"IO WR";
case SAVE_STATE_IO_READ_WRITE_OPCODE:
- return "IO RD/WR";
+ return (CHAR8*)"IO RD/WR";
case SAVE_STATE_IO_POLL_OPCODE:
- return "IO POLL";
+ return (CHAR8*)"IO POLL";
case SAVE_STATE_MEM_WRITE_OPCODE:
- return "MEM WR";
+ return (CHAR8*)"MEM WR";
case SAVE_STATE_MEM_READ_WRITE_OPCODE:
- return "MEM RD/WR";
+ return (CHAR8*)"MEM RD/WR";
case SAVE_STATE_MEM_POLL_OPCODE:
- return "MEM POLL";
+ return (CHAR8*)"MEM POLL";
case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
- return "PCI WR";
+ return (CHAR8*)"PCI WR";
case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
- return "PCI RD/WR";
+ return (CHAR8*)"PCI RD/WR";
case SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
- return "PCI POLL";
+ return (CHAR8*)"PCI POLL";
case SAVE_STATE_STALL_OPCODE:
- return "STALL";
+ return (CHAR8*)"STALL";
case SAVE_STATE_DISPATCH_OPCODE:
- return "DISPATCH";
+ return (CHAR8*)"DISPATCH";
default:
IDS_ERROR_TRAP;
}
- return "!!! Unrecognize opcode !!!";
+ return (CHAR8*)"!!! Unrecognize opcode !!!";
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
#endif
#endif
+#ifndef MIN
#define MIN(x, y) (((x) > (y))? (y):(x))
+#endif
+
+#ifndef MAX
#define MAX(x, y) (((x) > (y))? (x):(y))
+#endif
#define OFF 0
-#define PVOID UINT64
-
#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader)
#define AGESA_STATUS_UPDATE(Current, Aggregated) \
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 38902 $ @e \$Date: 2010-10-02 02:01:38 +0800 (Sat, 02 Oct 2010) $
+ * @e \$Revision: 47437 $ @e \$Date: 2011-02-20 15:32:39 -0700 (Sun, 20 Feb 2011) $
*
*/
/*
#define PP_FUSE_MAX_NUM_DPM_STATE 5
#define PP_FUSE_MAX_NUM_SW_STATE 6
+
/// Fuse definition structure
typedef struct {
UINT8 PPlayTableRev; ///< PP table revision
UINT8 SclkDpmValid[6]; ///< Valid DPM states
- UINT8 SclkDpmDid[5]; ///< Sclk DPM DID
- UINT8 SclkDpmVid[5]; ///< Sclk DPM VID
- UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac
+ UINT8 SclkDpmDid[6]; ///< Sclk DPM DID
+ UINT8 SclkDpmVid[6]; ///< Sclk DPM VID
+ UINT8 SclkDpmCac[6]; ///< Sclk DPM Cac
UINT8 PolicyFlags[6]; ///< State policy flags
UINT8 PolicyLabel[6]; ///< State policy label
UINT8 VclkDid[4]; ///< VCLK DID
UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID
UINT8 MainPllId; ///< Main PLL Id from fuses
UINT8 WrCkDid; ///< WRCK SMU clock Divisor
+ UINT8 GpuBoostCap; ///< GPU boost cap
+ UINT16 SclkDpmTdpLimit[6]; ///< Sclk DPM TDP limit
+ UINT16 SclkDpmTdpLimitPG; ///< TDP limit PG
+ UINT32 SclkDpmBoostMargin; ///< Boost margin
+ UINT32 SclkDpmThrottleMargin; ///< Throttle margin
} PP_FUSE_ARRAY;
#pragma pack (pop)
#ifndef _GNBGFX_H_
#define _GNBGFX_H_
-//#ifndef PVOID
-// typedef UINT64 PVOID;
-//#endif
-
#define DEVICE_DFP 0x1
#define DEVICE_CRT 0x2
#define DEVICE_LCD 0x3
/// Graphics Platform Configuration
typedef struct {
- PVOID StdHeader; ///< Standard Header
+ AMD_CONFIG_PARAMS* StdHeader; ///< Standard Header
PCI_ADDR GfxPciAddress; ///< Graphics PCI Address
UMA_INFO UmaInfo; ///< UMA Information
UINT32 GmmBase; ///< GMM Base
GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode
UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+ LVDS_MISC_CONTROL LvdsMiscControl; ///< This item configures LVDS swap/Hsync/Vsync/BLON
+ UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
} GFX_PLATFORM_CONFIG;
USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz
USHORT usDVISSPercentage; ///< usDVISSPercentage
USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz
- ULONG ulReserved3[21]; ///< Reserved
+ ULONG SclkDpmBoostMargin; ///< SclkDpmBoostMargin
+ ULONG SclkDpmThrottleMargin; ///< SclkDpmThrottleMargin
+ USHORT SclkDpmTdpLimitPG; ///< SclkDpmTdpLimitPG
+ USHORT SclkDpmTdpLimitBoost; ///< SclkDpmTdpLimitBoost
+ ULONG ulBoostEngineCLock; ///< ulBoostEngineCLock
+ UCHAR ulBoostVid_2bit; ///< ulBoostVid_2bit
+ UCHAR EnableBoost; ///< EnableBoost
+ USHORT GnbTdpLimit; ///< GnbTdpLimit
+ ULONG ulReserved3[16]; ///< Reserved
ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition
} ATOM_INTEGRATED_SYSTEM_INFO_V6;
IN GFX_PLATFORM_CONFIG *Gfx
);
-AGESA_STATUS
+UINT32
GfxFmCalculateClock (
IN UINT8 Did,
IN AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+GfxFmSetIdleVoltageMode (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
#endif
#include "AMD.h"
#include "Gnb.h"
#include "OptionGnb.h"
+#include "GnbLibFeatures.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+GnbCommonFeatureStub (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
#define UNUSED_LANE_ID 128
-#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
-#define PCIE_LINK_L0_POOLING (60 * 1000)
-#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
-#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
-
-#define IS_LAST_DESCRIPTOR(x) (x->Flags & DESCRIPTOR_TERMINATE_LIST) == 0
-#define IS_VALID_DESCRIPTOR(x) ((x->Flags & DESCRIPTOR_ALLOCATED) != 0)
-
-// Get lowes phy lane on engine
-#define PcieUtilGetLoPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane)
-// Get highest phy lane on engine
-#define PcieUtilGetHiPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane)
+
+#define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1))
+#define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
+
+// Get lowest PHY lane on engine
+#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF)
+// Get highest PHY lane on engine
+#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF)
// Get number of lanes on wrapper
-#define PcieLibWrapperNumberOfLanes(Wrapper) ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1))
+#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0)
// Check if virtual descriptor
-#define PcieLibIsVirtualDesciptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0)
+#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) : (1==0))
// Check if it is allocated descriptor
-#define PcieLibIsEngineAllocated(Descriptor) ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0)
+#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
// Check if it is last descriptor in list
-#define PcieLibIsLastDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0)
+#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1))
// Check if descriptor a PCIe engine
-#define PcieLibIsPcieEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0)
+#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0))
// Check if descriptor a DDI engine
-#define PcieLibIsDdiEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0)
+#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0))
// Check if descriptor a DDI wrapper
-#define PcieLibIsDdiWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0)
+#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0))
// Check if descriptor a PCIe wrapper
-#define PcieLibIsPcieWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0)
+#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0))
// Check if descriptor a PCIe wrapper
-#define PcieLibGetNextDescriptor(Descriptor) ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor)))
+#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL)
#define LANE_TYPE_ACTIVE (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE)
#define LANE_TYPE_ALLOCATED (LANE_TYPE_PCIE_ALLOCATED | LANE_TYPE_DDI_ALLOCATED)
-typedef UINT64 PPCIe_ENGINE_CONFIG;
-typedef UINT64 PPCIe_WRAPPER_CONFIG;
-typedef UINT64 PPCIe_SILICON_CONFIG;
+//typedef UINT64 PPCIe_ENGINE_CONFIG;
+//typedef UINT64 PPCIe_WRAPPER_CONFIG;
+//typedef UINT64 PPCIe_SILICON_CONFIG;
#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull
#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull
#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011
#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012
+/// PCIe Link Training State
+typedef enum {
+ PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit.
+ ///< PCIe device accessible after AmdEarlyInit complete
+ PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore
+ ///< PCIe device accessible after AmdPostInit complete.
+ ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots.
+} PCIE_TRAINING_ALGORITHM;
+
/// PCIe port configuration info
typedef struct {
PCIe_PORT_DATA PortData; ///< Port data
* @li @b Bit31 - last descriptor on wrapper
* @li @b Bit30 - Descriptor allocated for PCIe port or DDI
*/
- PPCIe_WRAPPER_CONFIG Wrapper; ///< Pointer to parent wrapper
+ VOID *Wrapper; ///< Pointer to parent wrapper
PCIe_ENGINE_DATA EngineData; ///< Engine Data
UINT32 InitStatus; ///< Initialization Status
UINT8 Scratch; ///< Scratch pad
UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down
UINT8 PllOffInL1:1; ///< PLL off in L1
} Features;
- PPCIe_ENGINE_CONFIG EngineList; ///< Pointer to Engine list
- PPCIe_SILICON_CONFIG Silicon; ///< Pointer to parent silicon
- PVOID FmWrapper; ///< Pointer to family Specific configuration data
+ VOID *EngineList; ///< Pointer to Engine list
+ VOID *Silicon; ///< Pointer to parent silicon
+ VOID *FmWrapper; ///< Pointer to family Specific configuration data
} PCIe_WRAPPER_CONFIG;
* @li @b Bit31 - last descriptor on complex
*/
PCI_ADDR Address; ///< PCI address of GNB host bridge
- PPCIe_WRAPPER_CONFIG WrapperList; ///< Pointer to wrapper list
- PVOID FmSilicon; ///< Pointer to family Specific configuration data
+ VOID *WrapperList; ///< Pointer to wrapper list
+ VOID *FmSilicon; ///< Pointer to family Specific configuration data
} PCIe_SILICON_CONFIG;
#define PcieSiliconGetWrapperList(mSiliconPtr) ((PCIe_WRAPPER_CONFIG *) (mSiliconPtr->WrapperList))
* @li @b Bit31 - last descriptor on platform
*/
UINT8 SocketId; ///< Processor socket ID
- PPCIe_SILICON_CONFIG SiliconList; ///< Pointer to silicon list
+ VOID *SiliconList; ///< Pointer to silicon list
} PCIe_COMPLEX_CONFIG;
#define PcieComplexGetSiliconList(mComplexPtr) ((PCIe_SILICON_CONFIG *)(UINTN)((mComplexPtr)->SiliconList))
/// PCIe platform configuration info
typedef struct {
- PVOID StdHeader; ///< Standard configuration header
+ AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header
UINT64 This; ///< base structure Base
UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
UINT8 GfxCardWorkaround; ///< GFX Card Workaround
UINT8 PsppPolicy; ///< PSPP policy
+ UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE)
+ UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///<
} PCIe_PLATFORM_CONFIG;
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
- *
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
- *
+ *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
UINT32 Value; ///<
} D18F2x80_STRUCT;
-// **** D18F2x084 Register Definition ****
+// **** D18F2x84 Register Definition ****
// Address
-#define D18F2x084_ADDRESS 0x84
+#define D18F2x84_ADDRESS 0x84
// Type
-#define D18F2x084_TYPE TYPE_D18F2
+#define D18F2x84_TYPE TYPE_D18F2
// Field Data
-#define D18F2x084_BurstCtrl_OFFSET 0
-#define D18F2x084_BurstCtrl_WIDTH 2
-#define D18F2x084_BurstCtrl_MASK 0x3
-#define D18F2x084_Reserved_3_2_OFFSET 2
-#define D18F2x084_Reserved_3_2_WIDTH 2
-#define D18F2x084_Reserved_3_2_MASK 0xc
-#define D18F2x084_Twr_OFFSET 4
-#define D18F2x084_Twr_WIDTH 3
-#define D18F2x084_Twr_MASK 0x70
-#define D18F2x084_Reserved_19_7_OFFSET 7
-#define D18F2x084_Reserved_19_7_WIDTH 13
-#define D18F2x084_Reserved_19_7_MASK 0xfff80
-#define D18F2x084_Tcwl_OFFSET 20
-#define D18F2x084_Tcwl_WIDTH 3
-#define D18F2x084_Tcwl_MASK 0x700000
-#define D18F2x084_PchgPDModeSel_OFFSET 23
-#define D18F2x084_PchgPDModeSel_WIDTH 1
-#define D18F2x084_PchgPDModeSel_MASK 0x800000
-#define D18F2x084_Reserved_31_24_OFFSET 24
-#define D18F2x084_Reserved_31_24_WIDTH 8
-#define D18F2x084_Reserved_31_24_MASK 0xff000000
+#define D18F2x84_BurstCtrl_OFFSET 0
+#define D18F2x84_BurstCtrl_WIDTH 2
+#define D18F2x84_BurstCtrl_MASK 0x3
+#define D18F2x84_Reserved_3_2_OFFSET 2
+#define D18F2x84_Reserved_3_2_WIDTH 2
+#define D18F2x84_Reserved_3_2_MASK 0xc
+#define D18F2x84_Twr_OFFSET 4
+#define D18F2x84_Twr_WIDTH 3
+#define D18F2x84_Twr_MASK 0x70
+#define D18F2x84_Reserved_19_7_OFFSET 7
+#define D18F2x84_Reserved_19_7_WIDTH 13
+#define D18F2x84_Reserved_19_7_MASK 0xfff80
+#define D18F2x84_Tcwl_OFFSET 20
+#define D18F2x84_Tcwl_WIDTH 3
+#define D18F2x84_Tcwl_MASK 0x700000
+#define D18F2x84_PchgPDModeSel_OFFSET 23
+#define D18F2x84_PchgPDModeSel_WIDTH 1
+#define D18F2x84_PchgPDModeSel_MASK 0x800000
+#define D18F2x84_Reserved_31_24_OFFSET 24
+#define D18F2x84_Reserved_31_24_WIDTH 8
+#define D18F2x84_Reserved_31_24_MASK 0xff000000
-/// D18F2x084
+/// D18F2x84
typedef union {
struct { ///<
UINT32 BurstCtrl:2 ; ///<
UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x084_STRUCT;
-
-// **** D18F2x08C Register Definition ****
-// Address
-#define D18F2x08C_ADDRESS 0x8c
-
-// Type
-#define D18F2x08C_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x08C_TrwtWB_OFFSET 0
-#define D18F2x08C_TrwtWB_WIDTH 4
-#define D18F2x08C_TrwtWB_MASK 0xf
-#define D18F2x08C_TrwtTO_OFFSET 4
-#define D18F2x08C_TrwtTO_WIDTH 4
-#define D18F2x08C_TrwtTO_MASK 0xf0
-#define D18F2x08C_Reserved_9_8_OFFSET 8
-#define D18F2x08C_Reserved_9_8_WIDTH 2
-#define D18F2x08C_Reserved_9_8_MASK 0x300
-#define D18F2x08C_Twrrd_1_0__OFFSET 10
-#define D18F2x08C_Twrrd_1_0__WIDTH 2
-#define D18F2x08C_Twrrd_1_0__MASK 0xc00
-#define D18F2x08C_Twrwr_1_0__OFFSET 12
-#define D18F2x08C_Twrwr_1_0__WIDTH 2
-#define D18F2x08C_Twrwr_1_0__MASK 0x3000
-#define D18F2x08C_Trdrd_1_0__OFFSET 14
-#define D18F2x08C_Trdrd_1_0__WIDTH 2
-#define D18F2x08C_Trdrd_1_0__MASK 0xc000
-#define D18F2x08C_Tref_OFFSET 16
-#define D18F2x08C_Tref_WIDTH 2
-#define D18F2x08C_Tref_MASK 0x30000
-#define D18F2x08C_DisAutoRefresh_OFFSET 18
-#define D18F2x08C_DisAutoRefresh_WIDTH 1
-#define D18F2x08C_DisAutoRefresh_MASK 0x40000
-#define D18F2x08C_Reserved_19_19_OFFSET 19
-#define D18F2x08C_Reserved_19_19_WIDTH 1
-#define D18F2x08C_Reserved_19_19_MASK 0x80000
-#define D18F2x08C_Trfc0_OFFSET 20
-#define D18F2x08C_Trfc0_WIDTH 3
-#define D18F2x08C_Trfc0_MASK 0x700000
-#define D18F2x08C_Trfc1_OFFSET 23
-#define D18F2x08C_Trfc1_WIDTH 3
-#define D18F2x08C_Trfc1_MASK 0x3800000
-#define D18F2x08C_Reserved_31_26_OFFSET 26
-#define D18F2x08C_Reserved_31_26_WIDTH 6
-#define D18F2x08C_Reserved_31_26_MASK 0xfc000000
-
-/// D18F2x08C
+} D18F2x84_STRUCT;
+
+// **** D18F2x88 Register Definition ****
+// Address
+#define D18F2x88_ADDRESS 0x88
+
+// Type
+#define D18F2x88_TYPE TYPE_D18F2
+// Field Data
+#define D18F2x88_Tcl_OFFSET 0
+#define D18F2x88_Tcl_WIDTH 4
+#define D18F2x88_Tcl_MASK 0xf
+#define D18F2x88_Reserved_23_4_OFFSET 4
+#define D18F2x88_Reserved_23_4_WIDTH 20
+#define D18F2x88_Reserved_23_4_MASK 0xfffff0
+#define D18F2x88_MemClkDis_OFFSET 24
+#define D18F2x88_MemClkDis_WIDTH 8
+#define D18F2x88_MemClkDis_MASK 0xff000000
+
+/// D18F2x88
+typedef union {
+ struct { ///<
+ UINT32 Tcl:4 ; ///<
+ UINT32 Reserved_23_4:20; ///<
+ UINT32 MemClkDis:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2x88_STRUCT;
+
+// **** D18F2x8C Register Definition ****
+// Address
+#define D18F2x8C_ADDRESS 0x8c
+
+// Type
+#define D18F2x8C_TYPE TYPE_D18F2
+// Field Data
+#define D18F2x8C_TrwtWB_OFFSET 0
+#define D18F2x8C_TrwtWB_WIDTH 4
+#define D18F2x8C_TrwtWB_MASK 0xf
+#define D18F2x8C_TrwtTO_OFFSET 4
+#define D18F2x8C_TrwtTO_WIDTH 4
+#define D18F2x8C_TrwtTO_MASK 0xf0
+#define D18F2x8C_Reserved_9_8_OFFSET 8
+#define D18F2x8C_Reserved_9_8_WIDTH 2
+#define D18F2x8C_Reserved_9_8_MASK 0x300
+#define D18F2x8C_Twrrd_1_0__OFFSET 10
+#define D18F2x8C_Twrrd_1_0__WIDTH 2
+#define D18F2x8C_Twrrd_1_0__MASK 0xc00
+#define D18F2x8C_Twrwr_1_0__OFFSET 12
+#define D18F2x8C_Twrwr_1_0__WIDTH 2
+#define D18F2x8C_Twrwr_1_0__MASK 0x3000
+#define D18F2x8C_Trdrd_1_0__OFFSET 14
+#define D18F2x8C_Trdrd_1_0__WIDTH 2
+#define D18F2x8C_Trdrd_1_0__MASK 0xc000
+#define D18F2x8C_Tref_OFFSET 16
+#define D18F2x8C_Tref_WIDTH 2
+#define D18F2x8C_Tref_MASK 0x30000
+#define D18F2x8C_DisAutoRefresh_OFFSET 18
+#define D18F2x8C_DisAutoRefresh_WIDTH 1
+#define D18F2x8C_DisAutoRefresh_MASK 0x40000
+#define D18F2x8C_Reserved_19_19_OFFSET 19
+#define D18F2x8C_Reserved_19_19_WIDTH 1
+#define D18F2x8C_Reserved_19_19_MASK 0x80000
+#define D18F2x8C_Trfc0_OFFSET 20
+#define D18F2x8C_Trfc0_WIDTH 3
+#define D18F2x8C_Trfc0_MASK 0x700000
+#define D18F2x8C_Trfc1_OFFSET 23
+#define D18F2x8C_Trfc1_WIDTH 3
+#define D18F2x8C_Trfc1_MASK 0x3800000
+#define D18F2x8C_Reserved_31_26_OFFSET 26
+#define D18F2x8C_Reserved_31_26_WIDTH 6
+#define D18F2x8C_Reserved_31_26_MASK 0xfc000000
+
+/// D18F2x8C
typedef union {
struct { ///<
UINT32 TrwtWB:4 ; ///<
UINT32 Reserved_31_26:6 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x08C_STRUCT;
-
-// **** D18F2x090 Register Definition ****
-// Address
-#define D18F2x090_ADDRESS 0x90
-
-// Type
-#define D18F2x090_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x090_Reserved_0_0_OFFSET 0
-#define D18F2x090_Reserved_0_0_WIDTH 1
-#define D18F2x090_Reserved_0_0_MASK 0x1
-#define D18F2x090_ExitSelfRef_OFFSET 1
-#define D18F2x090_ExitSelfRef_WIDTH 1
-#define D18F2x090_ExitSelfRef_MASK 0x2
-#define D18F2x090_Reserved_16_2_OFFSET 2
-#define D18F2x090_Reserved_16_2_WIDTH 15
-#define D18F2x090_Reserved_16_2_MASK 0x1fffc
-#define D18F2x090_EnterSelfRef_OFFSET 17
-#define D18F2x090_EnterSelfRef_WIDTH 1
-#define D18F2x090_EnterSelfRef_MASK 0x20000
-#define D18F2x090_Reserved_19_18_OFFSET 18
-#define D18F2x090_Reserved_19_18_WIDTH 2
-#define D18F2x090_Reserved_19_18_MASK 0xc0000
-#define D18F2x090_DynPageCloseEn_OFFSET 20
-#define D18F2x090_DynPageCloseEn_WIDTH 1
-#define D18F2x090_DynPageCloseEn_MASK 0x100000
-#define D18F2x090_IdleCycInit_OFFSET 21
-#define D18F2x090_IdleCycInit_WIDTH 2
-#define D18F2x090_IdleCycInit_MASK 0x600000
-#define D18F2x090_ForceAutoPchg_OFFSET 23
-#define D18F2x090_ForceAutoPchg_WIDTH 1
-#define D18F2x090_ForceAutoPchg_MASK 0x800000
-#define D18F2x090_Reserved_24_24_OFFSET 24
-#define D18F2x090_Reserved_24_24_WIDTH 1
-#define D18F2x090_Reserved_24_24_MASK 0x1000000
-#define D18F2x090_EnDispAutoPrecharge_OFFSET 25
-#define D18F2x090_EnDispAutoPrecharge_WIDTH 1
-#define D18F2x090_EnDispAutoPrecharge_MASK 0x2000000
-#define D18F2x090_DbeSkidBufDis_OFFSET 26
-#define D18F2x090_DbeSkidBufDis_WIDTH 1
-#define D18F2x090_DbeSkidBufDis_MASK 0x4000000
-#define D18F2x090_DisDllShutdownSR_OFFSET 27
-#define D18F2x090_DisDllShutdownSR_WIDTH 1
-#define D18F2x090_DisDllShutdownSR_MASK 0x8000000
-#define D18F2x090_Reserved_31_28_OFFSET 28
-#define D18F2x090_Reserved_31_28_WIDTH 4
-#define D18F2x090_Reserved_31_28_MASK 0xf0000000
-
-/// D18F2x090
+} D18F2x8C_STRUCT;
+
+// **** D18F2x90 Register Definition ****
+// Address
+#define D18F2x90_ADDRESS 0x90
+
+// Type
+#define D18F2x90_TYPE TYPE_D18F2
+// Field Data
+#define D18F2x90_Reserved_0_0_OFFSET 0
+#define D18F2x90_Reserved_0_0_WIDTH 1
+#define D18F2x90_Reserved_0_0_MASK 0x1
+#define D18F2x90_ExitSelfRef_OFFSET 1
+#define D18F2x90_ExitSelfRef_WIDTH 1
+#define D18F2x90_ExitSelfRef_MASK 0x2
+#define D18F2x90_Reserved_16_2_OFFSET 2
+#define D18F2x90_Reserved_16_2_WIDTH 15
+#define D18F2x90_Reserved_16_2_MASK 0x1fffc
+#define D18F2x90_EnterSelfRef_OFFSET 17
+#define D18F2x90_EnterSelfRef_WIDTH 1
+#define D18F2x90_EnterSelfRef_MASK 0x20000
+#define D18F2x90_Reserved_19_18_OFFSET 18
+#define D18F2x90_Reserved_19_18_WIDTH 2
+#define D18F2x90_Reserved_19_18_MASK 0xc0000
+#define D18F2x90_DynPageCloseEn_OFFSET 20
+#define D18F2x90_DynPageCloseEn_WIDTH 1
+#define D18F2x90_DynPageCloseEn_MASK 0x100000
+#define D18F2x90_IdleCycInit_OFFSET 21
+#define D18F2x90_IdleCycInit_WIDTH 2
+#define D18F2x90_IdleCycInit_MASK 0x600000
+#define D18F2x90_ForceAutoPchg_OFFSET 23
+#define D18F2x90_ForceAutoPchg_WIDTH 1
+#define D18F2x90_ForceAutoPchg_MASK 0x800000
+#define D18F2x90_Reserved_24_24_OFFSET 24
+#define D18F2x90_Reserved_24_24_WIDTH 1
+#define D18F2x90_Reserved_24_24_MASK 0x1000000
+#define D18F2x90_EnDispAutoPrecharge_OFFSET 25
+#define D18F2x90_EnDispAutoPrecharge_WIDTH 1
+#define D18F2x90_EnDispAutoPrecharge_MASK 0x2000000
+#define D18F2x90_DbeSkidBufDis_OFFSET 26
+#define D18F2x90_DbeSkidBufDis_WIDTH 1
+#define D18F2x90_DbeSkidBufDis_MASK 0x4000000
+#define D18F2x90_DisDllShutdownSR_OFFSET 27
+#define D18F2x90_DisDllShutdownSR_WIDTH 1
+#define D18F2x90_DisDllShutdownSR_MASK 0x8000000
+#define D18F2x90_Reserved_31_28_OFFSET 28
+#define D18F2x90_Reserved_31_28_WIDTH 4
+#define D18F2x90_Reserved_31_28_MASK 0xf0000000
+
+/// D18F2x90
typedef union {
struct { ///<
UINT32 Reserved_0_0:1 ; ///<
UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x090_STRUCT;
+} D18F2x90_STRUCT;
+
+// **** D18F2x94 Register Definition ****
+// Address
+#define D18F2x94_ADDRESS 0x94
+
+// Type
+#define D18F2x94_TYPE TYPE_D18F2
+// Field Data
+#define D18F2x94_MemClkFreq_OFFSET 0
+#define D18F2x94_MemClkFreq_WIDTH 5
+#define D18F2x94_MemClkFreq_MASK 0x1f
+#define D18F2x94_Reserved_6_5_OFFSET 5
+#define D18F2x94_Reserved_6_5_WIDTH 2
+#define D18F2x94_Reserved_6_5_MASK 0x60
+#define D18F2x94_MemClkFreqVal_OFFSET 7
+#define D18F2x94_MemClkFreqVal_WIDTH 1
+#define D18F2x94_MemClkFreqVal_MASK 0x80
+#define D18F2x94_Reserved_9_8_OFFSET 8
+#define D18F2x94_Reserved_9_8_WIDTH 2
+#define D18F2x94_Reserved_9_8_MASK 0x300
+#define D18F2x94_ZqcsInterval_OFFSET 10
+#define D18F2x94_ZqcsInterval_WIDTH 2
+#define D18F2x94_ZqcsInterval_MASK 0xc00
+#define D18F2x94_Reserved_13_12_OFFSET 12
+#define D18F2x94_Reserved_13_12_WIDTH 2
+#define D18F2x94_Reserved_13_12_MASK 0x3000
+#define D18F2x94_DisDramInterface_OFFSET 14
+#define D18F2x94_DisDramInterface_WIDTH 1
+#define D18F2x94_DisDramInterface_MASK 0x4000
+#define D18F2x94_PowerDownEn_OFFSET 15
+#define D18F2x94_PowerDownEn_WIDTH 1
+#define D18F2x94_PowerDownEn_MASK 0x8000
+#define D18F2x94_PowerDownMode_OFFSET 16
+#define D18F2x94_PowerDownMode_WIDTH 1
+#define D18F2x94_PowerDownMode_MASK 0x10000
+#define D18F2x94_Reserved_19_17_OFFSET 17
+#define D18F2x94_Reserved_19_17_WIDTH 3
+#define D18F2x94_Reserved_19_17_MASK 0xe0000
+#define D18F2x94_SlowAccessMode_OFFSET 20
+#define D18F2x94_SlowAccessMode_WIDTH 1
+#define D18F2x94_SlowAccessMode_MASK 0x100000
+#define D18F2x94_Reserved_21_21_OFFSET 21
+#define D18F2x94_Reserved_21_21_WIDTH 1
+#define D18F2x94_Reserved_21_21_MASK 0x200000
+#define D18F2x94_BankSwizzleMode_OFFSET 22
+#define D18F2x94_BankSwizzleMode_WIDTH 1
+#define D18F2x94_BankSwizzleMode_MASK 0x400000
+#define D18F2x94_ProcOdtDis_OFFSET 23
+#define D18F2x94_ProcOdtDis_WIDTH 1
+#define D18F2x94_ProcOdtDis_MASK 0x800000
+#define D18F2x94_DcqBypassMax_OFFSET 24
+#define D18F2x94_DcqBypassMax_WIDTH 4
+#define D18F2x94_DcqBypassMax_MASK 0xf000000
+#define D18F2x94_FourActWindow_OFFSET 28
+#define D18F2x94_FourActWindow_WIDTH 4
+#define D18F2x94_FourActWindow_MASK 0xf0000000
+
+/// D18F2x94
+typedef union {
+ struct { ///<
+ UINT32 MemClkFreq:5 ; ///<
+ UINT32 Reserved_6_5:2 ; ///<
+ UINT32 MemClkFreqVal:1 ; ///<
+ UINT32 Reserved_9_8:2 ; ///<
+ UINT32 ZqcsInterval:2 ; ///<
+ UINT32 Reserved_13_12:3 ; ///<
+ UINT32 DisDramInterface:1 ; ///<
+ UINT32 PowerDownEn:1 ; ///<
+ UINT32 PowerDownMode:1 ; ///<
+ UINT32 Reserved_19_17:3 ; ///<
+ UINT32 SlowAccessMode:1 ; ///<
+ UINT32 Reserved_21_21:1 ; ///<
+ UINT32 BankSwizzleMode:1 ; ///<
+ UINT32 ProcOdtDis:1 ; ///<
+ UINT32 DcqBypassMax:4 ; ///<
+ UINT32 FourActWindow:4 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2x94_STRUCT;
+
+// **** D18F2x98 Register Definition ****
+// Address
+#define D18F2x98_ADDRESS 0x98
+
+// Type
+#define D18F2x98_TYPE TYPE_D18F2
+// Field Data
+#define D18F2x98_DctOffset_OFFSET 0
+#define D18F2x98_DctOffset_WIDTH 30
+#define D18F2x98_DctOffset_MASK 0x3fffffff
+#define D18F2x98_DctAccessWrite_OFFSET 30
+#define D18F2x98_DctAccessWrite_WIDTH 1
+#define D18F2x98_DctAccessWrite_MASK 0x40000000
+#define D18F2x98_DctAccessDone_OFFSET 31
+#define D18F2x98_DctAccessDone_WIDTH 1
+#define D18F2x98_DctAccessDone_MASK 0x80000000
+
+/// D18F2x98
+typedef union {
+ struct { ///<
+ UINT32 DctOffset:30; ///<
+ UINT32 DctAccessWrite:1 ; ///<
+ UINT32 DctAccessDone:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2x98_STRUCT;
// **** D18F2x9C Register Definition ****
// Address
#define D18F2x9C_ADDRESS 0x9c
+// Type
+#define D18F2x9C_TYPE TYPE_D18F2
+// Field Data
+#define D18F2x9C_DctDataPort_OFFSET 0
+#define D18F2x9C_DctDataPort_WIDTH 32
+#define D18F2x9C_DctDataPort_MASK 0xffffffff
+
+/// D18F2x9C
+typedef union {
+ struct { ///<
+ UINT32 DctDataPort:32; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2x9C_STRUCT;
+
+// **** D18F2x09C_x0D0FE00A Register Definition ****
+// Address
+#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A
+
+// Type
+#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C
+// Field Data
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4
+#define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF
+#define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4
+#define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1
+#define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7
+#define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0
+#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12
+#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2
+#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000
+#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14
+#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1
+#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17
+#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000
+
+/// D18F2x09C_x0D0FE00A
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4; ///<
+ UINT32 SkewMemClk:1; ///<
+ UINT32 Reserved_11_5:7; ///<
+ UINT32 CsrPhySrPllPdMode:2; ///<
+ UINT32 SelCsrPllPdMode:1; ///<
+ UINT32 Reserved_31_15:17; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2x09C_x0D0FE00A_STRUCT;
+
// **** D18F2xA0 Register Definition ****
// Address
#define D18F2xA0_ADDRESS 0xa0
UINT32 Value; ///<
} D18F2xAC_STRUCT;
-// **** D18F2xF0 Register Definition ****
+// **** D18F2xB0 Register Definition ****
// Address
-#define D18F2xF0_ADDRESS 0xf0
+#define D18F2xB0_ADDRESS 0xb0
// Type
-#define D18F2xF0_TYPE TYPE_D18F2
+#define D18F2xB0_TYPE TYPE_D18F2
// Field Data
-#define D18F2xF0_DctOffset_OFFSET 0
-#define D18F2xF0_DctOffset_WIDTH 28
-#define D18F2xF0_DctOffset_MASK 0xfffffff
-#define D18F2xF0_Reserved_29_28_OFFSET 28
-#define D18F2xF0_Reserved_29_28_WIDTH 2
-#define D18F2xF0_Reserved_29_28_MASK 0x30000000
-#define D18F2xF0_DctAccessWrite_OFFSET 30
-#define D18F2xF0_DctAccessWrite_WIDTH 1
-#define D18F2xF0_DctAccessWrite_MASK 0x40000000
-#define D18F2xF0_DctAccessDone_OFFSET 31
-#define D18F2xF0_DctAccessDone_WIDTH 1
-#define D18F2xF0_DctAccessDone_MASK 0x80000000
+#define D18F2xB0_TscLow_OFFSET 0
+#define D18F2xB0_TscLow_WIDTH 32
+#define D18F2xB0_TscLow_MASK 0xffffffff
-/// D18F2xF0
+/// D18F2xB0
typedef union {
struct { ///<
- UINT32 DctOffset:28; ///<
- UINT32 Reserved_29_28:2 ; ///<
- UINT32 DctAccessWrite:1 ; ///<
- UINT32 DctAccessDone:1 ; ///<
+ UINT32 TscLow:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2xF0_STRUCT;
+} D18F2xB0_STRUCT;
-// **** D18F2xF4 Register Definition ****
+// **** D18F2xB4 Register Definition ****
// Address
-#define D18F2xF4_ADDRESS 0xf4
+#define D18F2xB4_ADDRESS 0xb4
// Type
-#define D18F2xF4_TYPE TYPE_D18F2
+#define D18F2xB4_TYPE TYPE_D18F2
// Field Data
-#define D18F2xF4_DctExtDataPort_OFFSET 0
-#define D18F2xF4_DctExtDataPort_WIDTH 32
-#define D18F2xF4_DctExtDataPort_MASK 0xffffffff
+#define D18F2xB4_TscHigh_OFFSET 0
+#define D18F2xB4_TscHigh_WIDTH 32
+#define D18F2xB4_TscHigh_MASK 0xffffffff
-/// D18F2xF4
+/// D18F2xB4
typedef union {
struct { ///<
- UINT32 DctExtDataPort:32; ///<
+ UINT32 TscHigh:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2xF4_STRUCT;
+} D18F2xB4_STRUCT;
-// **** D18F2x110 Register Definition ****
+// **** D18F2xB8 Register Definition ****
// Address
-#define D18F2x110_ADDRESS 0x110
+#define D18F2xB8_ADDRESS 0xb8
// Type
-#define D18F2x110_TYPE TYPE_D18F2
+#define D18F2xB8_TYPE TYPE_D18F2
// Field Data
-#define D18F2x110_Reserved_2_0_OFFSET 0
-#define D18F2x110_Reserved_2_0_WIDTH 3
-#define D18F2x110_Reserved_2_0_MASK 0x7
-#define D18F2x110_MemClrInit_OFFSET 3
-#define D18F2x110_MemClrInit_WIDTH 1
-#define D18F2x110_MemClrInit_MASK 0x8
-#define D18F2x110_Reserved_7_4_OFFSET 4
-#define D18F2x110_Reserved_7_4_WIDTH 4
-#define D18F2x110_Reserved_7_4_MASK 0xf0
-#define D18F2x110_DramEnable_OFFSET 8
-#define D18F2x110_DramEnable_WIDTH 1
-#define D18F2x110_DramEnable_MASK 0x100
-#define D18F2x110_MemClrBusy_OFFSET 9
-#define D18F2x110_MemClrBusy_WIDTH 1
-#define D18F2x110_MemClrBusy_MASK 0x200
-#define D18F2x110_MemCleared_OFFSET 10
-#define D18F2x110_MemCleared_WIDTH 1
-#define D18F2x110_MemCleared_MASK 0x400
-#define D18F2x110_Reserved_31_11_OFFSET 11
-#define D18F2x110_Reserved_31_11_WIDTH 21
-#define D18F2x110_Reserved_31_11_MASK 0xfffff800
+#define D18F2xB8_TrcBufDramBase_35_24__OFFSET 0
+#define D18F2xB8_TrcBufDramBase_35_24__WIDTH 12
+#define D18F2xB8_TrcBufDramBase_35_24__MASK 0xfff
+#define D18F2xB8_TrcBufDramBase_39_36__OFFSET 12
+#define D18F2xB8_TrcBufDramBase_39_36__WIDTH 4
+#define D18F2xB8_TrcBufDramBase_39_36__MASK 0xf000
+#define D18F2xB8_TrcBufDramLimit_35_24__OFFSET 16
+#define D18F2xB8_TrcBufDramLimit_35_24__WIDTH 12
+#define D18F2xB8_TrcBufDramLimit_35_24__MASK 0xfff0000
+#define D18F2xB8_TrcBufDramLimit_39_36__OFFSET 28
+#define D18F2xB8_TrcBufDramLimit_39_36__WIDTH 4
+#define D18F2xB8_TrcBufDramLimit_39_36__MASK 0xf0000000
-/// D18F2x110
+/// D18F2xB8
typedef union {
struct { ///<
- UINT32 Reserved_2_0:3 ; ///<
- UINT32 MemClrInit:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 DramEnable:1 ; ///<
- UINT32 MemClrBusy:1 ; ///<
- UINT32 MemCleared:1 ; ///<
- UINT32 Reserved_31_11:21; ///<
+ UINT32 TrcBufDramBase_35_24_:12; ///<
+ UINT32 TrcBufDramBase_39_36_:4 ; ///<
+ UINT32 TrcBufDramLimit_35_24_:12; ///<
+ UINT32 TrcBufDramLimit_39_36_:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x110_STRUCT;
+} D18F2xB8_STRUCT;
-// **** D18F2x114 Register Definition ****
+// **** D18F2xBC Register Definition ****
// Address
-#define D18F2x114_ADDRESS 0x114
+#define D18F2xBC_ADDRESS 0xbc
// Type
-#define D18F2x114_TYPE TYPE_D18F2
+#define D18F2xBC_TYPE TYPE_D18F2
// Field Data
-#define D18F2x114_Reserved_8_0_OFFSET 0
-#define D18F2x114_Reserved_8_0_WIDTH 9
-#define D18F2x114_Reserved_8_0_MASK 0x1ff
-#define D18F2x114_DctSelBankSwap_OFFSET 9
-#define D18F2x114_DctSelBankSwap_WIDTH 1
-#define D18F2x114_DctSelBankSwap_MASK 0x200
-#define D18F2x114_Reserved_31_10_OFFSET 10
-#define D18F2x114_Reserved_31_10_WIDTH 22
-#define D18F2x114_Reserved_31_10_MASK 0xfffffc00
+#define D18F2xBC_TrcBufAdrPtr_35_6__OFFSET 0
+#define D18F2xBC_TrcBufAdrPtr_35_6__WIDTH 30
+#define D18F2xBC_TrcBufAdrPtr_35_6__MASK 0x3fffffff
+#define D18F2xBC_TrcBufAdrPtr_37_36__OFFSET 30
+#define D18F2xBC_TrcBufAdrPtr_37_36__WIDTH 2
+#define D18F2xBC_TrcBufAdrPtr_37_36__MASK 0xc0000000
-/// D18F2x114
+/// D18F2xBC
typedef union {
struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 DctSelBankSwap:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
+ UINT32 TrcBufAdrPtr_35_6_:30; ///<
+ UINT32 TrcBufAdrPtr_37_36_:2 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x114_STRUCT;
+} D18F2xBC_STRUCT;
-// **** D18F3x64 Register Definition ****
+// **** D18F2xC0 Register Definition ****
// Address
-#define D18F3x64_ADDRESS 0x64
+#define D18F2xC0_ADDRESS 0xc0
// Type
-#define D18F3x64_TYPE TYPE_D18F3
+#define D18F2xC0_TYPE TYPE_D18F2
// Field Data
-#define D18F3x64_HtcEn_OFFSET 0
-#define D18F3x64_HtcEn_WIDTH 1
-#define D18F3x64_HtcEn_MASK 0x1
-#define D18F3x64_Reserved_3_1_OFFSET 1
-#define D18F3x64_Reserved_3_1_WIDTH 3
-#define D18F3x64_Reserved_3_1_MASK 0xe
-#define D18F3x64_HtcAct_OFFSET 4
-#define D18F3x64_HtcAct_WIDTH 1
-#define D18F3x64_HtcAct_MASK 0x10
-#define D18F3x64_HtcActSts_OFFSET 5
-#define D18F3x64_HtcActSts_WIDTH 1
-#define D18F3x64_HtcActSts_MASK 0x20
-#define D18F3x64_PslApicHiEn_OFFSET 6
-#define D18F3x64_PslApicHiEn_WIDTH 1
-#define D18F3x64_PslApicHiEn_MASK 0x40
-#define D18F3x64_PslApicLoEn_OFFSET 7
-#define D18F3x64_PslApicLoEn_WIDTH 1
-#define D18F3x64_PslApicLoEn_MASK 0x80
-#define D18F3x64_Reserved_15_8_OFFSET 8
-#define D18F3x64_Reserved_15_8_WIDTH 8
-#define D18F3x64_Reserved_15_8_MASK 0xff00
-#define D18F3x64_HtcTmpLmt_OFFSET 16
-#define D18F3x64_HtcTmpLmt_WIDTH 7
-#define D18F3x64_HtcTmpLmt_MASK 0x7f0000
-#define D18F3x64_HtcSlewSel_OFFSET 23
-#define D18F3x64_HtcSlewSel_WIDTH 1
-#define D18F3x64_HtcSlewSel_MASK 0x800000
-#define D18F3x64_HtcHystLmt_OFFSET 24
-#define D18F3x64_HtcHystLmt_WIDTH 4
-#define D18F3x64_HtcHystLmt_MASK 0xf000000
-#define D18F3x64_HtcPstateLimit_OFFSET 28
-#define D18F3x64_HtcPstateLimit_WIDTH 3
-#define D18F3x64_HtcPstateLimit_MASK 0x70000000
-#define D18F3x64_HtcLock_OFFSET 31
-#define D18F3x64_HtcLock_WIDTH 1
-#define D18F3x64_HtcLock_MASK 0x80000000
+#define D18F2xC0_TraceModeEn_OFFSET 0
+#define D18F2xC0_TraceModeEn_WIDTH 1
+#define D18F2xC0_TraceModeEn_MASK 0x1
+#define D18F2xC0_TcbModeEn_OFFSET 1
+#define D18F2xC0_TcbModeEn_WIDTH 1
+#define D18F2xC0_TcbModeEn_MASK 0x2
+#define D18F2xC0_Reserved_3_2_OFFSET 2
+#define D18F2xC0_Reserved_3_2_WIDTH 2
+#define D18F2xC0_Reserved_3_2_MASK 0xc
+#define D18F2xC0_ncHTEn0_OFFSET 4
+#define D18F2xC0_ncHTEn0_WIDTH 1
+#define D18F2xC0_ncHTEn0_MASK 0x10
+#define D18F2xC0_ncHTEn1_OFFSET 5
+#define D18F2xC0_ncHTEn1_WIDTH 1
+#define D18F2xC0_ncHTEn1_MASK 0x20
+#define D18F2xC0_Reserved_11_6_OFFSET 6
+#define D18F2xC0_Reserved_11_6_WIDTH 6
+#define D18F2xC0_Reserved_11_6_MASK 0xfc0
+#define D18F2xC0_FlushTcb_OFFSET 12
+#define D18F2xC0_FlushTcb_WIDTH 1
+#define D18F2xC0_FlushTcb_MASK 0x1000
+#define D18F2xC0_Reserved_14_13_OFFSET 13
+#define D18F2xC0_Reserved_14_13_WIDTH 2
+#define D18F2xC0_Reserved_14_13_MASK 0x6000
+#define D18F2xC0_TraceCmdMtchReq_OFFSET 15
+#define D18F2xC0_TraceCmdMtchReq_WIDTH 1
+#define D18F2xC0_TraceCmdMtchReq_MASK 0x8000
+#define D18F2xC0_Reserved_17_16_OFFSET 16
+#define D18F2xC0_Reserved_17_16_WIDTH 2
+#define D18F2xC0_Reserved_17_16_MASK 0x30000
+#define D18F2xC0_MultiLevelSingleEvent_OFFSET 18
+#define D18F2xC0_MultiLevelSingleEvent_WIDTH 1
+#define D18F2xC0_MultiLevelSingleEvent_MASK 0x40000
+#define D18F2xC0_MultiLevelMultiEvent_OFFSET 19
+#define D18F2xC0_MultiLevelMultiEvent_WIDTH 1
+#define D18F2xC0_MultiLevelMultiEvent_MASK 0x80000
+#define D18F2xC0_Reserved_20_20_OFFSET 20
+#define D18F2xC0_Reserved_20_20_WIDTH 1
+#define D18F2xC0_Reserved_20_20_MASK 0x100000
+#define D18F2xC0_TraceSrcDstAndEn_OFFSET 21
+#define D18F2xC0_TraceSrcDstAndEn_WIDTH 1
+#define D18F2xC0_TraceSrcDstAndEn_MASK 0x200000
+#define D18F2xC0_TraceFlushOnDbReq_OFFSET 22
+#define D18F2xC0_TraceFlushOnDbReq_WIDTH 1
+#define D18F2xC0_TraceFlushOnDbReq_MASK 0x400000
+#define D18F2xC0_TraceOneShotEn_OFFSET 23
+#define D18F2xC0_TraceOneShotEn_WIDTH 1
+#define D18F2xC0_TraceOneShotEn_MASK 0x800000
+#define D18F2xC0_Reserved_31_24_OFFSET 24
+#define D18F2xC0_Reserved_31_24_WIDTH 8
+#define D18F2xC0_Reserved_31_24_MASK 0xff000000
+
+/// D18F2xC0
+typedef union {
+ struct { ///<
+ UINT32 TraceModeEn:1 ; ///<
+ UINT32 TcbModeEn:1 ; ///<
+ UINT32 Reserved_3_2:2 ; ///<
+ UINT32 ncHTEn0:1 ; ///<
+ UINT32 ncHTEn1:1 ; ///<
+ UINT32 Reserved_11_6:6 ; ///<
+ UINT32 FlushTcb:1 ; ///<
+ UINT32 Reserved_14_13:2 ; ///<
+ UINT32 TraceCmdMtchReq:1 ; ///<
+ UINT32 Reserved_17_16:2 ; ///<
+ UINT32 MultiLevelSingleEvent:1 ; ///<
+ UINT32 MultiLevelMultiEvent:1 ; ///<
+ UINT32 Reserved_20_20:1 ; ///<
+ UINT32 TraceSrcDstAndEn:1 ; ///<
+ UINT32 TraceFlushOnDbReq:1 ; ///<
+ UINT32 TraceOneShotEn:1 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2xC0_STRUCT;
+
+// **** D18F2xC4 Register Definition ****
+// Address
+#define D18F2xC4_ADDRESS 0xc4
+
+// Type
+#define D18F2xC4_TYPE TYPE_D18F2
+// Field Data
+#define D18F2xC4_StartCmd0_OFFSET 0
+#define D18F2xC4_StartCmd0_WIDTH 1
+#define D18F2xC4_StartCmd0_MASK 0x1
+#define D18F2xC4_StartCmd1_OFFSET 1
+#define D18F2xC4_StartCmd1_WIDTH 1
+#define D18F2xC4_StartCmd1_MASK 0x2
+#define D18F2xC4_Reserved_21_2_OFFSET 2
+#define D18F2xC4_Reserved_21_2_WIDTH 20
+#define D18F2xC4_Reserved_21_2_MASK 0x3ffffc
+#define D18F2xC4_StartDbRdy_OFFSET 22
+#define D18F2xC4_StartDbRdy_WIDTH 1
+#define D18F2xC4_StartDbRdy_MASK 0x400000
+#define D18F2xC4_StartDbReq_OFFSET 23
+#define D18F2xC4_StartDbReq_WIDTH 1
+#define D18F2xC4_StartDbReq_MASK 0x800000
+#define D18F2xC4_StartPerfMon0_OFFSET 24
+#define D18F2xC4_StartPerfMon0_WIDTH 1
+#define D18F2xC4_StartPerfMon0_MASK 0x1000000
+#define D18F2xC4_StartPerfMon1_OFFSET 25
+#define D18F2xC4_StartPerfMon1_WIDTH 1
+#define D18F2xC4_StartPerfMon1_MASK 0x2000000
+#define D18F2xC4_StartPerfMon2_OFFSET 26
+#define D18F2xC4_StartPerfMon2_WIDTH 1
+#define D18F2xC4_StartPerfMon2_MASK 0x4000000
+#define D18F2xC4_StartPerfMon3_OFFSET 27
+#define D18F2xC4_StartPerfMon3_WIDTH 1
+#define D18F2xC4_StartPerfMon3_MASK 0x8000000
+#define D18F2xC4_StartMCE_OFFSET 28
+#define D18F2xC4_StartMCE_WIDTH 1
+#define D18F2xC4_StartMCE_MASK 0x10000000
+#define D18F2xC4_Reserved_29_29_OFFSET 29
+#define D18F2xC4_Reserved_29_29_WIDTH 1
+#define D18F2xC4_Reserved_29_29_MASK 0x20000000
+#define D18F2xC4_StartTSC_OFFSET 30
+#define D18F2xC4_StartTSC_WIDTH 1
+#define D18F2xC4_StartTSC_MASK 0x40000000
+#define D18F2xC4_StartNow_OFFSET 31
+#define D18F2xC4_StartNow_WIDTH 1
+#define D18F2xC4_StartNow_MASK 0x80000000
+
+/// D18F2xC4
+typedef union {
+ struct { ///<
+ UINT32 StartCmd0:1 ; ///<
+ UINT32 StartCmd1:1 ; ///<
+ UINT32 Reserved_21_2:20; ///<
+ UINT32 StartDbRdy:1 ; ///<
+ UINT32 StartDbReq:1 ; ///<
+ UINT32 StartPerfMon0:1 ; ///<
+ UINT32 StartPerfMon1:1 ; ///<
+ UINT32 StartPerfMon2:1 ; ///<
+ UINT32 StartPerfMon3:1 ; ///<
+ UINT32 StartMCE:1 ; ///<
+ UINT32 Reserved_29_29:1 ; ///<
+ UINT32 StartTSC:1 ; ///<
+ UINT32 StartNow:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2xC4_STRUCT;
+
+// **** D18F2xC8 Register Definition ****
+// Address
+#define D18F2xC8_ADDRESS 0xc8
+
+// Type
+#define D18F2xC8_TYPE TYPE_D18F2
+// Field Data
+#define D18F2xC8_StopCmd0_OFFSET 0
+#define D18F2xC8_StopCmd0_WIDTH 1
+#define D18F2xC8_StopCmd0_MASK 0x1
+#define D18F2xC8_StopCmd1_OFFSET 1
+#define D18F2xC8_StopCmd1_WIDTH 1
+#define D18F2xC8_StopCmd1_MASK 0x2
+#define D18F2xC8_Reserved_21_2_OFFSET 2
+#define D18F2xC8_Reserved_21_2_WIDTH 20
+#define D18F2xC8_Reserved_21_2_MASK 0x3ffffc
+#define D18F2xC8_StopDbRdy_OFFSET 22
+#define D18F2xC8_StopDbRdy_WIDTH 1
+#define D18F2xC8_StopDbRdy_MASK 0x400000
+#define D18F2xC8_StopDbReq_OFFSET 23
+#define D18F2xC8_StopDbReq_WIDTH 1
+#define D18F2xC8_StopDbReq_MASK 0x800000
+#define D18F2xC8_StopPerfMon0_OFFSET 24
+#define D18F2xC8_StopPerfMon0_WIDTH 1
+#define D18F2xC8_StopPerfMon0_MASK 0x1000000
+#define D18F2xC8_StopPerfMon1_OFFSET 25
+#define D18F2xC8_StopPerfMon1_WIDTH 1
+#define D18F2xC8_StopPerfMon1_MASK 0x2000000
+#define D18F2xC8_StopPerfMon2_OFFSET 26
+#define D18F2xC8_StopPerfMon2_WIDTH 1
+#define D18F2xC8_StopPerfMon2_MASK 0x4000000
+#define D18F2xC8_StopPerfMon3_OFFSET 27
+#define D18F2xC8_StopPerfMon3_WIDTH 1
+#define D18F2xC8_StopPerfMon3_MASK 0x8000000
+#define D18F2xC8_StopMCE_OFFSET 28
+#define D18F2xC8_StopMCE_WIDTH 1
+#define D18F2xC8_StopMCE_MASK 0x10000000
+#define D18F2xC8_StopTrcBufFull_OFFSET 29
+#define D18F2xC8_StopTrcBufFull_WIDTH 1
+#define D18F2xC8_StopTrcBufFull_MASK 0x20000000
+#define D18F2xC8_StopTSC_OFFSET 30
+#define D18F2xC8_StopTSC_WIDTH 1
+#define D18F2xC8_StopTSC_MASK 0x40000000
+#define D18F2xC8_StopNow_OFFSET 31
+#define D18F2xC8_StopNow_WIDTH 1
+#define D18F2xC8_StopNow_MASK 0x80000000
+
+/// D18F2xC8
+typedef union {
+ struct { ///<
+ UINT32 StopCmd0:1 ; ///<
+ UINT32 StopCmd1:1 ; ///<
+ UINT32 Reserved_21_2:20; ///<
+ UINT32 StopDbRdy:1 ; ///<
+ UINT32 StopDbReq:1 ; ///<
+ UINT32 StopPerfMon0:1 ; ///<
+ UINT32 StopPerfMon1:1 ; ///<
+ UINT32 StopPerfMon2:1 ; ///<
+ UINT32 StopPerfMon3:1 ; ///<
+ UINT32 StopMCE:1 ; ///<
+ UINT32 StopTrcBufFull:1 ; ///<
+ UINT32 StopTSC:1 ; ///<
+ UINT32 StopNow:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2xC8_STRUCT;
+
+// **** D18F2xCC Register Definition ****
+// Address
+#define D18F2xCC_ADDRESS 0xcc
+
+// Type
+#define D18F2xCC_TYPE TYPE_D18F2
+// Field Data
+#define D18F2xCC_TrcCmd0_OFFSET 0
+#define D18F2xCC_TrcCmd0_WIDTH 1
+#define D18F2xCC_TrcCmd0_MASK 0x1
+#define D18F2xCC_TrcCmd1_OFFSET 1
+#define D18F2xCC_TrcCmd1_WIDTH 1
+#define D18F2xCC_TrcCmd1_MASK 0x2
+#define D18F2xCC_Reserved_3_2_OFFSET 2
+#define D18F2xCC_Reserved_3_2_WIDTH 2
+#define D18F2xCC_Reserved_3_2_MASK 0xc
+#define D18F2xCC_TrcRsp0_OFFSET 4
+#define D18F2xCC_TrcRsp0_WIDTH 1
+#define D18F2xCC_TrcRsp0_MASK 0x10
+#define D18F2xCC_TrcRsp1_OFFSET 5
+#define D18F2xCC_TrcRsp1_WIDTH 1
+#define D18F2xCC_TrcRsp1_MASK 0x20
+#define D18F2xCC_Reserved_11_6_OFFSET 6
+#define D18F2xCC_Reserved_11_6_WIDTH 6
+#define D18F2xCC_Reserved_11_6_MASK 0xfc0
+#define D18F2xCC_TrcDat0_OFFSET 12
+#define D18F2xCC_TrcDat0_WIDTH 1
+#define D18F2xCC_TrcDat0_MASK 0x1000
+#define D18F2xCC_TrcDat1_OFFSET 13
+#define D18F2xCC_TrcDat1_WIDTH 1
+#define D18F2xCC_TrcDat1_MASK 0x2000
+#define D18F2xCC_MultiDatXbarSel_OFFSET 14
+#define D18F2xCC_MultiDatXbarSel_WIDTH 1
+#define D18F2xCC_MultiDatXbarSel_MASK 0x4000
+#define D18F2xCC_TrcCmdSrcPtr_OFFSET 15
+#define D18F2xCC_TrcCmdSrcPtr_WIDTH 7
+#define D18F2xCC_TrcCmdSrcPtr_MASK 0x3f8000
+#define D18F2xCC_MultiTscCapture_OFFSET 22
+#define D18F2xCC_MultiTscCapture_WIDTH 1
+#define D18F2xCC_MultiTscCapture_MASK 0x400000
+#define D18F2xCC_TscBase_OFFSET 23
+#define D18F2xCC_TscBase_WIDTH 1
+#define D18F2xCC_TscBase_MASK 0x800000
+#define D18F2xCC_TrcCmdDstPtr_OFFSET 24
+#define D18F2xCC_TrcCmdDstPtr_WIDTH 6
+#define D18F2xCC_TrcCmdDstPtr_MASK 0x3f000000
+#define D18F2xCC_DisTscCapture_OFFSET 30
+#define D18F2xCC_DisTscCapture_WIDTH 1
+#define D18F2xCC_DisTscCapture_MASK 0x40000000
+#define D18F2xCC_TrcDatSrcDst_OFFSET 31
+#define D18F2xCC_TrcDatSrcDst_WIDTH 1
+#define D18F2xCC_TrcDatSrcDst_MASK 0x80000000
+
+/// D18F2xCC
+typedef union {
+ struct { ///<
+ UINT32 TrcCmd0:1 ; ///<
+ UINT32 TrcCmd1:1 ; ///<
+ UINT32 Reserved_3_2:2 ; ///<
+ UINT32 TrcRsp0:1 ; ///<
+ UINT32 TrcRsp1:1 ; ///<
+ UINT32 Reserved_11_6:6 ; ///<
+ UINT32 TrcDat0:1 ; ///<
+ UINT32 TrcDat1:1 ; ///<
+ UINT32 MultiDatXbarSel:1 ; ///<
+ UINT32 TrcCmdSrcPtr:7 ; ///<
+ UINT32 MultiTscCapture:1 ; ///<
+ UINT32 TscBase:1 ; ///<
+ UINT32 TrcCmdDstPtr:6 ; ///<
+ UINT32 DisTscCapture:1 ; ///<
+ UINT32 TrcDatSrcDst:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F2xCC_STRUCT;
-/// D18F3x64
+// **** D18F2xD0 Register Definition ****
+// Address
+#define D18F2xD0_ADDRESS 0xd0
+
+// Type
+#define D18F2xD0_TYPE TYPE_D18F2
+// Field Data
+#define D18F2xD0_HTCmdLow_OFFSET 0
+#define D18F2xD0_HTCmdLow_WIDTH 32
+#define D18F2xD0_HTCmdLow_MASK 0xffffffff
+
+/// D18F2xD0
typedef union {
struct { ///<
- UINT32 HtcEn:1 ; ///<
- UINT32 Reserved_3_1:3 ; ///<
- UINT32 HtcAct:1 ; ///<
- UINT32 HtcActSts:1 ; ///<
- UINT32 PslApicHiEn:1 ; ///<
- UINT32 PslApicLoEn:1 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 HtcTmpLmt:7 ; ///<
- UINT32 HtcSlewSel:1 ; ///<
- UINT32 HtcHystLmt:4 ; ///<
- UINT32 HtcPstateLimit:3 ; ///<
- UINT32 HtcLock:1 ; ///<
+ UINT32 HTCmdLow:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3x64_STRUCT;
+} D18F2xD0_STRUCT;
-// **** D18F3x6C Register Definition ****
+// **** D18F2xD4 Register Definition ****
// Address
-#define D18F3x6C_ADDRESS 0x6c
+#define D18F2xD4_ADDRESS 0xd4
// Type
-#define D18F3x6C_TYPE TYPE_D18F3
+#define D18F2xD4_TYPE TYPE_D18F2
// Field Data
-#define D18F3x6C_UpLoPreqDBC_OFFSET 0
-#define D18F3x6C_UpLoPreqDBC_WIDTH 4
-#define D18F3x6C_UpLoPreqDBC_MASK 0xf
-#define D18F3x6C_UpLoNpreqDBC_OFFSET 4
-#define D18F3x6C_UpLoNpreqDBC_WIDTH 4
-#define D18F3x6C_UpLoNpreqDBC_MASK 0xf0
-#define D18F3x6C_UpLoRespDBC_OFFSET 8
-#define D18F3x6C_UpLoRespDBC_WIDTH 4
-#define D18F3x6C_UpLoRespDBC_MASK 0xf00
-#define D18F3x6C_Reserved_15_12_OFFSET 12
-#define D18F3x6C_Reserved_15_12_WIDTH 4
-#define D18F3x6C_Reserved_15_12_MASK 0xf000
-#define D18F3x6C_UpHiPreqDBC_OFFSET 16
-#define D18F3x6C_UpHiPreqDBC_WIDTH 4
-#define D18F3x6C_UpHiPreqDBC_MASK 0xf0000
-#define D18F3x6C_UpHiNpreqDBC_OFFSET 20
-#define D18F3x6C_UpHiNpreqDBC_WIDTH 4
-#define D18F3x6C_UpHiNpreqDBC_MASK 0xf00000
-#define D18F3x6C_Reserved_31_24_OFFSET 24
-#define D18F3x6C_Reserved_31_24_WIDTH 8
-#define D18F3x6C_Reserved_31_24_MASK 0xff000000
+#define D18F2xD4_HTCmdHigh_OFFSET 0
+#define D18F2xD4_HTCmdHigh_WIDTH 32
+#define D18F2xD4_HTCmdHigh_MASK 0xffffffff
-/// D18F3x6C
+/// D18F2xD4
typedef union {
struct { ///<
- UINT32 UpLoPreqDBC:4 ; ///<
- UINT32 UpLoNpreqDBC:4 ; ///<
- UINT32 UpLoRespDBC:4 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 UpHiPreqDBC:4 ; ///<
- UINT32 UpHiNpreqDBC:4 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
+ UINT32 HTCmdHigh:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3x6C_STRUCT;
+} D18F2xD4_STRUCT;
-// **** D18F3x74 Register Definition ****
+// **** D18F2xD8 Register Definition ****
// Address
-#define D18F3x74_ADDRESS 0x74
+#define D18F2xD8_ADDRESS 0xd8
// Type
-#define D18F3x74_TYPE TYPE_D18F3
+#define D18F2xD8_TYPE TYPE_D18F2
// Field Data
-#define D18F3x74_UpLoPreqCBC_OFFSET 0
-#define D18F3x74_UpLoPreqCBC_WIDTH 4
-#define D18F3x74_UpLoPreqCBC_MASK 0xf
-#define D18F3x74_UpLoNpreqCBC_OFFSET 4
-#define D18F3x74_UpLoNpreqCBC_WIDTH 4
-#define D18F3x74_UpLoNpreqCBC_MASK 0xf0
-#define D18F3x74_UpLoRespCBC_OFFSET 8
-#define D18F3x74_UpLoRespCBC_WIDTH 4
-#define D18F3x74_UpLoRespCBC_MASK 0xf00
-#define D18F3x74_Reserved_15_12_OFFSET 12
-#define D18F3x74_Reserved_15_12_WIDTH 4
-#define D18F3x74_Reserved_15_12_MASK 0xf000
-#define D18F3x74_UpHiPreqCBC_OFFSET 16
-#define D18F3x74_UpHiPreqCBC_WIDTH 4
-#define D18F3x74_UpHiPreqCBC_MASK 0xf0000
-#define D18F3x74_UpHiNpreqCBC_OFFSET 20
-#define D18F3x74_UpHiNpreqCBC_WIDTH 4
-#define D18F3x74_UpHiNpreqCBC_MASK 0xf00000
-#define D18F3x74_Reserved_31_24_OFFSET 24
-#define D18F3x74_Reserved_31_24_WIDTH 8
-#define D18F3x74_Reserved_31_24_MASK 0xff000000
+#define D18F2xD8_HTMaskLow_OFFSET 0
+#define D18F2xD8_HTMaskLow_WIDTH 32
+#define D18F2xD8_HTMaskLow_MASK 0xffffffff
-/// D18F3x74
+/// D18F2xD8
typedef union {
struct { ///<
- UINT32 UpLoPreqCBC:4 ; ///<
- UINT32 UpLoNpreqCBC:4 ; ///<
- UINT32 UpLoRespCBC:4 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 UpHiPreqCBC:4 ; ///<
- UINT32 UpHiNpreqCBC:4 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
+ UINT32 HTMaskLow:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3x74_STRUCT;
+} D18F2xD8_STRUCT;
-// **** D18F3x7C Register Definition ****
+// **** D18F2xDC Register Definition ****
// Address
-#define D18F3x7C_ADDRESS 0x7c
+#define D18F2xDC_ADDRESS 0xdc
// Type
-#define D18F3x7C_TYPE TYPE_D18F3
+#define D18F2xDC_TYPE TYPE_D18F2
// Field Data
-#define D18F3x7C_CpuBC_OFFSET 0
-#define D18F3x7C_CpuBC_WIDTH 6
-#define D18F3x7C_CpuBC_MASK 0x3f
-#define D18F3x7C_Reserved_7_6_OFFSET 6
-#define D18F3x7C_Reserved_7_6_WIDTH 2
-#define D18F3x7C_Reserved_7_6_MASK 0xc0
-#define D18F3x7C_LoPriPBC_OFFSET 8
-#define D18F3x7C_LoPriPBC_WIDTH 6
-#define D18F3x7C_LoPriPBC_MASK 0x3f00
-#define D18F3x7C_Reserved_15_14_OFFSET 14
-#define D18F3x7C_Reserved_15_14_WIDTH 2
-#define D18F3x7C_Reserved_15_14_MASK 0xc000
-#define D18F3x7C_LoPriNPBC_OFFSET 16
-#define D18F3x7C_LoPriNPBC_WIDTH 6
-#define D18F3x7C_LoPriNPBC_MASK 0x3f0000
-#define D18F3x7C_Reserved_23_22_OFFSET 22
-#define D18F3x7C_Reserved_23_22_WIDTH 2
-#define D18F3x7C_Reserved_23_22_MASK 0xc00000
-#define D18F3x7C_FreePoolBC_OFFSET 24
-#define D18F3x7C_FreePoolBC_WIDTH 6
-#define D18F3x7C_FreePoolBC_MASK 0x3f000000
-#define D18F3x7C_Reserved_31_30_OFFSET 30
-#define D18F3x7C_Reserved_31_30_WIDTH 2
-#define D18F3x7C_Reserved_31_30_MASK 0xc0000000
+#define D18F2xDC_HTMaskHigh_OFFSET 0
+#define D18F2xDC_HTMaskHigh_WIDTH 32
+#define D18F2xDC_HTMaskHigh_MASK 0xffffffff
-/// D18F3x7C
+/// D18F2xDC
typedef union {
struct { ///<
- UINT32 CpuBC:6 ; ///<
- UINT32 Reserved_7_6:2 ; ///<
- UINT32 LoPriPBC:6 ; ///<
- UINT32 Reserved_15_14:2 ; ///<
- UINT32 LoPriNPBC:6 ; ///<
- UINT32 Reserved_23_22:2 ; ///<
- UINT32 FreePoolBC:6 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
+ UINT32 HTMaskHigh:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3x7C_STRUCT;
+} D18F2xDC_STRUCT;
-// **** D18F3xD8 Register Definition ****
+// **** D18F2xE0 Register Definition ****
// Address
-#define D18F3xD8_ADDRESS 0xd8
+#define D18F2xE0_ADDRESS 0xe0
// Type
-#define D18F3xD8_TYPE TYPE_D18F3
+#define D18F2xE0_TYPE TYPE_D18F2
// Field Data
-#define D18F3xD8_Reserved_3_0_OFFSET 0
-#define D18F3xD8_Reserved_3_0_WIDTH 4
-#define D18F3xD8_Reserved_3_0_MASK 0xf
-#define D18F3xD8_VSRampSlamTime_OFFSET 4
-#define D18F3xD8_VSRampSlamTime_WIDTH 3
-#define D18F3xD8_VSRampSlamTime_MASK 0x70
-#define D18F3xD8_ExtndTriDly_OFFSET 7
-#define D18F3xD8_ExtndTriDly_WIDTH 5
-#define D18F3xD8_ExtndTriDly_MASK 0xf80
-#define D18F3xD8_Reserved_31_12_OFFSET 12
-#define D18F3xD8_Reserved_31_12_WIDTH 20
-#define D18F3xD8_Reserved_31_12_MASK 0xfffff000
+#define D18F2xE0_HTCmdLow_OFFSET 0
+#define D18F2xE0_HTCmdLow_WIDTH 32
+#define D18F2xE0_HTCmdLow_MASK 0xffffffff
-/// D18F3xD8
+/// D18F2xE0
typedef union {
struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 VSRampSlamTime:3 ; ///<
- UINT32 ExtndTriDly:5 ; ///<
- UINT32 Reserved_31_12:20; ///<
+ UINT32 HTCmdLow:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3xD8_STRUCT;
+} D18F2xE0_STRUCT;
-// **** D18F3xDC Register Definition ****
+// **** D18F2xE4 Register Definition ****
// Address
-#define D18F3xDC_ADDRESS 0xdc
+#define D18F2xE4_ADDRESS 0xe4
// Type
-#define D18F3xDC_TYPE TYPE_D18F3
+#define D18F2xE4_TYPE TYPE_D18F2
// Field Data
-#define D18F3xDC_Reserved_7_0_OFFSET 0
-#define D18F3xDC_Reserved_7_0_WIDTH 8
-#define D18F3xDC_Reserved_7_0_MASK 0xff
-#define D18F3xDC_PstateMaxVal_OFFSET 8
-#define D18F3xDC_PstateMaxVal_WIDTH 3
-#define D18F3xDC_PstateMaxVal_MASK 0x700
-#define D18F3xDC_Reserved_11_11_OFFSET 11
-#define D18F3xDC_Reserved_11_11_WIDTH 1
-#define D18F3xDC_Reserved_11_11_MASK 0x800
-#define D18F3xDC_NbPs0Vid_OFFSET 12
-#define D18F3xDC_NbPs0Vid_WIDTH 7
-#define D18F3xDC_NbPs0Vid_MASK 0x7f000
-#define D18F3xDC_NclkFreqDone_OFFSET 19
-#define D18F3xDC_NclkFreqDone_WIDTH 1
-#define D18F3xDC_NclkFreqDone_MASK 0x80000
-#define D18F3xDC_NbPs0NclkDiv_OFFSET 20
-#define D18F3xDC_NbPs0NclkDiv_WIDTH 7
-#define D18F3xDC_NbPs0NclkDiv_MASK 0x7f00000
-#define D18F3xDC_NbClockGateHyst_OFFSET 27
-#define D18F3xDC_NbClockGateHyst_WIDTH 3
-#define D18F3xDC_NbClockGateHyst_MASK 0x38000000
-#define D18F3xDC_NbClockGateEn_OFFSET 30
-#define D18F3xDC_NbClockGateEn_WIDTH 1
-#define D18F3xDC_NbClockGateEn_MASK 0x40000000
-#define D18F3xDC_CnbCifClockGateEn_OFFSET 31
-#define D18F3xDC_CnbCifClockGateEn_WIDTH 1
-#define D18F3xDC_CnbCifClockGateEn_MASK 0x80000000
+#define D18F2xE4_HTCmdHigh_OFFSET 0
+#define D18F2xE4_HTCmdHigh_WIDTH 32
+#define D18F2xE4_HTCmdHigh_MASK 0xffffffff
-/// D18F3xDC
+/// D18F2xE4
typedef union {
struct { ///<
- UINT32 Reserved_7_0:8 ; ///<
- UINT32 PstateMaxVal:3 ; ///<
- UINT32 Reserved_11_11:1 ; ///<
- UINT32 NbPs0Vid:7 ; ///<
- UINT32 NclkFreqDone:1 ; ///<
- UINT32 NbPs0NclkDiv:7 ; ///<
- UINT32 NbClockGateHyst:3 ; ///<
- UINT32 NbClockGateEn:1 ; ///<
- UINT32 CnbCifClockGateEn:1 ; ///<
+ UINT32 HTCmdHigh:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3xDC_STRUCT;
+} D18F2xE4_STRUCT;
-// **** D18F3x15C Register Definition ****
+// **** D18F2xE8 Register Definition ****
// Address
-#define D18F3x15C_ADDRESS 0x15c
+#define D18F2xE8_ADDRESS 0xe8
// Type
-#define D18F3x15C_TYPE TYPE_D18F3
+#define D18F2xE8_TYPE TYPE_D18F2
// Field Data
-#define D18F3x15C_SclkVidLevel0_OFFSET 0
-#define D18F3x15C_SclkVidLevel0_WIDTH 7
-#define D18F3x15C_SclkVidLevel0_MASK 0x7f
-#define D18F3x15C_Reserved_7_7_OFFSET 7
-#define D18F3x15C_Reserved_7_7_WIDTH 1
-#define D18F3x15C_Reserved_7_7_MASK 0x80
-#define D18F3x15C_SclkVidLevel1_OFFSET 8
-#define D18F3x15C_SclkVidLevel1_WIDTH 7
-#define D18F3x15C_SclkVidLevel1_MASK 0x7f00
-#define D18F3x15C_Reserved_15_15_OFFSET 15
-#define D18F3x15C_Reserved_15_15_WIDTH 1
-#define D18F3x15C_Reserved_15_15_MASK 0x8000
-#define D18F3x15C_SclkVidLevel2_OFFSET 16
-#define D18F3x15C_SclkVidLevel2_WIDTH 7
-#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000
-#define D18F3x15C_Reserved_23_23_OFFSET 23
-#define D18F3x15C_Reserved_23_23_WIDTH 1
-#define D18F3x15C_Reserved_23_23_MASK 0x800000
-#define D18F3x15C_SclkVidLevel3_OFFSET 24
-#define D18F3x15C_SclkVidLevel3_WIDTH 7
-#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000
-#define D18F3x15C_Reserved_31_31_OFFSET 31
-#define D18F3x15C_Reserved_31_31_WIDTH 1
-#define D18F3x15C_Reserved_31_31_MASK 0x80000000
+#define D18F2xE8_HTMaskLow_OFFSET 0
+#define D18F2xE8_HTMaskLow_WIDTH 32
+#define D18F2xE8_HTMaskLow_MASK 0xffffffff
-/// D18F3x15C
+/// D18F2xE8
typedef union {
struct { ///<
- UINT32 SclkVidLevel0:7 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 SclkVidLevel1:7 ; ///<
- UINT32 Reserved_15_15:1 ; ///<
- UINT32 SclkVidLevel2:7 ; ///<
- UINT32 Reserved_23_23:1 ; ///<
- UINT32 SclkVidLevel3:7 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 HTMaskLow:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3x15C_STRUCT;
+} D18F2xE8_STRUCT;
-// **** D18F3x17C Register Definition ****
+// **** D18F2xEC Register Definition ****
// Address
-#define D18F3x17C_ADDRESS 0x17c
+#define D18F2xEC_ADDRESS 0xec
// Type
-#define D18F3x17C_TYPE TYPE_D18F3
+#define D18F2xEC_TYPE TYPE_D18F2
// Field Data
-#define D18F3x17C_HiPriPBC_OFFSET 0
-#define D18F3x17C_HiPriPBC_WIDTH 6
-#define D18F3x17C_HiPriPBC_MASK 0x3f
-#define D18F3x17C_Reserved_7_6_OFFSET 6
-#define D18F3x17C_Reserved_7_6_WIDTH 2
-#define D18F3x17C_Reserved_7_6_MASK 0xc0
-#define D18F3x17C_HiPriNPBC_OFFSET 8
-#define D18F3x17C_HiPriNPBC_WIDTH 6
-#define D18F3x17C_HiPriNPBC_MASK 0x3f00
-#define D18F3x17C_Reserved_31_14_OFFSET 14
-#define D18F3x17C_Reserved_31_14_WIDTH 18
-#define D18F3x17C_Reserved_31_14_MASK 0xffffc000
+#define D18F2xEC_HTMaskHigh_OFFSET 0
+#define D18F2xEC_HTMaskHigh_WIDTH 32
+#define D18F2xEC_HTMaskHigh_MASK 0xffffffff
-/// D18F3x17C
+/// D18F2xEC
typedef union {
struct { ///<
- UINT32 HiPriPBC:6 ; ///<
- UINT32 Reserved_7_6:2 ; ///<
- UINT32 HiPriNPBC:6 ; ///<
- UINT32 Reserved_31_14:18; ///<
+ UINT32 HTMaskHigh:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3x17C_STRUCT;
+} D18F2xEC_STRUCT;
-// **** D18F4x12C Register Definition ****
+// **** D18F2xF0 Register Definition ****
// Address
-#define D18F4x12C_ADDRESS 0x12c
+#define D18F2xF0_ADDRESS 0xf0
// Type
-#define D18F4x12C_TYPE TYPE_D18F4
+#define D18F2xF0_TYPE TYPE_D18F2
// Field Data
-#define D18F4x12C_C6Base_35_24__OFFSET 0
-#define D18F4x12C_C6Base_35_24__WIDTH 12
-#define D18F4x12C_C6Base_35_24__MASK 0xfff
-#define D18F4x12C_Reserved_31_12_OFFSET 12
-#define D18F4x12C_Reserved_31_12_WIDTH 20
-#define D18F4x12C_Reserved_31_12_MASK 0xfffff000
+#define D18F2xF0_DctOffset_OFFSET 0
+#define D18F2xF0_DctOffset_WIDTH 28
+#define D18F2xF0_DctOffset_MASK 0xfffffff
+#define D18F2xF0_Reserved_29_28_OFFSET 28
+#define D18F2xF0_Reserved_29_28_WIDTH 2
+#define D18F2xF0_Reserved_29_28_MASK 0x30000000
+#define D18F2xF0_DctAccessWrite_OFFSET 30
+#define D18F2xF0_DctAccessWrite_WIDTH 1
+#define D18F2xF0_DctAccessWrite_MASK 0x40000000
+#define D18F2xF0_DctAccessDone_OFFSET 31
+#define D18F2xF0_DctAccessDone_WIDTH 1
+#define D18F2xF0_DctAccessDone_MASK 0x80000000
-/// D18F4x12C
+/// D18F2xF0
typedef union {
struct { ///<
- UINT32 C6Base_35_24_:12; ///<
- UINT32 Reserved_31_12:20; ///<
+ UINT32 DctOffset:28; ///<
+ UINT32 Reserved_29_28:2 ; ///<
+ UINT32 DctAccessWrite:1 ; ///<
+ UINT32 DctAccessDone:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F4x12C_STRUCT;
+} D18F2xF0_STRUCT;
-// **** D18F4x164 Register Definition ****
+// **** D18F2x184 Register Definition ****
// Address
-#define D18F4x164_ADDRESS 0x164
+#define D18F2x184_ADDRESS 0x184
-// Type
-#define D18F4x164_TYPE TYPE_D18F4
-// Field Data
-#define D18F4x164_FixedErrata_OFFSET 0
-#define D18F4x164_FixedErrata_WIDTH 32
-#define D18F4x164_FixedErrata_MASK 0xffffffff
+// **** D18F2x18C Register Definition ****
+// Address
+#define D18F2x18C_ADDRESS 0x18c
-/// D18F4x164
-typedef union {
- struct { ///<
- UINT32 FixedErrata:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F4x164_STRUCT;
+// **** D18F2x190 Register Definition ****
+// Address
+#define D18F2x190_ADDRESS 0x190
-// **** D18F6x90 Register Definition ****
+// **** D18F2x194 Register Definition ****
// Address
-#define D18F6x90_ADDRESS 0x90
+#define D18F2x194_ADDRESS 0x194
+
+// **** D18F2x198 Register Definition ****
+// Address
+#define D18F2x198_ADDRESS 0x198
+
+// **** D18F2x1F0 Register Definition ****
+// Address
+#define D18F2x1F0_ADDRESS 0x1f0
+
+// **** D18F2xF4 Register Definition ****
+// Address
+#define D18F2xF4_ADDRESS 0xf4
// Type
-#define D18F6x90_TYPE TYPE_D18F6
+#define D18F2xF4_TYPE TYPE_D18F2
// Field Data
-#define D18F6x90_NbPs1NclkDiv_OFFSET 0
-#define D18F6x90_NbPs1NclkDiv_WIDTH 7
-#define D18F6x90_NbPs1NclkDiv_MASK 0x7f
-#define D18F6x90_Reserved_7_7_OFFSET 7
-#define D18F6x90_Reserved_7_7_WIDTH 1
-#define D18F6x90_Reserved_7_7_MASK 0x80
-#define D18F6x90_NbPs1Vid_OFFSET 8
-#define D18F6x90_NbPs1Vid_WIDTH 7
-#define D18F6x90_NbPs1Vid_MASK 0x7f00
-#define D18F6x90_Reserved_15_15_OFFSET 15
-#define D18F6x90_Reserved_15_15_WIDTH 1
-#define D18F6x90_Reserved_15_15_MASK 0x8000
-#define D18F6x90_NbPs1GnbSlowIgn_OFFSET 16
-#define D18F6x90_NbPs1GnbSlowIgn_WIDTH 1
-#define D18F6x90_NbPs1GnbSlowIgn_MASK 0x10000
-#define D18F6x90_Reserved_19_17_OFFSET 17
-#define D18F6x90_Reserved_19_17_WIDTH 3
-#define D18F6x90_Reserved_19_17_MASK 0xe0000
-#define D18F6x90_NbPsLock_OFFSET 20
-#define D18F6x90_NbPsLock_WIDTH 1
-#define D18F6x90_NbPsLock_MASK 0x100000
-#define D18F6x90_Reserved_27_21_OFFSET 21
-#define D18F6x90_Reserved_27_21_WIDTH 7
-#define D18F6x90_Reserved_27_21_MASK 0xfe00000
-#define D18F6x90_NbPsForceReq_OFFSET 28
-#define D18F6x90_NbPsForceReq_WIDTH 1
-#define D18F6x90_NbPsForceReq_MASK 0x10000000
-#define D18F6x90_NbPsForceSel_OFFSET 29
-#define D18F6x90_NbPsForceSel_WIDTH 1
-#define D18F6x90_NbPsForceSel_MASK 0x20000000
-#define D18F6x90_NbPsCtrlDis_OFFSET 30
-#define D18F6x90_NbPsCtrlDis_WIDTH 1
-#define D18F6x90_NbPsCtrlDis_MASK 0x40000000
-#define D18F6x90_NbPsCap_OFFSET 31
-#define D18F6x90_NbPsCap_WIDTH 1
-#define D18F6x90_NbPsCap_MASK 0x80000000
+#define D18F2xF4_DctExtDataPort_OFFSET 0
+#define D18F2xF4_DctExtDataPort_WIDTH 32
+#define D18F2xF4_DctExtDataPort_MASK 0xffffffff
-/// D18F6x90
+/// D18F2xF4
typedef union {
struct { ///<
- UINT32 NbPs1NclkDiv:7 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 NbPs1Vid:7 ; ///<
- UINT32 Reserved_15_15:1 ; ///<
- UINT32 NbPs1GnbSlowIgn:1 ; ///<
- UINT32 Reserved_19_17:3 ; ///<
- UINT32 NbPsLock:1 ; ///<
- UINT32 Reserved_27_21:7 ; ///<
- UINT32 NbPsForceReq:1 ; ///<
- UINT32 NbPsForceSel:1 ; ///<
- UINT32 NbPsCtrlDis:1 ; ///<
- UINT32 NbPsCap:1 ; ///<
+ UINT32 DctExtDataPort:32; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F6x90_STRUCT;
+} D18F2xF4_STRUCT;
-// **** D18F6x94 Register Definition ****
+// **** D18F2x0F4_x40 Register Definition ****
// Address
-#define D18F6x94_ADDRESS 0x94
+#define D18F2x0F4_x40_ADDRESS 0x40
// Type
-#define D18F6x94_TYPE TYPE_D18F6
+#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4
// Field Data
-#define D18F6x94_CpuPstateThr_OFFSET 0
-#define D18F6x94_CpuPstateThr_WIDTH 3
-#define D18F6x94_CpuPstateThr_MASK 0x7
-#define D18F6x94_CpuPstateThrEn_OFFSET 3
-#define D18F6x94_CpuPstateThrEn_WIDTH 1
-#define D18F6x94_CpuPstateThrEn_MASK 0x8
-#define D18F6x94_NbPsNoTransOnDma_OFFSET 4
-#define D18F6x94_NbPsNoTransOnDma_WIDTH 1
-#define D18F6x94_NbPsNoTransOnDma_MASK 0x10
-#define D18F6x94_Reserved_19_5_OFFSET 5
-#define D18F6x94_Reserved_19_5_WIDTH 15
-#define D18F6x94_Reserved_19_5_MASK 0xfffe0
-#define D18F6x94_NbPsNonC0Timer_OFFSET 20
-#define D18F6x94_NbPsNonC0Timer_WIDTH 3
-#define D18F6x94_NbPsNonC0Timer_MASK 0x700000
-#define D18F6x94_NbPsC0Timer_OFFSET 23
-#define D18F6x94_NbPsC0Timer_WIDTH 3
-#define D18F6x94_NbPsC0Timer_MASK 0x3800000
-#define D18F6x94_NbPs1ResTmrMin_OFFSET 26
-#define D18F6x94_NbPs1ResTmrMin_WIDTH 3
-#define D18F6x94_NbPs1ResTmrMin_MASK 0x1c000000
-#define D18F6x94_NbPs0ResTmrMin_OFFSET 29
-#define D18F6x94_NbPs0ResTmrMin_WIDTH 3
-#define D18F6x94_NbPs0ResTmrMin_MASK 0xe0000000
+#define D18F2x0F4_x40_Trcd_OFFSET 0
+#define D18F2x0F4_x40_Trcd_WIDTH 4
+#define D18F2x0F4_x40_Trcd_MASK 0xf
+#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4
+#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4
+#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0
+#define D18F2x0F4_x40_Trp_OFFSET 8
+#define D18F2x0F4_x40_Trp_WIDTH 4
+#define D18F2x0F4_x40_Trp_MASK 0xf00
+#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12
+#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4
+#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000
+#define D18F2x0F4_x40_Tras_OFFSET 16
+#define D18F2x0F4_x40_Tras_WIDTH 5
+#define D18F2x0F4_x40_Tras_MASK 0x1f0000
+#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21
+#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3
+#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000
+#define D18F2x0F4_x40_Trc_OFFSET 24
+#define D18F2x0F4_x40_Trc_WIDTH 6
+#define D18F2x0F4_x40_Trc_MASK 0x3f000000
+#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30
+#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2
+#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000
-/// D18F6x94
+/// D18F2x0F4_x40
typedef union {
struct { ///<
- UINT32 CpuPstateThr:3 ; ///<
- UINT32 CpuPstateThrEn:1 ; ///<
- UINT32 NbPsNoTransOnDma:1 ; ///<
- UINT32 Reserved_19_5:15; ///<
- UINT32 NbPsNonC0Timer:3 ; ///<
- UINT32 NbPsC0Timer:3 ; ///<
- UINT32 NbPs1ResTmrMin:3 ; ///<
- UINT32 NbPs0ResTmrMin:3 ; ///<
+ UINT32 Trcd:4 ; ///<
+ UINT32 Reserved_7_4:4 ; ///<
+ UINT32 Trp:4 ; ///<
+ UINT32 Reserved_15_12:4 ; ///<
+ UINT32 Tras:5 ; ///<
+ UINT32 Reserved_23_21:3 ; ///<
+ UINT32 Trc:6 ; ///<
+ UINT32 Reserved_31_30:2 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F6x94_STRUCT;
+} D18F2x0F4_x40_STRUCT;
-// **** D18F6x98 Register Definition ****
+// **** D18F2x0F4_x41 Register Definition ****
// Address
-#define D18F6x98_ADDRESS 0x98
+#define D18F2x0F4_x41_ADDRESS 0x41
// Type
-#define D18F6x98_TYPE TYPE_D18F6
+#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4
// Field Data
-#define D18F6x98_NbPsTransInFlight_OFFSET 0
-#define D18F6x98_NbPsTransInFlight_WIDTH 1
-#define D18F6x98_NbPsTransInFlight_MASK 0x1
-#define D18F6x98_NbPs1ActSts_OFFSET 1
-#define D18F6x98_NbPs1ActSts_WIDTH 1
-#define D18F6x98_NbPs1ActSts_MASK 0x2
-#define D18F6x98_NbPs1Act_OFFSET 2
-#define D18F6x98_NbPs1Act_WIDTH 1
-#define D18F6x98_NbPs1Act_MASK 0x4
-#define D18F6x98_Reserved_29_3_OFFSET 3
-#define D18F6x98_Reserved_29_3_WIDTH 27
-#define D18F6x98_Reserved_29_3_MASK 0x3ffffff8
-#define D18F6x98_NbPsCsrAccSel_OFFSET 30
-#define D18F6x98_NbPsCsrAccSel_WIDTH 1
-#define D18F6x98_NbPsCsrAccSel_MASK 0x40000000
-#define D18F6x98_NbPsDbgEn_OFFSET 31
-#define D18F6x98_NbPsDbgEn_WIDTH 1
-#define D18F6x98_NbPsDbgEn_MASK 0x80000000
+#define D18F2x0F4_x41_Trtp_OFFSET 0
+#define D18F2x0F4_x41_Trtp_WIDTH 3
+#define D18F2x0F4_x41_Trtp_MASK 0x7
+#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3
+#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5
+#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8
+#define D18F2x0F4_x41_Trrd_OFFSET 8
+#define D18F2x0F4_x41_Trrd_WIDTH 3
+#define D18F2x0F4_x41_Trrd_MASK 0x700
+#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11
+#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5
+#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800
+#define D18F2x0F4_x41_Twtr_OFFSET 16
+#define D18F2x0F4_x41_Twtr_WIDTH 3
+#define D18F2x0F4_x41_Twtr_MASK 0x70000
+#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19
+#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13
+#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000
-/// D18F6x98
+/// D18F2x0F4_x41
typedef union {
struct { ///<
- UINT32 NbPsTransInFlight:1 ; ///<
- UINT32 NbPs1ActSts:1 ; ///<
- UINT32 NbPs1Act:1 ; ///<
- UINT32 Reserved_29_3:27; ///<
- UINT32 NbPsCsrAccSel:1 ; ///<
- UINT32 NbPsDbgEn:1 ; ///<
+ UINT32 Trtp:3 ; ///<
+ UINT32 Reserved_7_3:5 ; ///<
+ UINT32 Trrd:3 ; ///<
+ UINT32 Reserved_15_11:5 ; ///<
+ UINT32 Twtr:3 ; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F6x98_STRUCT;
+} D18F2x0F4_x41_STRUCT;
-// **** D18F6x9C Register Definition ****
+// **** D18F2x110 Register Definition ****
// Address
-#define D18F6x9C_ADDRESS 0x9c
+#define D18F2x110_ADDRESS 0x110
// Type
-#define D18F6x9C_TYPE TYPE_D18F6
+#define D18F2x110_TYPE TYPE_D18F2
// Field Data
-#define D18F6x9C_NclkRedDiv_OFFSET 0
-#define D18F6x9C_NclkRedDiv_WIDTH 7
-#define D18F6x9C_NclkRedDiv_MASK 0x7f
-#define D18F6x9C_NclkRedSelfRefrAlways_OFFSET 7
-#define D18F6x9C_NclkRedSelfRefrAlways_WIDTH 1
-#define D18F6x9C_NclkRedSelfRefrAlways_MASK 0x80
-#define D18F6x9C_NclkRampWithDllRelock_OFFSET 8
-#define D18F6x9C_NclkRampWithDllRelock_WIDTH 1
-#define D18F6x9C_NclkRampWithDllRelock_MASK 0x100
-#define D18F6x9C_Reserved_31_9_OFFSET 9
-#define D18F6x9C_Reserved_31_9_WIDTH 23
-#define D18F6x9C_Reserved_31_9_MASK 0xfffffe00
+#define D18F2x110_Reserved_2_0_OFFSET 0
+#define D18F2x110_Reserved_2_0_WIDTH 3
+#define D18F2x110_Reserved_2_0_MASK 0x7
+#define D18F2x110_MemClrInit_OFFSET 3
+#define D18F2x110_MemClrInit_WIDTH 1
+#define D18F2x110_MemClrInit_MASK 0x8
+#define D18F2x110_Reserved_7_4_OFFSET 4
+#define D18F2x110_Reserved_7_4_WIDTH 4
+#define D18F2x110_Reserved_7_4_MASK 0xf0
+#define D18F2x110_DramEnable_OFFSET 8
+#define D18F2x110_DramEnable_WIDTH 1
+#define D18F2x110_DramEnable_MASK 0x100
+#define D18F2x110_MemClrBusy_OFFSET 9
+#define D18F2x110_MemClrBusy_WIDTH 1
+#define D18F2x110_MemClrBusy_MASK 0x200
+#define D18F2x110_MemCleared_OFFSET 10
+#define D18F2x110_MemCleared_WIDTH 1
+#define D18F2x110_MemCleared_MASK 0x400
+#define D18F2x110_Reserved_31_11_OFFSET 11
+#define D18F2x110_Reserved_31_11_WIDTH 21
+#define D18F2x110_Reserved_31_11_MASK 0xfffff800
-/// D18F6x9C
+/// D18F2x110
typedef union {
struct { ///<
- UINT32 NclkRedDiv:7 ; ///<
- UINT32 NclkRedSelfRefrAlways:1 ; ///<
- UINT32 NclkRampWithDllRelock:1 ; ///<
- UINT32 Reserved_31_9:23; ///<
+ UINT32 Reserved_2_0:3 ; ///<
+ UINT32 MemClrInit:1 ; ///<
+ UINT32 Reserved_7_4:4 ; ///<
+ UINT32 DramEnable:1 ; ///<
+ UINT32 MemClrBusy:1 ; ///<
+ UINT32 MemCleared:1 ; ///<
+ UINT32 Reserved_31_11:21; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F6x9C_STRUCT;
+} D18F2x110_STRUCT;
-// **** DxF0x00 Register Definition ****
+// **** D18F2x114 Register Definition ****
// Address
-#define DxF0x00_ADDRESS 0x0
+#define D18F2x114_ADDRESS 0x114
// Type
-#define DxF0x00_TYPE TYPE_D4F0
+#define D18F2x114_TYPE TYPE_D18F2
// Field Data
-#define DxF0x00_VendorID_OFFSET 0
-#define DxF0x00_VendorID_WIDTH 16
-#define DxF0x00_VendorID_MASK 0xffff
-#define DxF0x00_DeviceID_OFFSET 16
-#define DxF0x00_DeviceID_WIDTH 16
-#define DxF0x00_DeviceID_MASK 0xffff0000
+#define D18F2x114_Reserved_8_0_OFFSET 0
+#define D18F2x114_Reserved_8_0_WIDTH 9
+#define D18F2x114_Reserved_8_0_MASK 0x1ff
+#define D18F2x114_DctSelBankSwap_OFFSET 9
+#define D18F2x114_DctSelBankSwap_WIDTH 1
+#define D18F2x114_DctSelBankSwap_MASK 0x200
+#define D18F2x114_Reserved_31_10_OFFSET 10
+#define D18F2x114_Reserved_31_10_WIDTH 22
+#define D18F2x114_Reserved_31_10_MASK 0xfffffc00
-/// DxF0x00
+/// D18F2x114
typedef union {
struct { ///<
- UINT32 VendorID:16; ///<
- UINT32 DeviceID:16; ///<
+ UINT32 Reserved_8_0:9 ; ///<
+ UINT32 DctSelBankSwap:1 ; ///<
+ UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x00_STRUCT;
+} D18F2x114_STRUCT;
-// **** DxF0x04 Register Definition ****
+// **** D18F3x64 Register Definition ****
// Address
-#define DxF0x04_ADDRESS 0x4
+#define D18F3x64_ADDRESS 0x64
// Type
-#define DxF0x04_TYPE TYPE_D4F0
+#define D18F3x64_TYPE TYPE_D18F3
// Field Data
-#define DxF0x04_IoAccessEn_OFFSET 0
-#define DxF0x04_IoAccessEn_WIDTH 1
-#define DxF0x04_IoAccessEn_MASK 0x1
-#define DxF0x04_MemAccessEn_OFFSET 1
-#define DxF0x04_MemAccessEn_WIDTH 1
-#define DxF0x04_MemAccessEn_MASK 0x2
-#define DxF0x04_BusMasterEn_OFFSET 2
-#define DxF0x04_BusMasterEn_WIDTH 1
-#define DxF0x04_BusMasterEn_MASK 0x4
-#define DxF0x04_SpecialCycleEn_OFFSET 3
-#define DxF0x04_SpecialCycleEn_WIDTH 1
-#define DxF0x04_SpecialCycleEn_MASK 0x8
-#define DxF0x04_MemWriteInvalidateEn_OFFSET 4
-#define DxF0x04_MemWriteInvalidateEn_WIDTH 1
-#define DxF0x04_MemWriteInvalidateEn_MASK 0x10
-#define DxF0x04_PalSnoopEn_OFFSET 5
-#define DxF0x04_PalSnoopEn_WIDTH 1
-#define DxF0x04_PalSnoopEn_MASK 0x20
-#define DxF0x04_ParityErrorEn_OFFSET 6
-#define DxF0x04_ParityErrorEn_WIDTH 1
-#define DxF0x04_ParityErrorEn_MASK 0x40
-#define DxF0x04_IdselStepping_OFFSET 7
-#define DxF0x04_IdselStepping_WIDTH 1
-#define DxF0x04_IdselStepping_MASK 0x80
-#define DxF0x04_SerrEn_OFFSET 8
-#define DxF0x04_SerrEn_WIDTH 1
-#define DxF0x04_SerrEn_MASK 0x100
-#define DxF0x04_FastB2BEn_OFFSET 9
-#define DxF0x04_FastB2BEn_WIDTH 1
-#define DxF0x04_FastB2BEn_MASK 0x200
-#define DxF0x04_IntDis_OFFSET 10
-#define DxF0x04_IntDis_WIDTH 1
-#define DxF0x04_IntDis_MASK 0x400
-#define DxF0x04_Reserved_18_11_OFFSET 11
-#define DxF0x04_Reserved_18_11_WIDTH 8
-#define DxF0x04_Reserved_18_11_MASK 0x7f800
-#define DxF0x04_IntStatus_OFFSET 19
-#define DxF0x04_IntStatus_WIDTH 1
-#define DxF0x04_IntStatus_MASK 0x80000
-#define DxF0x04_CapList_OFFSET 20
-#define DxF0x04_CapList_WIDTH 1
-#define DxF0x04_CapList_MASK 0x100000
-#define DxF0x04_PCI66En_OFFSET 21
-#define DxF0x04_PCI66En_WIDTH 1
-#define DxF0x04_PCI66En_MASK 0x200000
-#define DxF0x04_UDFEn_OFFSET 22
-#define DxF0x04_UDFEn_WIDTH 1
-#define DxF0x04_UDFEn_MASK 0x400000
-#define DxF0x04_FastBackCapable_OFFSET 23
-#define DxF0x04_FastBackCapable_WIDTH 1
-#define DxF0x04_FastBackCapable_MASK 0x800000
-#define DxF0x04_MasterDataPerr_OFFSET 24
-#define DxF0x04_MasterDataPerr_WIDTH 1
-#define DxF0x04_MasterDataPerr_MASK 0x1000000
-#define DxF0x04_DevselTiming_OFFSET 25
-#define DxF0x04_DevselTiming_WIDTH 2
-#define DxF0x04_DevselTiming_MASK 0x6000000
-#define DxF0x04_SignaledTargetAbort_OFFSET 27
-#define DxF0x04_SignaledTargetAbort_WIDTH 1
-#define DxF0x04_SignaledTargetAbort_MASK 0x8000000
-#define DxF0x04_ReceivedTargetAbort_OFFSET 28
-#define DxF0x04_ReceivedTargetAbort_WIDTH 1
-#define DxF0x04_ReceivedTargetAbort_MASK 0x10000000
-#define DxF0x04_ReceivedMasterAbort_OFFSET 29
-#define DxF0x04_ReceivedMasterAbort_WIDTH 1
-#define DxF0x04_ReceivedMasterAbort_MASK 0x20000000
-#define DxF0x04_SignaledSystemError_OFFSET 30
-#define DxF0x04_SignaledSystemError_WIDTH 1
-#define DxF0x04_SignaledSystemError_MASK 0x40000000
-#define DxF0x04_ParityErrorDetected_OFFSET 31
-#define DxF0x04_ParityErrorDetected_WIDTH 1
-#define DxF0x04_ParityErrorDetected_MASK 0x80000000
+#define D18F3x64_HtcEn_OFFSET 0
+#define D18F3x64_HtcEn_WIDTH 1
+#define D18F3x64_HtcEn_MASK 0x1
+#define D18F3x64_Reserved_3_1_OFFSET 1
+#define D18F3x64_Reserved_3_1_WIDTH 3
+#define D18F3x64_Reserved_3_1_MASK 0xe
+#define D18F3x64_HtcAct_OFFSET 4
+#define D18F3x64_HtcAct_WIDTH 1
+#define D18F3x64_HtcAct_MASK 0x10
+#define D18F3x64_HtcActSts_OFFSET 5
+#define D18F3x64_HtcActSts_WIDTH 1
+#define D18F3x64_HtcActSts_MASK 0x20
+#define D18F3x64_PslApicHiEn_OFFSET 6
+#define D18F3x64_PslApicHiEn_WIDTH 1
+#define D18F3x64_PslApicHiEn_MASK 0x40
+#define D18F3x64_PslApicLoEn_OFFSET 7
+#define D18F3x64_PslApicLoEn_WIDTH 1
+#define D18F3x64_PslApicLoEn_MASK 0x80
+#define D18F3x64_Reserved_15_8_OFFSET 8
+#define D18F3x64_Reserved_15_8_WIDTH 8
+#define D18F3x64_Reserved_15_8_MASK 0xff00
+#define D18F3x64_HtcTmpLmt_OFFSET 16
+#define D18F3x64_HtcTmpLmt_WIDTH 7
+#define D18F3x64_HtcTmpLmt_MASK 0x7f0000
+#define D18F3x64_HtcSlewSel_OFFSET 23
+#define D18F3x64_HtcSlewSel_WIDTH 1
+#define D18F3x64_HtcSlewSel_MASK 0x800000
+#define D18F3x64_HtcHystLmt_OFFSET 24
+#define D18F3x64_HtcHystLmt_WIDTH 4
+#define D18F3x64_HtcHystLmt_MASK 0xf000000
+#define D18F3x64_HtcPstateLimit_OFFSET 28
+#define D18F3x64_HtcPstateLimit_WIDTH 3
+#define D18F3x64_HtcPstateLimit_MASK 0x70000000
+#define D18F3x64_HtcLock_OFFSET 31
+#define D18F3x64_HtcLock_WIDTH 1
+#define D18F3x64_HtcLock_MASK 0x80000000
-/// DxF0x04
+/// D18F3x64
typedef union {
struct { ///<
- UINT32 IoAccessEn:1 ; ///<
- UINT32 MemAccessEn:1 ; ///<
- UINT32 BusMasterEn:1 ; ///<
- UINT32 SpecialCycleEn:1 ; ///<
- UINT32 MemWriteInvalidateEn:1 ; ///<
- UINT32 PalSnoopEn:1 ; ///<
- UINT32 ParityErrorEn:1 ; ///<
- UINT32 IdselStepping:1 ; ///<
- UINT32 SerrEn:1 ; ///<
- UINT32 FastB2BEn:1 ; ///<
- UINT32 IntDis:1 ; ///<
- UINT32 Reserved_18_11:8 ; ///<
- UINT32 IntStatus:1 ; ///<
- UINT32 CapList:1 ; ///<
- UINT32 PCI66En:1 ; ///<
- UINT32 UDFEn:1 ; ///<
- UINT32 FastBackCapable:1 ; ///<
- UINT32 MasterDataPerr:1 ; ///<
- UINT32 DevselTiming:2 ; ///<
- UINT32 SignaledTargetAbort:1 ; ///<
- UINT32 ReceivedTargetAbort:1 ; ///<
- UINT32 ReceivedMasterAbort:1 ; ///<
- UINT32 SignaledSystemError:1 ; ///<
- UINT32 ParityErrorDetected:1 ; ///<
+ UINT32 HtcEn:1 ; ///<
+ UINT32 Reserved_3_1:3 ; ///<
+ UINT32 HtcAct:1 ; ///<
+ UINT32 HtcActSts:1 ; ///<
+ UINT32 PslApicHiEn:1 ; ///<
+ UINT32 PslApicLoEn:1 ; ///<
+ UINT32 Reserved_15_8:8 ; ///<
+ UINT32 HtcTmpLmt:7 ; ///<
+ UINT32 HtcSlewSel:1 ; ///<
+ UINT32 HtcHystLmt:4 ; ///<
+ UINT32 HtcPstateLimit:3 ; ///<
+ UINT32 HtcLock:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x04_STRUCT;
+} D18F3x64_STRUCT;
-// **** DxF0x08 Register Definition ****
+// **** D18F3x6C Register Definition ****
// Address
-#define DxF0x08_ADDRESS 0x8
+#define D18F3x6C_ADDRESS 0x6c
// Type
-#define DxF0x08_TYPE TYPE_D4F0
+#define D18F3x6C_TYPE TYPE_D18F3
// Field Data
-#define DxF0x08_RevID_OFFSET 0
-#define DxF0x08_RevID_WIDTH 8
-#define DxF0x08_RevID_MASK 0xff
-#define DxF0x08_ClassCode_OFFSET 8
-#define DxF0x08_ClassCode_WIDTH 24
-#define DxF0x08_ClassCode_MASK 0xffffff00
+#define D18F3x6C_UpLoPreqDBC_OFFSET 0
+#define D18F3x6C_UpLoPreqDBC_WIDTH 4
+#define D18F3x6C_UpLoPreqDBC_MASK 0xf
+#define D18F3x6C_UpLoNpreqDBC_OFFSET 4
+#define D18F3x6C_UpLoNpreqDBC_WIDTH 4
+#define D18F3x6C_UpLoNpreqDBC_MASK 0xf0
+#define D18F3x6C_UpLoRespDBC_OFFSET 8
+#define D18F3x6C_UpLoRespDBC_WIDTH 4
+#define D18F3x6C_UpLoRespDBC_MASK 0xf00
+#define D18F3x6C_Reserved_15_12_OFFSET 12
+#define D18F3x6C_Reserved_15_12_WIDTH 4
+#define D18F3x6C_Reserved_15_12_MASK 0xf000
+#define D18F3x6C_UpHiPreqDBC_OFFSET 16
+#define D18F3x6C_UpHiPreqDBC_WIDTH 4
+#define D18F3x6C_UpHiPreqDBC_MASK 0xf0000
+#define D18F3x6C_UpHiNpreqDBC_OFFSET 20
+#define D18F3x6C_UpHiNpreqDBC_WIDTH 4
+#define D18F3x6C_UpHiNpreqDBC_MASK 0xf00000
+#define D18F3x6C_Reserved_31_24_OFFSET 24
+#define D18F3x6C_Reserved_31_24_WIDTH 8
+#define D18F3x6C_Reserved_31_24_MASK 0xff000000
-/// DxF0x08
+/// D18F3x6C
typedef union {
struct { ///<
- UINT32 RevID:8 ; ///<
- UINT32 ClassCode:24; ///<
+ UINT32 UpLoPreqDBC:4 ; ///<
+ UINT32 UpLoNpreqDBC:4 ; ///<
+ UINT32 UpLoRespDBC:4 ; ///<
+ UINT32 Reserved_15_12:4 ; ///<
+ UINT32 UpHiPreqDBC:4 ; ///<
+ UINT32 UpHiNpreqDBC:4 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x08_STRUCT;
+} D18F3x6C_STRUCT;
-// **** DxF0x0C Register Definition ****
+// **** D18F3x74 Register Definition ****
// Address
-#define DxF0x0C_ADDRESS 0xc
+#define D18F3x74_ADDRESS 0x74
// Type
-#define DxF0x0C_TYPE TYPE_D4F0
+#define D18F3x74_TYPE TYPE_D18F3
// Field Data
-#define DxF0x0C_CacheLineSize_OFFSET 0
-#define DxF0x0C_CacheLineSize_WIDTH 8
-#define DxF0x0C_CacheLineSize_MASK 0xff
-#define DxF0x0C_LatencyTimer_OFFSET 8
-#define DxF0x0C_LatencyTimer_WIDTH 8
-#define DxF0x0C_LatencyTimer_MASK 0xff00
-#define DxF0x0C_HeaderTypeReg_OFFSET 16
-#define DxF0x0C_HeaderTypeReg_WIDTH 8
-#define DxF0x0C_HeaderTypeReg_MASK 0xff0000
-#define DxF0x0C_BIST_OFFSET 24
-#define DxF0x0C_BIST_WIDTH 8
-#define DxF0x0C_BIST_MASK 0xff000000
-
-/// DxF0x0C
-typedef union {
- struct { ///<
- UINT32 CacheLineSize:8 ; ///<
- UINT32 LatencyTimer:8 ; ///<
- UINT32 HeaderTypeReg:8 ; ///<
- UINT32 BIST:8 ; ///<
+#define D18F3x74_UpLoPreqCBC_OFFSET 0
+#define D18F3x74_UpLoPreqCBC_WIDTH 4
+#define D18F3x74_UpLoPreqCBC_MASK 0xf
+#define D18F3x74_UpLoNpreqCBC_OFFSET 4
+#define D18F3x74_UpLoNpreqCBC_WIDTH 4
+#define D18F3x74_UpLoNpreqCBC_MASK 0xf0
+#define D18F3x74_UpLoRespCBC_OFFSET 8
+#define D18F3x74_UpLoRespCBC_WIDTH 4
+#define D18F3x74_UpLoRespCBC_MASK 0xf00
+#define D18F3x74_Reserved_15_12_OFFSET 12
+#define D18F3x74_Reserved_15_12_WIDTH 4
+#define D18F3x74_Reserved_15_12_MASK 0xf000
+#define D18F3x74_UpHiPreqCBC_OFFSET 16
+#define D18F3x74_UpHiPreqCBC_WIDTH 4
+#define D18F3x74_UpHiPreqCBC_MASK 0xf0000
+#define D18F3x74_UpHiNpreqCBC_OFFSET 20
+#define D18F3x74_UpHiNpreqCBC_WIDTH 4
+#define D18F3x74_UpHiNpreqCBC_MASK 0xf00000
+#define D18F3x74_Reserved_31_24_OFFSET 24
+#define D18F3x74_Reserved_31_24_WIDTH 8
+#define D18F3x74_Reserved_31_24_MASK 0xff000000
+
+/// D18F3x74
+typedef union {
+ struct { ///<
+ UINT32 UpLoPreqCBC:4 ; ///<
+ UINT32 UpLoNpreqCBC:4 ; ///<
+ UINT32 UpLoRespCBC:4 ; ///<
+ UINT32 Reserved_15_12:4 ; ///<
+ UINT32 UpHiPreqCBC:4 ; ///<
+ UINT32 UpHiNpreqCBC:4 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x0C_STRUCT;
+} D18F3x74_STRUCT;
-// **** DxF0x18 Register Definition ****
+// **** D18F3x7C Register Definition ****
// Address
-#define DxF0x18_ADDRESS 0x18
+#define D18F3x7C_ADDRESS 0x7c
// Type
-#define DxF0x18_TYPE TYPE_D4F0
+#define D18F3x7C_TYPE TYPE_D18F3
// Field Data
-#define DxF0x18_PrimaryBus_OFFSET 0
-#define DxF0x18_PrimaryBus_WIDTH 8
-#define DxF0x18_PrimaryBus_MASK 0xff
-#define DxF0x18_SecondaryBus_OFFSET 8
-#define DxF0x18_SecondaryBus_WIDTH 8
-#define DxF0x18_SecondaryBus_MASK 0xff00
-#define DxF0x18_SubBusNumber_OFFSET 16
-#define DxF0x18_SubBusNumber_WIDTH 8
-#define DxF0x18_SubBusNumber_MASK 0xff0000
-#define DxF0x18_SecondaryLatencyTimer_OFFSET 24
-#define DxF0x18_SecondaryLatencyTimer_WIDTH 8
-#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000
+#define D18F3x7C_CpuBC_OFFSET 0
+#define D18F3x7C_CpuBC_WIDTH 6
+#define D18F3x7C_CpuBC_MASK 0x3f
+#define D18F3x7C_Reserved_7_6_OFFSET 6
+#define D18F3x7C_Reserved_7_6_WIDTH 2
+#define D18F3x7C_Reserved_7_6_MASK 0xc0
+#define D18F3x7C_LoPriPBC_OFFSET 8
+#define D18F3x7C_LoPriPBC_WIDTH 6
+#define D18F3x7C_LoPriPBC_MASK 0x3f00
+#define D18F3x7C_Reserved_15_14_OFFSET 14
+#define D18F3x7C_Reserved_15_14_WIDTH 2
+#define D18F3x7C_Reserved_15_14_MASK 0xc000
+#define D18F3x7C_LoPriNpBC_OFFSET 16
+#define D18F3x7C_LoPriNpBC_WIDTH 6
+#define D18F3x7C_LoPriNpBC_MASK 0x3f0000
+#define D18F3x7C_Reserved_23_22_OFFSET 22
+#define D18F3x7C_Reserved_23_22_WIDTH 2
+#define D18F3x7C_Reserved_23_22_MASK 0xc00000
+#define D18F3x7C_FreePoolBC_OFFSET 24
+#define D18F3x7C_FreePoolBC_WIDTH 6
+#define D18F3x7C_FreePoolBC_MASK 0x3f000000
+#define D18F3x7C_Reserved_31_30_OFFSET 30
+#define D18F3x7C_Reserved_31_30_WIDTH 2
+#define D18F3x7C_Reserved_31_30_MASK 0xc0000000
-/// DxF0x18
+/// D18F3x7C
typedef union {
struct { ///<
- UINT32 PrimaryBus:8 ; ///<
- UINT32 SecondaryBus:8 ; ///<
- UINT32 SubBusNumber:8 ; ///<
- UINT32 SecondaryLatencyTimer:8 ; ///<
+ UINT32 CpuBC:6 ; ///<
+ UINT32 Reserved_7_6:2 ; ///<
+ UINT32 LoPriPBC:6 ; ///<
+ UINT32 Reserved_15_14:2 ; ///<
+ UINT32 LoPriNPBC:6 ; ///<
+ UINT32 Reserved_23_22:2 ; ///<
+ UINT32 FreePoolBC:6 ; ///<
+ UINT32 Reserved_31_30:2 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x18_STRUCT;
+} D18F3x7C_STRUCT;
-// **** DxF0x1C Register Definition ****
+// **** D18F3xD4 Register Definition ****
// Address
-#define DxF0x1C_ADDRESS 0x1c
+#define D18F3xD4_ADDRESS 0xd4
// Type
-#define DxF0x1C_TYPE TYPE_D4F0
+#define D18F3xD4_TYPE TYPE_D18F3
// Field Data
-#define DxF0x1C_Reserved_3_0_OFFSET 0
-#define DxF0x1C_Reserved_3_0_WIDTH 4
-#define DxF0x1C_Reserved_3_0_MASK 0xf
-#define DxF0x1C_IOBase_15_12__OFFSET 4
-#define DxF0x1C_IOBase_15_12__WIDTH 4
-#define DxF0x1C_IOBase_15_12__MASK 0xf0
-#define DxF0x1C_Reserved_11_8_OFFSET 8
-#define DxF0x1C_Reserved_11_8_WIDTH 4
-#define DxF0x1C_Reserved_11_8_MASK 0xf00
-#define DxF0x1C_IOLimit_15_12__OFFSET 12
-#define DxF0x1C_IOLimit_15_12__WIDTH 4
-#define DxF0x1C_IOLimit_15_12__MASK 0xf000
-#define DxF0x1C_Reserved_19_16_OFFSET 16
-#define DxF0x1C_Reserved_19_16_WIDTH 4
-#define DxF0x1C_Reserved_19_16_MASK 0xf0000
-#define DxF0x1C_CapList_OFFSET 20
-#define DxF0x1C_CapList_WIDTH 1
-#define DxF0x1C_CapList_MASK 0x100000
-#define DxF0x1C_PCI66En_OFFSET 21
-#define DxF0x1C_PCI66En_WIDTH 1
-#define DxF0x1C_PCI66En_MASK 0x200000
-#define DxF0x1C_UDFEn_OFFSET 22
-#define DxF0x1C_UDFEn_WIDTH 1
-#define DxF0x1C_UDFEn_MASK 0x400000
-#define DxF0x1C_FastBackCapable_OFFSET 23
-#define DxF0x1C_FastBackCapable_WIDTH 1
-#define DxF0x1C_FastBackCapable_MASK 0x800000
-#define DxF0x1C_MasterDataPerr_OFFSET 24
-#define DxF0x1C_MasterDataPerr_WIDTH 1
-#define DxF0x1C_MasterDataPerr_MASK 0x1000000
-#define DxF0x1C_DevselTiming_OFFSET 25
-#define DxF0x1C_DevselTiming_WIDTH 2
-#define DxF0x1C_DevselTiming_MASK 0x6000000
-#define DxF0x1C_SignalTargetAbort_OFFSET 27
-#define DxF0x1C_SignalTargetAbort_WIDTH 1
-#define DxF0x1C_SignalTargetAbort_MASK 0x8000000
-#define DxF0x1C_ReceivedTargetAbort_OFFSET 28
-#define DxF0x1C_ReceivedTargetAbort_WIDTH 1
-#define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000
-#define DxF0x1C_ReceivedMasterAbort_OFFSET 29
-#define DxF0x1C_ReceivedMasterAbort_WIDTH 1
-#define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000
-#define DxF0x1C_ReceivedSystemError_OFFSET 30
-#define DxF0x1C_ReceivedSystemError_WIDTH 1
-#define DxF0x1C_ReceivedSystemError_MASK 0x40000000
-#define DxF0x1C_ParityErrorDetected_OFFSET 31
-#define DxF0x1C_ParityErrorDetected_WIDTH 1
-#define DxF0x1C_ParityErrorDetected_MASK 0x80000000
+#define D18F3xD4_MainPllOpFreqId_OFFSET 0
+#define D18F3xD4_MainPllOpFreqId_WIDTH 6
+#define D18F3xD4_MainPllOpFreqId_MASK 0x3f
+#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6
+#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1
+#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40
+#define D18F3xD4_Reserved_7_7_OFFSET 7
+#define D18F3xD4_Reserved_7_7_WIDTH 1
+#define D18F3xD4_Reserved_7_7_MASK 0x80
+#define D18F3xD4_ClkRampHystSel_OFFSET 8
+#define D18F3xD4_ClkRampHystSel_WIDTH 4
+#define D18F3xD4_ClkRampHystSel_MASK 0xf00
+#define D18F3xD4_NbOutHyst_OFFSET 12
+#define D18F3xD4_NbOutHyst_WIDTH 4
+#define D18F3xD4_NbOutHyst_MASK 0xf000
+#define D18F3xD4_DisNclkGatingIdle_OFFSET 16
+#define D18F3xD4_DisNclkGatingIdle_WIDTH 1
+#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000
+#define D18F3xD4_ClockGatingEnDram_OFFSET 17
+#define D18F3xD4_ClockGatingEnDram_WIDTH 1
+#define D18F3xD4_ClockGatingEnDram_MASK 0x20000
+#define D18F3xD4_Reserved_18_18_OFFSET 18
+#define D18F3xD4_Reserved_18_18_WIDTH 1
+#define D18F3xD4_Reserved_18_18_MASK 0x40000
+#define D18F3xD4_Reserved_31_19_OFFSET 19
+#define D18F3xD4_Reserved_31_19_WIDTH 13
+#define D18F3xD4_Reserved_31_19_MASK 0xfff80000
-/// DxF0x1C
+/// D18F3xD4
typedef union {
struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 IOBase_15_12_:4 ; ///<
- UINT32 Reserved_11_8:4 ; ///<
- UINT32 IOLimit_15_12_:4 ; ///<
- UINT32 Reserved_19_16:4 ; ///<
- UINT32 CapList:1 ; ///<
- UINT32 PCI66En:1 ; ///<
- UINT32 UDFEn:1 ; ///<
- UINT32 FastBackCapable:1 ; ///<
- UINT32 MasterDataPerr:1 ; ///<
- UINT32 DevselTiming:2 ; ///<
- UINT32 SignalTargetAbort:1 ; ///<
- UINT32 ReceivedTargetAbort:1 ; ///<
- UINT32 ReceivedMasterAbort:1 ; ///<
- UINT32 ReceivedSystemError:1 ; ///<
- UINT32 ParityErrorDetected:1 ; ///<
+ UINT32 MainPllOpFreqId:6 ; ///<
+ UINT32 MainPllOpFreqIdEn:1 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 ClkRampHystSel:4 ; ///<
+ UINT32 NbOutHyst:4 ; ///<
+ UINT32 DisNclkGatingIdle:1 ; ///<
+ UINT32 ClockGatingEnDram:1 ; ///<
+ UINT32 Reserved_18_18:1 ; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x1C_STRUCT;
+} D18F3xD4_STRUCT;
-// **** DxF0x20 Register Definition ****
+// **** D18F3xD8 Register Definition ****
// Address
-#define DxF0x20_ADDRESS 0x20
+#define D18F3xD8_ADDRESS 0xd8
// Type
-#define DxF0x20_TYPE TYPE_D4F0
+#define D18F3xD8_TYPE TYPE_D18F3
// Field Data
-#define DxF0x20_Reserved_3_0_OFFSET 0
-#define DxF0x20_Reserved_3_0_WIDTH 4
-#define DxF0x20_Reserved_3_0_MASK 0xf
-#define DxF0x20_MemBase_OFFSET 4
-#define DxF0x20_MemBase_WIDTH 12
-#define DxF0x20_MemBase_MASK 0xfff0
-#define DxF0x20_Reserved_19_16_OFFSET 16
-#define DxF0x20_Reserved_19_16_WIDTH 4
-#define DxF0x20_Reserved_19_16_MASK 0xf0000
-#define DxF0x20_MemLimit_OFFSET 20
-#define DxF0x20_MemLimit_WIDTH 12
-#define DxF0x20_MemLimit_MASK 0xfff00000
+#define D18F3xD8_Reserved_3_0_OFFSET 0
+#define D18F3xD8_Reserved_3_0_WIDTH 4
+#define D18F3xD8_Reserved_3_0_MASK 0xf
+#define D18F3xD8_VSRampSlamTime_OFFSET 4
+#define D18F3xD8_VSRampSlamTime_WIDTH 3
+#define D18F3xD8_VSRampSlamTime_MASK 0x70
+#define D18F3xD8_ExtndTriDly_OFFSET 7
+#define D18F3xD8_ExtndTriDly_WIDTH 5
+#define D18F3xD8_ExtndTriDly_MASK 0xf80
+#define D18F3xD8_Reserved_31_12_OFFSET 12
+#define D18F3xD8_Reserved_31_12_WIDTH 20
+#define D18F3xD8_Reserved_31_12_MASK 0xfffff000
-/// DxF0x20
+/// D18F3xD8
typedef union {
struct { ///<
UINT32 Reserved_3_0:4 ; ///<
- UINT32 MemBase:12; ///<
- UINT32 Reserved_19_16:4 ; ///<
- UINT32 MemLimit:12; ///<
+ UINT32 VSRampSlamTime:3 ; ///<
+ UINT32 ExtndTriDly:5 ; ///<
+ UINT32 Reserved_31_12:20; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x20_STRUCT;
+} D18F3xD8_STRUCT;
-// **** DxF0x24 Register Definition ****
+// **** D18F3xDC Register Definition ****
// Address
-#define DxF0x24_ADDRESS 0x24
+#define D18F3xDC_ADDRESS 0xdc
// Type
-#define DxF0x24_TYPE TYPE_D4F0
+#define D18F3xDC_TYPE TYPE_D18F3
// Field Data
-#define DxF0x24_PrefMemBaseR_OFFSET 0
-#define DxF0x24_PrefMemBaseR_WIDTH 4
-#define DxF0x24_PrefMemBaseR_MASK 0xf
-#define DxF0x24_PrefMemBase_31_20__OFFSET 4
-#define DxF0x24_PrefMemBase_31_20__WIDTH 12
-#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0
-#define DxF0x24_PrefMemLimitR_OFFSET 16
-#define DxF0x24_PrefMemLimitR_WIDTH 4
-#define DxF0x24_PrefMemLimitR_MASK 0xf0000
-#define DxF0x24_PrefMemLimit_OFFSET 20
-#define DxF0x24_PrefMemLimit_WIDTH 12
-#define DxF0x24_PrefMemLimit_MASK 0xfff00000
-
-/// DxF0x24
-typedef union {
- struct { ///<
- UINT32 PrefMemBaseR:4 ; ///<
- UINT32 PrefMemBase_31_20_:12; ///<
- UINT32 PrefMemLimitR:4 ; ///<
- UINT32 PrefMemLimit:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x24_STRUCT;
+#define D18F3xDC_Reserved_7_0_OFFSET 0
+#define D18F3xDC_Reserved_7_0_WIDTH 8
+#define D18F3xDC_Reserved_7_0_MASK 0xff
+#define D18F3xDC_PstateMaxVal_OFFSET 8
+#define D18F3xDC_PstateMaxVal_WIDTH 3
+#define D18F3xDC_PstateMaxVal_MASK 0x700
+#define D18F3xDC_Reserved_11_11_OFFSET 11
+#define D18F3xDC_Reserved_11_11_WIDTH 1
+#define D18F3xDC_Reserved_11_11_MASK 0x800
+#define D18F3xDC_NbPs0Vid_OFFSET 12
+#define D18F3xDC_NbPs0Vid_WIDTH 7
+#define D18F3xDC_NbPs0Vid_MASK 0x7f000
+#define D18F3xDC_NclkFreqDone_OFFSET 19
+#define D18F3xDC_NclkFreqDone_WIDTH 1
+#define D18F3xDC_NclkFreqDone_MASK 0x80000
+#define D18F3xDC_NbPs0NclkDiv_OFFSET 20
+#define D18F3xDC_NbPs0NclkDiv_WIDTH 7
+#define D18F3xDC_NbPs0NclkDiv_MASK 0x7f00000
+#define D18F3xDC_NbClockGateHyst_OFFSET 27
+#define D18F3xDC_NbClockGateHyst_WIDTH 3
+#define D18F3xDC_NbClockGateHyst_MASK 0x38000000
+#define D18F3xDC_NbClockGateEn_OFFSET 30
+#define D18F3xDC_NbClockGateEn_WIDTH 1
+#define D18F3xDC_NbClockGateEn_MASK 0x40000000
+#define D18F3xDC_CnbCifClockGateEn_OFFSET 31
+#define D18F3xDC_CnbCifClockGateEn_WIDTH 1
+#define D18F3xDC_CnbCifClockGateEn_MASK 0x80000000
-// **** DxF0x28 Register Definition ****
+/// D18F3xDC
+typedef union {
+ struct { ///<
+ UINT32 Reserved_7_0:8 ; ///<
+ UINT32 PstateMaxVal:3 ; ///<
+ UINT32 Reserved_11_11:1 ; ///<
+ UINT32 NbPs0Vid:7 ; ///<
+ UINT32 NclkFreqDone:1 ; ///<
+ UINT32 NbPs0NclkDiv:7 ; ///<
+ UINT32 NbClockGateHyst:3 ; ///<
+ UINT32 NbClockGateEn:1 ; ///<
+ UINT32 CnbCifClockGateEn:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F3xDC_STRUCT;
+
+// **** D18F3x15C Register Definition ****
// Address
-#define DxF0x28_ADDRESS 0x28
+#define D18F3x15C_ADDRESS 0x15c
// Type
-#define DxF0x28_TYPE TYPE_D4F0
+#define D18F3x15C_TYPE TYPE_D18F3
// Field Data
-#define DxF0x28_PrefMemBase_63_32__OFFSET 0
-#define DxF0x28_PrefMemBase_63_32__WIDTH 32
-#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff
+#define D18F3x15C_SclkVidLevel0_OFFSET 0
+#define D18F3x15C_SclkVidLevel0_WIDTH 7
+#define D18F3x15C_SclkVidLevel0_MASK 0x7f
+#define D18F3x15C_Reserved_7_7_OFFSET 7
+#define D18F3x15C_Reserved_7_7_WIDTH 1
+#define D18F3x15C_Reserved_7_7_MASK 0x80
+#define D18F3x15C_SclkVidLevel1_OFFSET 8
+#define D18F3x15C_SclkVidLevel1_WIDTH 7
+#define D18F3x15C_SclkVidLevel1_MASK 0x7f00
+#define D18F3x15C_Reserved_15_15_OFFSET 15
+#define D18F3x15C_Reserved_15_15_WIDTH 1
+#define D18F3x15C_Reserved_15_15_MASK 0x8000
+#define D18F3x15C_SclkVidLevel2_OFFSET 16
+#define D18F3x15C_SclkVidLevel2_WIDTH 7
+#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000
+#define D18F3x15C_Reserved_23_23_OFFSET 23
+#define D18F3x15C_Reserved_23_23_WIDTH 1
+#define D18F3x15C_Reserved_23_23_MASK 0x800000
+#define D18F3x15C_SclkVidLevel3_OFFSET 24
+#define D18F3x15C_SclkVidLevel3_WIDTH 7
+#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000
+#define D18F3x15C_Reserved_31_31_OFFSET 31
+#define D18F3x15C_Reserved_31_31_WIDTH 1
+#define D18F3x15C_Reserved_31_31_MASK 0x80000000
-/// DxF0x28
+/// D18F3x15C
typedef union {
struct { ///<
- UINT32 PrefMemBase_63_32_:32; ///<
+ UINT32 SclkVidLevel0:7 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 SclkVidLevel1:7 ; ///<
+ UINT32 Reserved_15_15:1 ; ///<
+ UINT32 SclkVidLevel2:7 ; ///<
+ UINT32 Reserved_23_23:1 ; ///<
+ UINT32 SclkVidLevel3:7 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x28_STRUCT;
+} D18F3x15C_STRUCT;
-// **** DxF0x2C Register Definition ****
+// **** D18F3x17C Register Definition ****
// Address
-#define DxF0x2C_ADDRESS 0x2c
+#define D18F3x17C_ADDRESS 0x17c
// Type
-#define DxF0x2C_TYPE TYPE_D4F0
+#define D18F3x17C_TYPE TYPE_D18F3
// Field Data
-#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0
-#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32
-#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff
+#define D18F3x17C_HiPriPBC_OFFSET 0
+#define D18F3x17C_HiPriPBC_WIDTH 6
+#define D18F3x17C_HiPriPBC_MASK 0x3f
+#define D18F3x17C_Reserved_7_6_OFFSET 6
+#define D18F3x17C_Reserved_7_6_WIDTH 2
+#define D18F3x17C_Reserved_7_6_MASK 0xc0
+#define D18F3x17C_HiPriNPBC_OFFSET 8
+#define D18F3x17C_HiPriNPBC_WIDTH 6
+#define D18F3x17C_HiPriNPBC_MASK 0x3f00
+#define D18F3x17C_Reserved_31_14_OFFSET 14
+#define D18F3x17C_Reserved_31_14_WIDTH 18
+#define D18F3x17C_Reserved_31_14_MASK 0xffffc000
-/// DxF0x2C
+/// D18F3x17C
typedef union {
struct { ///<
- UINT32 PrefMemLimit_63_32_:32; ///<
+ UINT32 HiPriPBC:6 ; ///<
+ UINT32 Reserved_7_6:2 ; ///<
+ UINT32 HiPriNPBC:6 ; ///<
+ UINT32 Reserved_31_14:18; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x2C_STRUCT;
+} D18F3x17C_STRUCT;
-// **** DxF0x30 Register Definition ****
+// **** D18F4x12C Register Definition ****
// Address
-#define DxF0x30_ADDRESS 0x30
+#define D18F4x12C_ADDRESS 0x12c
// Type
-#define DxF0x30_TYPE TYPE_D4F0
+#define D18F4x12C_TYPE TYPE_D18F4
// Field Data
-#define DxF0x30_IOBase_31_16__OFFSET 0
-#define DxF0x30_IOBase_31_16__WIDTH 16
-#define DxF0x30_IOBase_31_16__MASK 0xffff
-#define DxF0x30_IOLimit_31_16__OFFSET 16
-#define DxF0x30_IOLimit_31_16__WIDTH 16
-#define DxF0x30_IOLimit_31_16__MASK 0xffff0000
+#define D18F4x12C_C6Base_35_24__OFFSET 0
+#define D18F4x12C_C6Base_35_24__WIDTH 12
+#define D18F4x12C_C6Base_35_24__MASK 0xfff
+#define D18F4x12C_Reserved_31_12_OFFSET 12
+#define D18F4x12C_Reserved_31_12_WIDTH 20
+#define D18F4x12C_Reserved_31_12_MASK 0xfffff000
-/// DxF0x30
+/// D18F4x12C
typedef union {
struct { ///<
- UINT32 IOBase_31_16_:16; ///<
- UINT32 IOLimit_31_16_:16; ///<
+ UINT32 C6Base_35_24_:12; ///<
+ UINT32 Reserved_31_12:20; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x30_STRUCT;
+} D18F4x12C_STRUCT;
-// **** DxF0x34 Register Definition ****
+// **** D18F4x15C Register Definition ****
// Address
-#define DxF0x34_ADDRESS 0x34
+#define D18F4x15C_ADDRESS 0x15c
// Type
-#define DxF0x34_TYPE TYPE_D4F0
+#define D18F4x15C_TYPE TYPE_D18F4
// Field Data
-#define DxF0x34_CapPtr_OFFSET 0
-#define DxF0x34_CapPtr_WIDTH 8
-#define DxF0x34_CapPtr_MASK 0xff
-#define DxF0x34_Reserved_31_8_OFFSET 8
-#define DxF0x34_Reserved_31_8_WIDTH 24
-#define DxF0x34_Reserved_31_8_MASK 0xffffff00
+#define D18F4x15C_BoostSrc_OFFSET 0
+#define D18F4x15C_BoostSrc_WIDTH 2
+#define D18F4x15C_BoostSrc_MASK 0x3
+#define D18F4x15C_NumBoostStates_OFFSET 2
+#define D18F4x15C_NumBoostStates_WIDTH 3
+#define D18F4x15C_NumBoostStates_MASK 0x1c
+#define D18F4x15C_Reserved_28_5_OFFSET 5
+#define D18F4x15C_Reserved_28_5_WIDTH 24
+#define D18F4x15C_Reserved_28_5_MASK 0x1fffffe0
+#define D18F4x15C_BoostEnAllCores_OFFSET 29
+#define D18F4x15C_BoostEnAllCores_WIDTH 1
+#define D18F4x15C_BoostEnAllCores_MASK 0x20000000
+#define D18F4x15C_Reserved_31_30_OFFSET 30
+#define D18F4x15C_Reserved_31_30_WIDTH 2
+#define D18F4x15C_Reserved_31_30_MASK 0xc0000000
-/// DxF0x34
+/// D18F4x15C
typedef union {
struct { ///<
- UINT32 CapPtr:8 ; ///<
- UINT32 Reserved_31_8:24; ///<
+ UINT32 BoostSrc:2 ; ///<
+ UINT32 NumBoostStates:3 ; ///<
+ UINT32 Reserved_28_5:24; ///<
+ UINT32 BoostEnAllCores:1 ; ///<
+ UINT32 Reserved_31_30:2 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x34_STRUCT;
+} D18F4x15C_STRUCT;
-// **** DxF0x3C Register Definition ****
+// **** D18F4x164 Register Definition ****
// Address
-#define DxF0x3C_ADDRESS 0x3c
+#define D18F4x164_ADDRESS 0x164
// Type
-#define DxF0x3C_TYPE TYPE_D4F0
+#define D18F4x164_TYPE TYPE_D18F4
// Field Data
-#define DxF0x3C_IntLine_OFFSET 0
-#define DxF0x3C_IntLine_WIDTH 8
-#define DxF0x3C_IntLine_MASK 0xff
-#define DxF0x3C_IntPin_OFFSET 8
-#define DxF0x3C_IntPin_WIDTH 3
-#define DxF0x3C_IntPin_MASK 0x700
-#define DxF0x3C_Reserved_15_11_OFFSET 11
-#define DxF0x3C_Reserved_15_11_WIDTH 5
-#define DxF0x3C_Reserved_15_11_MASK 0xf800
-#define DxF0x3C_ParityResponseEn_OFFSET 16
-#define DxF0x3C_ParityResponseEn_WIDTH 1
-#define DxF0x3C_ParityResponseEn_MASK 0x10000
-#define DxF0x3C_SerrEn_OFFSET 17
-#define DxF0x3C_SerrEn_WIDTH 1
-#define DxF0x3C_SerrEn_MASK 0x20000
-#define DxF0x3C_IsaEn_OFFSET 18
-#define DxF0x3C_IsaEn_WIDTH 1
-#define DxF0x3C_IsaEn_MASK 0x40000
-#define DxF0x3C_VgaEn_OFFSET 19
-#define DxF0x3C_VgaEn_WIDTH 1
-#define DxF0x3C_VgaEn_MASK 0x80000
-#define DxF0x3C_Vga16En_OFFSET 20
-#define DxF0x3C_Vga16En_WIDTH 1
-#define DxF0x3C_Vga16En_MASK 0x100000
-#define DxF0x3C_MasterAbortMode_OFFSET 21
-#define DxF0x3C_MasterAbortMode_WIDTH 1
-#define DxF0x3C_MasterAbortMode_MASK 0x200000
-#define DxF0x3C_SecondaryBusReset_OFFSET 22
-#define DxF0x3C_SecondaryBusReset_WIDTH 1
-#define DxF0x3C_SecondaryBusReset_MASK 0x400000
-#define DxF0x3C_FastB2BCap_OFFSET 23
-#define DxF0x3C_FastB2BCap_WIDTH 1
-#define DxF0x3C_FastB2BCap_MASK 0x800000
-#define DxF0x3C_Reserved_31_24_OFFSET 24
-#define DxF0x3C_Reserved_31_24_WIDTH 8
-#define DxF0x3C_Reserved_31_24_MASK 0xff000000
+#define D18F4x164_FixedErrata_OFFSET 0
+#define D18F4x164_FixedErrata_WIDTH 32
+#define D18F4x164_FixedErrata_MASK 0xffffffff
-/// DxF0x3C
+/// D18F4x164
typedef union {
struct { ///<
- UINT32 IntLine:8 ; ///<
- UINT32 IntPin:3 ; ///<
- UINT32 Reserved_15_11:5 ; ///<
- UINT32 ParityResponseEn:1 ; ///<
- UINT32 SerrEn:1 ; ///<
- UINT32 IsaEn:1 ; ///<
- UINT32 VgaEn:1 ; ///<
- UINT32 Vga16En:1 ; ///<
- UINT32 MasterAbortMode:1 ; ///<
- UINT32 SecondaryBusReset:1 ; ///<
- UINT32 FastB2BCap:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
+ UINT32 FixedErrata:32; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x3C_STRUCT;
+} D18F4x164_STRUCT;
-// **** DxF0x50 Register Definition ****
+// **** D18F6x90 Register Definition ****
// Address
-#define DxF0x50_ADDRESS 0x50
+#define D18F6x90_ADDRESS 0x90
// Type
-#define DxF0x50_TYPE TYPE_D4F0
+#define D18F6x90_TYPE TYPE_D18F6
// Field Data
-#define DxF0x50_CapID_OFFSET 0
-#define DxF0x50_CapID_WIDTH 8
-#define DxF0x50_CapID_MASK 0xff
-#define DxF0x50_NextPtr_OFFSET 8
-#define DxF0x50_NextPtr_WIDTH 8
-#define DxF0x50_NextPtr_MASK 0xff00
-#define DxF0x50_Version_OFFSET 16
-#define DxF0x50_Version_WIDTH 3
-#define DxF0x50_Version_MASK 0x70000
-#define DxF0x50_PmeClock_OFFSET 19
-#define DxF0x50_PmeClock_WIDTH 1
-#define DxF0x50_PmeClock_MASK 0x80000
-#define DxF0x50_Reserved_20_20_OFFSET 20
-#define DxF0x50_Reserved_20_20_WIDTH 1
-#define DxF0x50_Reserved_20_20_MASK 0x100000
-#define DxF0x50_DevSpecificInit_OFFSET 21
-#define DxF0x50_DevSpecificInit_WIDTH 1
-#define DxF0x50_DevSpecificInit_MASK 0x200000
-#define DxF0x50_AuxCurrent_OFFSET 22
-#define DxF0x50_AuxCurrent_WIDTH 3
-#define DxF0x50_AuxCurrent_MASK 0x1c00000
-#define DxF0x50_D1Support_OFFSET 25
-#define DxF0x50_D1Support_WIDTH 1
-#define DxF0x50_D1Support_MASK 0x2000000
-#define DxF0x50_D2Support_OFFSET 26
-#define DxF0x50_D2Support_WIDTH 1
-#define DxF0x50_D2Support_MASK 0x4000000
-#define DxF0x50_PmeSupport_OFFSET 27
-#define DxF0x50_PmeSupport_WIDTH 5
-#define DxF0x50_PmeSupport_MASK 0xf8000000
+#define D18F6x90_NbPs1NclkDiv_OFFSET 0
+#define D18F6x90_NbPs1NclkDiv_WIDTH 7
+#define D18F6x90_NbPs1NclkDiv_MASK 0x7f
+#define D18F6x90_Reserved_7_7_OFFSET 7
+#define D18F6x90_Reserved_7_7_WIDTH 1
+#define D18F6x90_Reserved_7_7_MASK 0x80
+#define D18F6x90_NbPs1Vid_OFFSET 8
+#define D18F6x90_NbPs1Vid_WIDTH 7
+#define D18F6x90_NbPs1Vid_MASK 0x7f00
+#define D18F6x90_Reserved_15_15_OFFSET 15
+#define D18F6x90_Reserved_15_15_WIDTH 1
+#define D18F6x90_Reserved_15_15_MASK 0x8000
+#define D18F6x90_NbPs1GnbSlowIgn_OFFSET 16
+#define D18F6x90_NbPs1GnbSlowIgn_WIDTH 1
+#define D18F6x90_NbPs1GnbSlowIgn_MASK 0x10000
+#define D18F6x90_Reserved_19_17_OFFSET 17
+#define D18F6x90_Reserved_19_17_WIDTH 3
+#define D18F6x90_Reserved_19_17_MASK 0xe0000
+#define D18F6x90_NbPsLock_OFFSET 20
+#define D18F6x90_NbPsLock_WIDTH 1
+#define D18F6x90_NbPsLock_MASK 0x100000
+#define D18F6x90_Reserved_27_21_OFFSET 21
+#define D18F6x90_Reserved_27_21_WIDTH 7
+#define D18F6x90_Reserved_27_21_MASK 0xfe00000
+#define D18F6x90_NbPsForceReq_OFFSET 28
+#define D18F6x90_NbPsForceReq_WIDTH 1
+#define D18F6x90_NbPsForceReq_MASK 0x10000000
+#define D18F6x90_NbPsForceSel_OFFSET 29
+#define D18F6x90_NbPsForceSel_WIDTH 1
+#define D18F6x90_NbPsForceSel_MASK 0x20000000
+#define D18F6x90_NbPsCtrlDis_OFFSET 30
+#define D18F6x90_NbPsCtrlDis_WIDTH 1
+#define D18F6x90_NbPsCtrlDis_MASK 0x40000000
+#define D18F6x90_NbPsCap_OFFSET 31
+#define D18F6x90_NbPsCap_WIDTH 1
+#define D18F6x90_NbPsCap_MASK 0x80000000
-/// DxF0x50
+/// D18F6x90
typedef union {
struct { ///<
- UINT32 CapID:8 ; ///<
- UINT32 NextPtr:8 ; ///<
- UINT32 Version:3 ; ///<
- UINT32 PmeClock:1 ; ///<
- UINT32 Reserved_20_20:1 ; ///<
- UINT32 DevSpecificInit:1 ; ///<
- UINT32 AuxCurrent:3 ; ///<
- UINT32 D1Support:1 ; ///<
- UINT32 D2Support:1 ; ///<
- UINT32 PmeSupport:5 ; ///<
+ UINT32 NbPs1NclkDiv:7 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 NbPs1Vid:7 ; ///<
+ UINT32 Reserved_15_15:1 ; ///<
+ UINT32 NbPs1GnbSlowIgn:1 ; ///<
+ UINT32 Reserved_19_17:3 ; ///<
+ UINT32 NbPsLock:1 ; ///<
+ UINT32 Reserved_27_21:7 ; ///<
+ UINT32 NbPsForceReq:1 ; ///<
+ UINT32 NbPsForceSel:1 ; ///<
+ UINT32 NbPsCtrlDis:1 ; ///<
+ UINT32 NbPsCap:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x50_STRUCT;
+} D18F6x90_STRUCT;
-// **** DxF0x54 Register Definition ****
+// **** D18F6x94 Register Definition ****
// Address
-#define DxF0x54_ADDRESS 0x54
+#define D18F6x94_ADDRESS 0x94
// Type
-#define DxF0x54_TYPE TYPE_D4F0
+#define D18F6x94_TYPE TYPE_D18F6
// Field Data
-#define DxF0x54_PowerState_OFFSET 0
-#define DxF0x54_PowerState_WIDTH 2
-#define DxF0x54_PowerState_MASK 0x3
-#define DxF0x54_Reserved_2_2_OFFSET 2
-#define DxF0x54_Reserved_2_2_WIDTH 1
-#define DxF0x54_Reserved_2_2_MASK 0x4
-#define DxF0x54_NoSoftReset_OFFSET 3
-#define DxF0x54_NoSoftReset_WIDTH 1
-#define DxF0x54_NoSoftReset_MASK 0x8
-#define DxF0x54_Reserved_7_4_OFFSET 4
-#define DxF0x54_Reserved_7_4_WIDTH 4
-#define DxF0x54_Reserved_7_4_MASK 0xf0
-#define DxF0x54_PmeEn_OFFSET 8
-#define DxF0x54_PmeEn_WIDTH 1
-#define DxF0x54_PmeEn_MASK 0x100
-#define DxF0x54_DataSelect_OFFSET 9
-#define DxF0x54_DataSelect_WIDTH 4
-#define DxF0x54_DataSelect_MASK 0x1e00
-#define DxF0x54_DataScale_OFFSET 13
-#define DxF0x54_DataScale_WIDTH 2
-#define DxF0x54_DataScale_MASK 0x6000
-#define DxF0x54_PmeStatus_OFFSET 15
-#define DxF0x54_PmeStatus_WIDTH 1
-#define DxF0x54_PmeStatus_MASK 0x8000
-#define DxF0x54_Reserved_21_16_OFFSET 16
-#define DxF0x54_Reserved_21_16_WIDTH 6
-#define DxF0x54_Reserved_21_16_MASK 0x3f0000
-#define DxF0x54_B2B3Support_OFFSET 22
-#define DxF0x54_B2B3Support_WIDTH 1
-#define DxF0x54_B2B3Support_MASK 0x400000
-#define DxF0x54_BusPwrEn_OFFSET 23
-#define DxF0x54_BusPwrEn_WIDTH 1
-#define DxF0x54_BusPwrEn_MASK 0x800000
-#define DxF0x54_PmeData_OFFSET 24
-#define DxF0x54_PmeData_WIDTH 8
-#define DxF0x54_PmeData_MASK 0xff000000
+#define D18F6x94_CpuPstateThr_OFFSET 0
+#define D18F6x94_CpuPstateThr_WIDTH 3
+#define D18F6x94_CpuPstateThr_MASK 0x7
+#define D18F6x94_CpuPstateThrEn_OFFSET 3
+#define D18F6x94_CpuPstateThrEn_WIDTH 1
+#define D18F6x94_CpuPstateThrEn_MASK 0x8
+#define D18F6x94_NbPsNoTransOnDma_OFFSET 4
+#define D18F6x94_NbPsNoTransOnDma_WIDTH 1
+#define D18F6x94_NbPsNoTransOnDma_MASK 0x10
+#define D18F6x94_Reserved_19_5_OFFSET 5
+#define D18F6x94_Reserved_19_5_WIDTH 15
+#define D18F6x94_Reserved_19_5_MASK 0xfffe0
+#define D18F6x94_NbPsNonC0Timer_OFFSET 20
+#define D18F6x94_NbPsNonC0Timer_WIDTH 3
+#define D18F6x94_NbPsNonC0Timer_MASK 0x700000
+#define D18F6x94_NbPsC0Timer_OFFSET 23
+#define D18F6x94_NbPsC0Timer_WIDTH 3
+#define D18F6x94_NbPsC0Timer_MASK 0x3800000
+#define D18F6x94_NbPs1ResTmrMin_OFFSET 26
+#define D18F6x94_NbPs1ResTmrMin_WIDTH 3
+#define D18F6x94_NbPs1ResTmrMin_MASK 0x1c000000
+#define D18F6x94_NbPs0ResTmrMin_OFFSET 29
+#define D18F6x94_NbPs0ResTmrMin_WIDTH 3
+#define D18F6x94_NbPs0ResTmrMin_MASK 0xe0000000
-/// DxF0x54
+/// D18F6x94
typedef union {
struct { ///<
- UINT32 PowerState:2 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 NoSoftReset:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 PmeEn:1 ; ///<
- UINT32 DataSelect:4 ; ///<
- UINT32 DataScale:2 ; ///<
- UINT32 PmeStatus:1 ; ///<
- UINT32 Reserved_21_16:6 ; ///<
- UINT32 B2B3Support:1 ; ///<
- UINT32 BusPwrEn:1 ; ///<
- UINT32 PmeData:8 ; ///<
+ UINT32 CpuPstateThr:3 ; ///<
+ UINT32 CpuPstateThrEn:1 ; ///<
+ UINT32 NbPsNoTransOnDma:1 ; ///<
+ UINT32 Reserved_19_5:15; ///<
+ UINT32 NbPsNonC0Timer:3 ; ///<
+ UINT32 NbPsC0Timer:3 ; ///<
+ UINT32 NbPs1ResTmrMin:3 ; ///<
+ UINT32 NbPs0ResTmrMin:3 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x54_STRUCT;
+} D18F6x94_STRUCT;
-// **** DxF0x58 Register Definition ****
+// **** D18F6x98 Register Definition ****
// Address
-#define DxF0x58_ADDRESS 0x58
+#define D18F6x98_ADDRESS 0x98
// Type
-#define DxF0x58_TYPE TYPE_D4F0
+#define D18F6x98_TYPE TYPE_D18F6
// Field Data
-#define DxF0x58_CapID_OFFSET 0
-#define DxF0x58_CapID_WIDTH 8
-#define DxF0x58_CapID_MASK 0xff
-#define DxF0x58_NextPtr_OFFSET 8
-#define DxF0x58_NextPtr_WIDTH 8
-#define DxF0x58_NextPtr_MASK 0xff00
-#define DxF0x58_Version_OFFSET 16
-#define DxF0x58_Version_WIDTH 4
-#define DxF0x58_Version_MASK 0xf0000
-#define DxF0x58_DeviceType_OFFSET 20
-#define DxF0x58_DeviceType_WIDTH 4
-#define DxF0x58_DeviceType_MASK 0xf00000
-#define DxF0x58_SlotImplemented_OFFSET 24
-#define DxF0x58_SlotImplemented_WIDTH 1
-#define DxF0x58_SlotImplemented_MASK 0x1000000
-#define DxF0x58_IntMessageNum_OFFSET 25
-#define DxF0x58_IntMessageNum_WIDTH 5
-#define DxF0x58_IntMessageNum_MASK 0x3e000000
-#define DxF0x58_Reserved_31_30_OFFSET 30
-#define DxF0x58_Reserved_31_30_WIDTH 2
-#define DxF0x58_Reserved_31_30_MASK 0xc0000000
+#define D18F6x98_NbPsTransInFlight_OFFSET 0
+#define D18F6x98_NbPsTransInFlight_WIDTH 1
+#define D18F6x98_NbPsTransInFlight_MASK 0x1
+#define D18F6x98_NbPs1ActSts_OFFSET 1
+#define D18F6x98_NbPs1ActSts_WIDTH 1
+#define D18F6x98_NbPs1ActSts_MASK 0x2
+#define D18F6x98_NbPs1Act_OFFSET 2
+#define D18F6x98_NbPs1Act_WIDTH 1
+#define D18F6x98_NbPs1Act_MASK 0x4
+#define D18F6x98_Reserved_29_3_OFFSET 3
+#define D18F6x98_Reserved_29_3_WIDTH 27
+#define D18F6x98_Reserved_29_3_MASK 0x3ffffff8
+#define D18F6x98_NbPsCsrAccSel_OFFSET 30
+#define D18F6x98_NbPsCsrAccSel_WIDTH 1
+#define D18F6x98_NbPsCsrAccSel_MASK 0x40000000
+#define D18F6x98_NbPsDbgEn_OFFSET 31
+#define D18F6x98_NbPsDbgEn_WIDTH 1
+#define D18F6x98_NbPsDbgEn_MASK 0x80000000
-/// DxF0x58
+/// D18F6x98
typedef union {
struct { ///<
- UINT32 CapID:8 ; ///<
- UINT32 NextPtr:8 ; ///<
- UINT32 Version:4 ; ///<
- UINT32 DeviceType:4 ; ///<
- UINT32 SlotImplemented:1 ; ///<
- UINT32 IntMessageNum:5 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
+ UINT32 NbPsTransInFlight:1 ; ///<
+ UINT32 NbPs1ActSts:1 ; ///<
+ UINT32 NbPs1Act:1 ; ///<
+ UINT32 Reserved_29_3:27; ///<
+ UINT32 NbPsCsrAccSel:1 ; ///<
+ UINT32 NbPsDbgEn:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} DxF0x58_STRUCT;
+} D18F6x98_STRUCT;
-// **** DxF0x5C Register Definition ****
+// **** D18F6x9C Register Definition ****
// Address
-#define DxF0x5C_ADDRESS 0x5c
+#define D18F6x9C_ADDRESS 0x9c
// Type
-#define DxF0x5C_TYPE TYPE_D4F0
+#define D18F6x9C_TYPE TYPE_D18F6
// Field Data
-#define DxF0x5C_MaxPayloadSupport_OFFSET 0
-#define DxF0x5C_MaxPayloadSupport_WIDTH 3
-#define DxF0x5C_MaxPayloadSupport_MASK 0x7
-#define DxF0x5C_PhantomFunc_OFFSET 3
-#define DxF0x5C_PhantomFunc_WIDTH 2
-#define DxF0x5C_PhantomFunc_MASK 0x18
-#define DxF0x5C_ExtendedTag_OFFSET 5
-#define DxF0x5C_ExtendedTag_WIDTH 1
-#define DxF0x5C_ExtendedTag_MASK 0x20
-#define DxF0x5C_L0SAcceptableLatency_OFFSET 6
-#define DxF0x5C_L0SAcceptableLatency_WIDTH 3
-#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0
-#define DxF0x5C_L1AcceptableLatency_OFFSET 9
-#define DxF0x5C_L1AcceptableLatency_WIDTH 3
-#define DxF0x5C_L1AcceptableLatency_MASK 0xe00
-#define DxF0x5C_Reserved_14_12_OFFSET 12
-#define DxF0x5C_Reserved_14_12_WIDTH 3
-#define DxF0x5C_Reserved_14_12_MASK 0x7000
-#define DxF0x5C_RoleBasedErrReporting_OFFSET 15
-#define DxF0x5C_RoleBasedErrReporting_WIDTH 1
-#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000
-#define DxF0x5C_Reserved_17_16_OFFSET 16
-#define DxF0x5C_Reserved_17_16_WIDTH 2
-#define DxF0x5C_Reserved_17_16_MASK 0x30000
-#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18
-#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8
-#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000
-#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26
-#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2
-#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000
-#define DxF0x5C_FlrCapable_OFFSET 28
-#define DxF0x5C_FlrCapable_WIDTH 1
-#define DxF0x5C_FlrCapable_MASK 0x10000000
-#define DxF0x5C_Reserved_31_29_OFFSET 29
+#define D18F6x9C_NclkRedDiv_OFFSET 0
+#define D18F6x9C_NclkRedDiv_WIDTH 7
+#define D18F6x9C_NclkRedDiv_MASK 0x7f
+#define D18F6x9C_NclkRedSelfRefrAlways_OFFSET 7
+#define D18F6x9C_NclkRedSelfRefrAlways_WIDTH 1
+#define D18F6x9C_NclkRedSelfRefrAlways_MASK 0x80
+#define D18F6x9C_NclkRampWithDllRelock_OFFSET 8
+#define D18F6x9C_NclkRampWithDllRelock_WIDTH 1
+#define D18F6x9C_NclkRampWithDllRelock_MASK 0x100
+#define D18F6x9C_Reserved_31_9_OFFSET 9
+#define D18F6x9C_Reserved_31_9_WIDTH 23
+#define D18F6x9C_Reserved_31_9_MASK 0xfffffe00
+
+/// D18F6x9C
+typedef union {
+ struct { ///<
+ UINT32 NclkRedDiv:7 ; ///<
+ UINT32 NclkRedSelfRefrAlways:1 ; ///<
+ UINT32 NclkRampWithDllRelock:1 ; ///<
+ UINT32 Reserved_31_9:23; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F6x9C_STRUCT;
+
+// **** DxF0x00 Register Definition ****
+// Address
+#define DxF0x00_ADDRESS 0x0
+
+// Type
+#define DxF0x00_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x00_VendorID_OFFSET 0
+#define DxF0x00_VendorID_WIDTH 16
+#define DxF0x00_VendorID_MASK 0xffff
+#define DxF0x00_DeviceID_OFFSET 16
+#define DxF0x00_DeviceID_WIDTH 16
+#define DxF0x00_DeviceID_MASK 0xffff0000
+
+/// DxF0x00
+typedef union {
+ struct { ///<
+ UINT32 VendorID:16; ///<
+ UINT32 DeviceID:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x00_STRUCT;
+
+// **** DxF0x04 Register Definition ****
+// Address
+#define DxF0x04_ADDRESS 0x4
+
+// Type
+#define DxF0x04_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x04_IoAccessEn_OFFSET 0
+#define DxF0x04_IoAccessEn_WIDTH 1
+#define DxF0x04_IoAccessEn_MASK 0x1
+#define DxF0x04_MemAccessEn_OFFSET 1
+#define DxF0x04_MemAccessEn_WIDTH 1
+#define DxF0x04_MemAccessEn_MASK 0x2
+#define DxF0x04_BusMasterEn_OFFSET 2
+#define DxF0x04_BusMasterEn_WIDTH 1
+#define DxF0x04_BusMasterEn_MASK 0x4
+#define DxF0x04_SpecialCycleEn_OFFSET 3
+#define DxF0x04_SpecialCycleEn_WIDTH 1
+#define DxF0x04_SpecialCycleEn_MASK 0x8
+#define DxF0x04_MemWriteInvalidateEn_OFFSET 4
+#define DxF0x04_MemWriteInvalidateEn_WIDTH 1
+#define DxF0x04_MemWriteInvalidateEn_MASK 0x10
+#define DxF0x04_PalSnoopEn_OFFSET 5
+#define DxF0x04_PalSnoopEn_WIDTH 1
+#define DxF0x04_PalSnoopEn_MASK 0x20
+#define DxF0x04_ParityErrorEn_OFFSET 6
+#define DxF0x04_ParityErrorEn_WIDTH 1
+#define DxF0x04_ParityErrorEn_MASK 0x40
+#define DxF0x04_IdselStepping_OFFSET 7
+#define DxF0x04_IdselStepping_WIDTH 1
+#define DxF0x04_IdselStepping_MASK 0x80
+#define DxF0x04_SerrEn_OFFSET 8
+#define DxF0x04_SerrEn_WIDTH 1
+#define DxF0x04_SerrEn_MASK 0x100
+#define DxF0x04_FastB2BEn_OFFSET 9
+#define DxF0x04_FastB2BEn_WIDTH 1
+#define DxF0x04_FastB2BEn_MASK 0x200
+#define DxF0x04_IntDis_OFFSET 10
+#define DxF0x04_IntDis_WIDTH 1
+#define DxF0x04_IntDis_MASK 0x400
+#define DxF0x04_Reserved_18_11_OFFSET 11
+#define DxF0x04_Reserved_18_11_WIDTH 8
+#define DxF0x04_Reserved_18_11_MASK 0x7f800
+#define DxF0x04_IntStatus_OFFSET 19
+#define DxF0x04_IntStatus_WIDTH 1
+#define DxF0x04_IntStatus_MASK 0x80000
+#define DxF0x04_CapList_OFFSET 20
+#define DxF0x04_CapList_WIDTH 1
+#define DxF0x04_CapList_MASK 0x100000
+#define DxF0x04_PCI66En_OFFSET 21
+#define DxF0x04_PCI66En_WIDTH 1
+#define DxF0x04_PCI66En_MASK 0x200000
+#define DxF0x04_UDFEn_OFFSET 22
+#define DxF0x04_UDFEn_WIDTH 1
+#define DxF0x04_UDFEn_MASK 0x400000
+#define DxF0x04_FastBackCapable_OFFSET 23
+#define DxF0x04_FastBackCapable_WIDTH 1
+#define DxF0x04_FastBackCapable_MASK 0x800000
+#define DxF0x04_MasterDataPerr_OFFSET 24
+#define DxF0x04_MasterDataPerr_WIDTH 1
+#define DxF0x04_MasterDataPerr_MASK 0x1000000
+#define DxF0x04_DevselTiming_OFFSET 25
+#define DxF0x04_DevselTiming_WIDTH 2
+#define DxF0x04_DevselTiming_MASK 0x6000000
+#define DxF0x04_SignaledTargetAbort_OFFSET 27
+#define DxF0x04_SignaledTargetAbort_WIDTH 1
+#define DxF0x04_SignaledTargetAbort_MASK 0x8000000
+#define DxF0x04_ReceivedTargetAbort_OFFSET 28
+#define DxF0x04_ReceivedTargetAbort_WIDTH 1
+#define DxF0x04_ReceivedTargetAbort_MASK 0x10000000
+#define DxF0x04_ReceivedMasterAbort_OFFSET 29
+#define DxF0x04_ReceivedMasterAbort_WIDTH 1
+#define DxF0x04_ReceivedMasterAbort_MASK 0x20000000
+#define DxF0x04_SignaledSystemError_OFFSET 30
+#define DxF0x04_SignaledSystemError_WIDTH 1
+#define DxF0x04_SignaledSystemError_MASK 0x40000000
+#define DxF0x04_ParityErrorDetected_OFFSET 31
+#define DxF0x04_ParityErrorDetected_WIDTH 1
+#define DxF0x04_ParityErrorDetected_MASK 0x80000000
+
+/// DxF0x04
+typedef union {
+ struct { ///<
+ UINT32 IoAccessEn:1 ; ///<
+ UINT32 MemAccessEn:1 ; ///<
+ UINT32 BusMasterEn:1 ; ///<
+ UINT32 SpecialCycleEn:1 ; ///<
+ UINT32 MemWriteInvalidateEn:1 ; ///<
+ UINT32 PalSnoopEn:1 ; ///<
+ UINT32 ParityErrorEn:1 ; ///<
+ UINT32 IdselStepping:1 ; ///<
+ UINT32 SerrEn:1 ; ///<
+ UINT32 FastB2BEn:1 ; ///<
+ UINT32 IntDis:1 ; ///<
+ UINT32 Reserved_18_11:8 ; ///<
+ UINT32 IntStatus:1 ; ///<
+ UINT32 CapList:1 ; ///<
+ UINT32 PCI66En:1 ; ///<
+ UINT32 UDFEn:1 ; ///<
+ UINT32 FastBackCapable:1 ; ///<
+ UINT32 MasterDataPerr:1 ; ///<
+ UINT32 DevselTiming:2 ; ///<
+ UINT32 SignaledTargetAbort:1 ; ///<
+ UINT32 ReceivedTargetAbort:1 ; ///<
+ UINT32 ReceivedMasterAbort:1 ; ///<
+ UINT32 SignaledSystemError:1 ; ///<
+ UINT32 ParityErrorDetected:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x04_STRUCT;
+
+// **** DxF0x08 Register Definition ****
+// Address
+#define DxF0x08_ADDRESS 0x8
+
+// Type
+#define DxF0x08_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x08_RevID_OFFSET 0
+#define DxF0x08_RevID_WIDTH 8
+#define DxF0x08_RevID_MASK 0xff
+#define DxF0x08_ClassCode_OFFSET 8
+#define DxF0x08_ClassCode_WIDTH 24
+#define DxF0x08_ClassCode_MASK 0xffffff00
+
+/// DxF0x08
+typedef union {
+ struct { ///<
+ UINT32 RevID:8 ; ///<
+ UINT32 ClassCode:24; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x08_STRUCT;
+
+// **** DxF0x0C Register Definition ****
+// Address
+#define DxF0x0C_ADDRESS 0xc
+
+// Type
+#define DxF0x0C_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x0C_CacheLineSize_OFFSET 0
+#define DxF0x0C_CacheLineSize_WIDTH 8
+#define DxF0x0C_CacheLineSize_MASK 0xff
+#define DxF0x0C_LatencyTimer_OFFSET 8
+#define DxF0x0C_LatencyTimer_WIDTH 8
+#define DxF0x0C_LatencyTimer_MASK 0xff00
+#define DxF0x0C_HeaderTypeReg_OFFSET 16
+#define DxF0x0C_HeaderTypeReg_WIDTH 8
+#define DxF0x0C_HeaderTypeReg_MASK 0xff0000
+#define DxF0x0C_BIST_OFFSET 24
+#define DxF0x0C_BIST_WIDTH 8
+#define DxF0x0C_BIST_MASK 0xff000000
+
+/// DxF0x0C
+typedef union {
+ struct { ///<
+ UINT32 CacheLineSize:8 ; ///<
+ UINT32 LatencyTimer:8 ; ///<
+ UINT32 HeaderTypeReg:8 ; ///<
+ UINT32 BIST:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x0C_STRUCT;
+
+// **** DxF0x18 Register Definition ****
+// Address
+#define DxF0x18_ADDRESS 0x18
+
+// Type
+#define DxF0x18_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x18_PrimaryBus_OFFSET 0
+#define DxF0x18_PrimaryBus_WIDTH 8
+#define DxF0x18_PrimaryBus_MASK 0xff
+#define DxF0x18_SecondaryBus_OFFSET 8
+#define DxF0x18_SecondaryBus_WIDTH 8
+#define DxF0x18_SecondaryBus_MASK 0xff00
+#define DxF0x18_SubBusNumber_OFFSET 16
+#define DxF0x18_SubBusNumber_WIDTH 8
+#define DxF0x18_SubBusNumber_MASK 0xff0000
+#define DxF0x18_SecondaryLatencyTimer_OFFSET 24
+#define DxF0x18_SecondaryLatencyTimer_WIDTH 8
+#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000
+
+/// DxF0x18
+typedef union {
+ struct { ///<
+ UINT32 PrimaryBus:8 ; ///<
+ UINT32 SecondaryBus:8 ; ///<
+ UINT32 SubBusNumber:8 ; ///<
+ UINT32 SecondaryLatencyTimer:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x18_STRUCT;
+
+// **** DxF0x1C Register Definition ****
+// Address
+#define DxF0x1C_ADDRESS 0x1c
+
+// Type
+#define DxF0x1C_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x1C_Reserved_3_0_OFFSET 0
+#define DxF0x1C_Reserved_3_0_WIDTH 4
+#define DxF0x1C_Reserved_3_0_MASK 0xf
+#define DxF0x1C_IOBase_15_12__OFFSET 4
+#define DxF0x1C_IOBase_15_12__WIDTH 4
+#define DxF0x1C_IOBase_15_12__MASK 0xf0
+#define DxF0x1C_Reserved_11_8_OFFSET 8
+#define DxF0x1C_Reserved_11_8_WIDTH 4
+#define DxF0x1C_Reserved_11_8_MASK 0xf00
+#define DxF0x1C_IOLimit_15_12__OFFSET 12
+#define DxF0x1C_IOLimit_15_12__WIDTH 4
+#define DxF0x1C_IOLimit_15_12__MASK 0xf000
+#define DxF0x1C_Reserved_19_16_OFFSET 16
+#define DxF0x1C_Reserved_19_16_WIDTH 4
+#define DxF0x1C_Reserved_19_16_MASK 0xf0000
+#define DxF0x1C_CapList_OFFSET 20
+#define DxF0x1C_CapList_WIDTH 1
+#define DxF0x1C_CapList_MASK 0x100000
+#define DxF0x1C_PCI66En_OFFSET 21
+#define DxF0x1C_PCI66En_WIDTH 1
+#define DxF0x1C_PCI66En_MASK 0x200000
+#define DxF0x1C_UDFEn_OFFSET 22
+#define DxF0x1C_UDFEn_WIDTH 1
+#define DxF0x1C_UDFEn_MASK 0x400000
+#define DxF0x1C_FastBackCapable_OFFSET 23
+#define DxF0x1C_FastBackCapable_WIDTH 1
+#define DxF0x1C_FastBackCapable_MASK 0x800000
+#define DxF0x1C_MasterDataPerr_OFFSET 24
+#define DxF0x1C_MasterDataPerr_WIDTH 1
+#define DxF0x1C_MasterDataPerr_MASK 0x1000000
+#define DxF0x1C_DevselTiming_OFFSET 25
+#define DxF0x1C_DevselTiming_WIDTH 2
+#define DxF0x1C_DevselTiming_MASK 0x6000000
+#define DxF0x1C_SignalTargetAbort_OFFSET 27
+#define DxF0x1C_SignalTargetAbort_WIDTH 1
+#define DxF0x1C_SignalTargetAbort_MASK 0x8000000
+#define DxF0x1C_ReceivedTargetAbort_OFFSET 28
+#define DxF0x1C_ReceivedTargetAbort_WIDTH 1
+#define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000
+#define DxF0x1C_ReceivedMasterAbort_OFFSET 29
+#define DxF0x1C_ReceivedMasterAbort_WIDTH 1
+#define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000
+#define DxF0x1C_ReceivedSystemError_OFFSET 30
+#define DxF0x1C_ReceivedSystemError_WIDTH 1
+#define DxF0x1C_ReceivedSystemError_MASK 0x40000000
+#define DxF0x1C_ParityErrorDetected_OFFSET 31
+#define DxF0x1C_ParityErrorDetected_WIDTH 1
+#define DxF0x1C_ParityErrorDetected_MASK 0x80000000
+
+/// DxF0x1C
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 IOBase_15_12_:4 ; ///<
+ UINT32 Reserved_11_8:4 ; ///<
+ UINT32 IOLimit_15_12_:4 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 CapList:1 ; ///<
+ UINT32 PCI66En:1 ; ///<
+ UINT32 UDFEn:1 ; ///<
+ UINT32 FastBackCapable:1 ; ///<
+ UINT32 MasterDataPerr:1 ; ///<
+ UINT32 DevselTiming:2 ; ///<
+ UINT32 SignalTargetAbort:1 ; ///<
+ UINT32 ReceivedTargetAbort:1 ; ///<
+ UINT32 ReceivedMasterAbort:1 ; ///<
+ UINT32 ReceivedSystemError:1 ; ///<
+ UINT32 ParityErrorDetected:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x1C_STRUCT;
+
+// **** DxF0x20 Register Definition ****
+// Address
+#define DxF0x20_ADDRESS 0x20
+
+// Type
+#define DxF0x20_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x20_Reserved_3_0_OFFSET 0
+#define DxF0x20_Reserved_3_0_WIDTH 4
+#define DxF0x20_Reserved_3_0_MASK 0xf
+#define DxF0x20_MemBase_OFFSET 4
+#define DxF0x20_MemBase_WIDTH 12
+#define DxF0x20_MemBase_MASK 0xfff0
+#define DxF0x20_Reserved_19_16_OFFSET 16
+#define DxF0x20_Reserved_19_16_WIDTH 4
+#define DxF0x20_Reserved_19_16_MASK 0xf0000
+#define DxF0x20_MemLimit_OFFSET 20
+#define DxF0x20_MemLimit_WIDTH 12
+#define DxF0x20_MemLimit_MASK 0xfff00000
+
+/// DxF0x20
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 MemBase:12; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 MemLimit:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x20_STRUCT;
+
+// **** DxF0x24 Register Definition ****
+// Address
+#define DxF0x24_ADDRESS 0x24
+
+// Type
+#define DxF0x24_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x24_PrefMemBaseR_OFFSET 0
+#define DxF0x24_PrefMemBaseR_WIDTH 4
+#define DxF0x24_PrefMemBaseR_MASK 0xf
+#define DxF0x24_PrefMemBase_31_20__OFFSET 4
+#define DxF0x24_PrefMemBase_31_20__WIDTH 12
+#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0
+#define DxF0x24_PrefMemLimitR_OFFSET 16
+#define DxF0x24_PrefMemLimitR_WIDTH 4
+#define DxF0x24_PrefMemLimitR_MASK 0xf0000
+#define DxF0x24_PrefMemLimit_OFFSET 20
+#define DxF0x24_PrefMemLimit_WIDTH 12
+#define DxF0x24_PrefMemLimit_MASK 0xfff00000
+
+/// DxF0x24
+typedef union {
+ struct { ///<
+ UINT32 PrefMemBaseR:4 ; ///<
+ UINT32 PrefMemBase_31_20_:12; ///<
+ UINT32 PrefMemLimitR:4 ; ///<
+ UINT32 PrefMemLimit:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x24_STRUCT;
+
+// **** DxF0x28 Register Definition ****
+// Address
+#define DxF0x28_ADDRESS 0x28
+
+// Type
+#define DxF0x28_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x28_PrefMemBase_63_32__OFFSET 0
+#define DxF0x28_PrefMemBase_63_32__WIDTH 32
+#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff
+
+/// DxF0x28
+typedef union {
+ struct { ///<
+ UINT32 PrefMemBase_63_32_:32; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x28_STRUCT;
+
+// **** DxF0x2C Register Definition ****
+// Address
+#define DxF0x2C_ADDRESS 0x2c
+
+// Type
+#define DxF0x2C_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0
+#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32
+#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff
+
+/// DxF0x2C
+typedef union {
+ struct { ///<
+ UINT32 PrefMemLimit_63_32_:32; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x2C_STRUCT;
+
+// **** DxF0x30 Register Definition ****
+// Address
+#define DxF0x30_ADDRESS 0x30
+
+// Type
+#define DxF0x30_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x30_IOBase_31_16__OFFSET 0
+#define DxF0x30_IOBase_31_16__WIDTH 16
+#define DxF0x30_IOBase_31_16__MASK 0xffff
+#define DxF0x30_IOLimit_31_16__OFFSET 16
+#define DxF0x30_IOLimit_31_16__WIDTH 16
+#define DxF0x30_IOLimit_31_16__MASK 0xffff0000
+
+/// DxF0x30
+typedef union {
+ struct { ///<
+ UINT32 IOBase_31_16_:16; ///<
+ UINT32 IOLimit_31_16_:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x30_STRUCT;
+
+// **** DxF0x34 Register Definition ****
+// Address
+#define DxF0x34_ADDRESS 0x34
+
+// Type
+#define DxF0x34_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x34_CapPtr_OFFSET 0
+#define DxF0x34_CapPtr_WIDTH 8
+#define DxF0x34_CapPtr_MASK 0xff
+#define DxF0x34_Reserved_31_8_OFFSET 8
+#define DxF0x34_Reserved_31_8_WIDTH 24
+#define DxF0x34_Reserved_31_8_MASK 0xffffff00
+
+/// DxF0x34
+typedef union {
+ struct { ///<
+ UINT32 CapPtr:8 ; ///<
+ UINT32 Reserved_31_8:24; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x34_STRUCT;
+
+// **** DxF0x3C Register Definition ****
+// Address
+#define DxF0x3C_ADDRESS 0x3c
+
+// Type
+#define DxF0x3C_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x3C_IntLine_OFFSET 0
+#define DxF0x3C_IntLine_WIDTH 8
+#define DxF0x3C_IntLine_MASK 0xff
+#define DxF0x3C_IntPin_OFFSET 8
+#define DxF0x3C_IntPin_WIDTH 3
+#define DxF0x3C_IntPin_MASK 0x700
+#define DxF0x3C_Reserved_15_11_OFFSET 11
+#define DxF0x3C_Reserved_15_11_WIDTH 5
+#define DxF0x3C_Reserved_15_11_MASK 0xf800
+#define DxF0x3C_ParityResponseEn_OFFSET 16
+#define DxF0x3C_ParityResponseEn_WIDTH 1
+#define DxF0x3C_ParityResponseEn_MASK 0x10000
+#define DxF0x3C_SerrEn_OFFSET 17
+#define DxF0x3C_SerrEn_WIDTH 1
+#define DxF0x3C_SerrEn_MASK 0x20000
+#define DxF0x3C_IsaEn_OFFSET 18
+#define DxF0x3C_IsaEn_WIDTH 1
+#define DxF0x3C_IsaEn_MASK 0x40000
+#define DxF0x3C_VgaEn_OFFSET 19
+#define DxF0x3C_VgaEn_WIDTH 1
+#define DxF0x3C_VgaEn_MASK 0x80000
+#define DxF0x3C_Vga16En_OFFSET 20
+#define DxF0x3C_Vga16En_WIDTH 1
+#define DxF0x3C_Vga16En_MASK 0x100000
+#define DxF0x3C_MasterAbortMode_OFFSET 21
+#define DxF0x3C_MasterAbortMode_WIDTH 1
+#define DxF0x3C_MasterAbortMode_MASK 0x200000
+#define DxF0x3C_SecondaryBusReset_OFFSET 22
+#define DxF0x3C_SecondaryBusReset_WIDTH 1
+#define DxF0x3C_SecondaryBusReset_MASK 0x400000
+#define DxF0x3C_FastB2BCap_OFFSET 23
+#define DxF0x3C_FastB2BCap_WIDTH 1
+#define DxF0x3C_FastB2BCap_MASK 0x800000
+#define DxF0x3C_Reserved_31_24_OFFSET 24
+#define DxF0x3C_Reserved_31_24_WIDTH 8
+#define DxF0x3C_Reserved_31_24_MASK 0xff000000
+
+/// DxF0x3C
+typedef union {
+ struct { ///<
+ UINT32 IntLine:8 ; ///<
+ UINT32 IntPin:3 ; ///<
+ UINT32 Reserved_15_11:5 ; ///<
+ UINT32 ParityResponseEn:1 ; ///<
+ UINT32 SerrEn:1 ; ///<
+ UINT32 IsaEn:1 ; ///<
+ UINT32 VgaEn:1 ; ///<
+ UINT32 Vga16En:1 ; ///<
+ UINT32 MasterAbortMode:1 ; ///<
+ UINT32 SecondaryBusReset:1 ; ///<
+ UINT32 FastB2BCap:1 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x3C_STRUCT;
+
+// **** DxF0x50 Register Definition ****
+// Address
+#define DxF0x50_ADDRESS 0x50
+
+// Type
+#define DxF0x50_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x50_CapID_OFFSET 0
+#define DxF0x50_CapID_WIDTH 8
+#define DxF0x50_CapID_MASK 0xff
+#define DxF0x50_NextPtr_OFFSET 8
+#define DxF0x50_NextPtr_WIDTH 8
+#define DxF0x50_NextPtr_MASK 0xff00
+#define DxF0x50_Version_OFFSET 16
+#define DxF0x50_Version_WIDTH 3
+#define DxF0x50_Version_MASK 0x70000
+#define DxF0x50_PmeClock_OFFSET 19
+#define DxF0x50_PmeClock_WIDTH 1
+#define DxF0x50_PmeClock_MASK 0x80000
+#define DxF0x50_Reserved_20_20_OFFSET 20
+#define DxF0x50_Reserved_20_20_WIDTH 1
+#define DxF0x50_Reserved_20_20_MASK 0x100000
+#define DxF0x50_DevSpecificInit_OFFSET 21
+#define DxF0x50_DevSpecificInit_WIDTH 1
+#define DxF0x50_DevSpecificInit_MASK 0x200000
+#define DxF0x50_AuxCurrent_OFFSET 22
+#define DxF0x50_AuxCurrent_WIDTH 3
+#define DxF0x50_AuxCurrent_MASK 0x1c00000
+#define DxF0x50_D1Support_OFFSET 25
+#define DxF0x50_D1Support_WIDTH 1
+#define DxF0x50_D1Support_MASK 0x2000000
+#define DxF0x50_D2Support_OFFSET 26
+#define DxF0x50_D2Support_WIDTH 1
+#define DxF0x50_D2Support_MASK 0x4000000
+#define DxF0x50_PmeSupport_OFFSET 27
+#define DxF0x50_PmeSupport_WIDTH 5
+#define DxF0x50_PmeSupport_MASK 0xf8000000
+
+/// DxF0x50
+typedef union {
+ struct { ///<
+ UINT32 CapID:8 ; ///<
+ UINT32 NextPtr:8 ; ///<
+ UINT32 Version:3 ; ///<
+ UINT32 PmeClock:1 ; ///<
+ UINT32 Reserved_20_20:1 ; ///<
+ UINT32 DevSpecificInit:1 ; ///<
+ UINT32 AuxCurrent:3 ; ///<
+ UINT32 D1Support:1 ; ///<
+ UINT32 D2Support:1 ; ///<
+ UINT32 PmeSupport:5 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x50_STRUCT;
+
+// **** DxF0x54 Register Definition ****
+// Address
+#define DxF0x54_ADDRESS 0x54
+
+// Type
+#define DxF0x54_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x54_PowerState_OFFSET 0
+#define DxF0x54_PowerState_WIDTH 2
+#define DxF0x54_PowerState_MASK 0x3
+#define DxF0x54_Reserved_2_2_OFFSET 2
+#define DxF0x54_Reserved_2_2_WIDTH 1
+#define DxF0x54_Reserved_2_2_MASK 0x4
+#define DxF0x54_NoSoftReset_OFFSET 3
+#define DxF0x54_NoSoftReset_WIDTH 1
+#define DxF0x54_NoSoftReset_MASK 0x8
+#define DxF0x54_Reserved_7_4_OFFSET 4
+#define DxF0x54_Reserved_7_4_WIDTH 4
+#define DxF0x54_Reserved_7_4_MASK 0xf0
+#define DxF0x54_PmeEn_OFFSET 8
+#define DxF0x54_PmeEn_WIDTH 1
+#define DxF0x54_PmeEn_MASK 0x100
+#define DxF0x54_DataSelect_OFFSET 9
+#define DxF0x54_DataSelect_WIDTH 4
+#define DxF0x54_DataSelect_MASK 0x1e00
+#define DxF0x54_DataScale_OFFSET 13
+#define DxF0x54_DataScale_WIDTH 2
+#define DxF0x54_DataScale_MASK 0x6000
+#define DxF0x54_PmeStatus_OFFSET 15
+#define DxF0x54_PmeStatus_WIDTH 1
+#define DxF0x54_PmeStatus_MASK 0x8000
+#define DxF0x54_Reserved_21_16_OFFSET 16
+#define DxF0x54_Reserved_21_16_WIDTH 6
+#define DxF0x54_Reserved_21_16_MASK 0x3f0000
+#define DxF0x54_B2B3Support_OFFSET 22
+#define DxF0x54_B2B3Support_WIDTH 1
+#define DxF0x54_B2B3Support_MASK 0x400000
+#define DxF0x54_BusPwrEn_OFFSET 23
+#define DxF0x54_BusPwrEn_WIDTH 1
+#define DxF0x54_BusPwrEn_MASK 0x800000
+#define DxF0x54_PmeData_OFFSET 24
+#define DxF0x54_PmeData_WIDTH 8
+#define DxF0x54_PmeData_MASK 0xff000000
+
+/// DxF0x54
+typedef union {
+ struct { ///<
+ UINT32 PowerState:2 ; ///<
+ UINT32 Reserved_2_2:1 ; ///<
+ UINT32 NoSoftReset:1 ; ///<
+ UINT32 Reserved_7_4:4 ; ///<
+ UINT32 PmeEn:1 ; ///<
+ UINT32 DataSelect:4 ; ///<
+ UINT32 DataScale:2 ; ///<
+ UINT32 PmeStatus:1 ; ///<
+ UINT32 Reserved_21_16:6 ; ///<
+ UINT32 B2B3Support:1 ; ///<
+ UINT32 BusPwrEn:1 ; ///<
+ UINT32 PmeData:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x54_STRUCT;
+
+// **** DxF0x58 Register Definition ****
+// Address
+#define DxF0x58_ADDRESS 0x58
+
+// Type
+#define DxF0x58_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x58_CapID_OFFSET 0
+#define DxF0x58_CapID_WIDTH 8
+#define DxF0x58_CapID_MASK 0xff
+#define DxF0x58_NextPtr_OFFSET 8
+#define DxF0x58_NextPtr_WIDTH 8
+#define DxF0x58_NextPtr_MASK 0xff00
+#define DxF0x58_Version_OFFSET 16
+#define DxF0x58_Version_WIDTH 4
+#define DxF0x58_Version_MASK 0xf0000
+#define DxF0x58_DeviceType_OFFSET 20
+#define DxF0x58_DeviceType_WIDTH 4
+#define DxF0x58_DeviceType_MASK 0xf00000
+#define DxF0x58_SlotImplemented_OFFSET 24
+#define DxF0x58_SlotImplemented_WIDTH 1
+#define DxF0x58_SlotImplemented_MASK 0x1000000
+#define DxF0x58_IntMessageNum_OFFSET 25
+#define DxF0x58_IntMessageNum_WIDTH 5
+#define DxF0x58_IntMessageNum_MASK 0x3e000000
+#define DxF0x58_Reserved_31_30_OFFSET 30
+#define DxF0x58_Reserved_31_30_WIDTH 2
+#define DxF0x58_Reserved_31_30_MASK 0xc0000000
+
+/// DxF0x58
+typedef union {
+ struct { ///<
+ UINT32 CapID:8 ; ///<
+ UINT32 NextPtr:8 ; ///<
+ UINT32 Version:4 ; ///<
+ UINT32 DeviceType:4 ; ///<
+ UINT32 SlotImplemented:1 ; ///<
+ UINT32 IntMessageNum:5 ; ///<
+ UINT32 Reserved_31_30:2 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0x58_STRUCT;
+
+// **** DxF0x5C Register Definition ****
+// Address
+#define DxF0x5C_ADDRESS 0x5c
+
+// Type
+#define DxF0x5C_TYPE TYPE_D4F0
+// Field Data
+#define DxF0x5C_MaxPayloadSupport_OFFSET 0
+#define DxF0x5C_MaxPayloadSupport_WIDTH 3
+#define DxF0x5C_MaxPayloadSupport_MASK 0x7
+#define DxF0x5C_PhantomFunc_OFFSET 3
+#define DxF0x5C_PhantomFunc_WIDTH 2
+#define DxF0x5C_PhantomFunc_MASK 0x18
+#define DxF0x5C_ExtendedTag_OFFSET 5
+#define DxF0x5C_ExtendedTag_WIDTH 1
+#define DxF0x5C_ExtendedTag_MASK 0x20
+#define DxF0x5C_L0SAcceptableLatency_OFFSET 6
+#define DxF0x5C_L0SAcceptableLatency_WIDTH 3
+#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0
+#define DxF0x5C_L1AcceptableLatency_OFFSET 9
+#define DxF0x5C_L1AcceptableLatency_WIDTH 3
+#define DxF0x5C_L1AcceptableLatency_MASK 0xe00
+#define DxF0x5C_Reserved_14_12_OFFSET 12
+#define DxF0x5C_Reserved_14_12_WIDTH 3
+#define DxF0x5C_Reserved_14_12_MASK 0x7000
+#define DxF0x5C_RoleBasedErrReporting_OFFSET 15
+#define DxF0x5C_RoleBasedErrReporting_WIDTH 1
+#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000
+#define DxF0x5C_Reserved_17_16_OFFSET 16
+#define DxF0x5C_Reserved_17_16_WIDTH 2
+#define DxF0x5C_Reserved_17_16_MASK 0x30000
+#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18
+#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8
+#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000
+#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26
+#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2
+#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000
+#define DxF0x5C_FlrCapable_OFFSET 28
+#define DxF0x5C_FlrCapable_WIDTH 1
+#define DxF0x5C_FlrCapable_MASK 0x10000000
+#define DxF0x5C_Reserved_31_29_OFFSET 29
#define DxF0x5C_Reserved_31_29_WIDTH 3
#define DxF0x5C_Reserved_31_29_MASK 0xe0000000
UINT32 Value; ///<
} FCRxFE00_7009_STRUCT;
+// **** FCRxFE00_7079 Register Definition ****
+// Address
+#define FCRxFE00_7079_ADDRESS 0xfe007079
+
+// Type
+#define FCRxFE00_7079_TYPE TYPE_FCR
+// Field Data
+#define FCRxFE00_7079_Reserved_4_0_OFFSET 0
+#define FCRxFE00_7079_Reserved_4_0_WIDTH 5
+#define FCRxFE00_7079_Reserved_4_0_MASK 0x1f
+#define FCRxFE00_7079_CoreDis_OFFSET 5
+#define FCRxFE00_7079_CoreDis_WIDTH 2
+#define FCRxFE00_7079_CoreDis_MASK 0x60
+#define FCRxFE00_7079_Reserved_31_7_OFFSET 7
+#define FCRxFE00_7079_Reserved_31_7_WIDTH 25
+#define FCRxFE00_7079_Reserved_31_7_MASK 0xffffff80
+
+/// FCRxFE00_7079
+typedef union {
+ struct { ///<
+ UINT32 Reserved_4_0:5 ; ///<
+ UINT32 CoreDis:2 ; ///<
+ UINT32 Reserved_31_7:25; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} FCRxFE00_7079_STRUCT;
+
+
+// **** FCRxFF30_0AE6 Register Definition ****
+// Address
+#define FCRxFF30_0AE6_ADDRESS 0xff300ae6
+
+// Type
+#define FCRxFF30_0AE6_TYPE TYPE_FCR
+// Field Data
+#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0
+#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10
+#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_MASK 0x3ff
+#define FCRxFF30_0AE6_Reserved_10_10_OFFSET 10
+#define FCRxFF30_0AE6_Reserved_10_10_WIDTH 1
+#define FCRxFF30_0AE6_Reserved_10_10_MASK 0x400
+#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11
+#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1
+#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_MASK 0x800
+#define FCRxFF30_0AE6_Reserved_15_12_OFFSET 12
+#define FCRxFF30_0AE6_Reserved_15_12_WIDTH 4
+#define FCRxFF30_0AE6_Reserved_15_12_MASK 0xf000
+#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16
+#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1
+#define FCRxFF30_0AE6_StctrlStutterEn_MASK 0x10000
+#define FCRxFF30_0AE6_Reserved_23_17_OFFSET 17
+#define FCRxFF30_0AE6_Reserved_23_17_WIDTH 7
+#define FCRxFF30_0AE6_Reserved_23_17_MASK 0xfe0000
+#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24
+#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1
+#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_MASK 0x1000000
+#define FCRxFF30_0AE6_Reserved_26_25_OFFSET 25
+#define FCRxFF30_0AE6_Reserved_26_25_WIDTH 2
+#define FCRxFF30_0AE6_Reserved_26_25_MASK 0x6000000
+#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27
+#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1
+#define FCRxFF30_0AE6_CriticalRegsLock_MASK 0x8000000
+#define FCRxFF30_0AE6_Reserved_31_28_OFFSET 28
+#define FCRxFF30_0AE6_Reserved_31_28_WIDTH 4
+#define FCRxFF30_0AE6_Reserved_31_28_MASK 0xf0000000
+
+/// FCRxFF30_0AE6
+typedef union {
+ struct { ///<
+ UINT32 RengExecuteNonsecureStartPtr:10; ///<
+ UINT32 Reserved_10_10:1 ; ///<
+ UINT32 RengExecuteOnRegUpdate:1 ; ///<
+ UINT32 Reserved_15_12:4 ; ///<
+ UINT32 StctrlStutterEn:1 ; ///<
+ UINT32 Reserved_23_17:7 ; ///<
+ UINT32 StctrlIgnoreProtectionFault:1 ; ///<
+ UINT32 Reserved_26_25:2 ; ///<
+ UINT32 CriticalRegsLock:1 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} FCRxFF30_0AE6_STRUCT;
// **** D0F0x64_x00 Register Definition ****
// Address
#define D0F0x64_x1A_Reserved_31_4_WIDTH 28
#define D0F0x64_x1A_Reserved_31_4_MASK 0xfffffff0
-/// D0F0x64_x1A
+/// D0F0x64_x1A
+typedef union {
+ struct { ///<
+ UINT32 Tom2_35_32_:4 ; ///<
+ UINT32 Reserved_31_4:28; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x64_x1A_STRUCT;
+
+// **** D0F0x64_x1C Register Definition ****
+// Address
+#define D0F0x64_x1C_ADDRESS 0x1c
+
+// Type
+#define D0F0x64_x1C_TYPE TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x1C_WriteDis_OFFSET 0
+#define D0F0x64_x1C_WriteDis_WIDTH 1
+#define D0F0x64_x1C_WriteDis_MASK 0x1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1
+#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2
+#define D0F0x64_x1C_F064BarEn_OFFSET 2
+#define D0F0x64_x1C_F064BarEn_WIDTH 1
+#define D0F0x64_x1C_F064BarEn_MASK 0x4
+#define D0F0x64_x1C_MemApSize_OFFSET 3
+#define D0F0x64_x1C_MemApSize_WIDTH 3
+#define D0F0x64_x1C_MemApSize_MASK 0x38
+#define D0F0x64_x1C_RegApSize_OFFSET 6
+#define D0F0x64_x1C_RegApSize_WIDTH 1
+#define D0F0x64_x1C_RegApSize_MASK 0x40
+#define D0F0x64_x1C_Reserved_7_7_OFFSET 7
+#define D0F0x64_x1C_Reserved_7_7_WIDTH 1
+#define D0F0x64_x1C_Reserved_7_7_MASK 0x80
+#define D0F0x64_x1C_AudioEn_OFFSET 8
+#define D0F0x64_x1C_AudioEn_WIDTH 1
+#define D0F0x64_x1C_AudioEn_MASK 0x100
+#define D0F0x64_x1C_MsiDis_OFFSET 9
+#define D0F0x64_x1C_MsiDis_WIDTH 1
+#define D0F0x64_x1C_MsiDis_MASK 0x200
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1
+#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400
+#define D0F0x64_x1C_Audio64BarEn_OFFSET 11
+#define D0F0x64_x1C_Audio64BarEn_WIDTH 1
+#define D0F0x64_x1C_Audio64BarEn_MASK 0x800
+#define D0F0x64_x1C_Reserved_15_12_OFFSET 12
+#define D0F0x64_x1C_Reserved_15_12_WIDTH 4
+#define D0F0x64_x1C_Reserved_15_12_MASK 0xf000
+#define D0F0x64_x1C_IoBarDis_OFFSET 16
+#define D0F0x64_x1C_IoBarDis_WIDTH 1
+#define D0F0x64_x1C_IoBarDis_MASK 0x10000
+#define D0F0x64_x1C_F0En_OFFSET 17
+#define D0F0x64_x1C_F0En_WIDTH 1
+#define D0F0x64_x1C_F0En_MASK 0x20000
+#define D0F0x64_x1C_Reserved_22_18_OFFSET 18
+#define D0F0x64_x1C_Reserved_22_18_WIDTH 5
+#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000
+#define D0F0x64_x1C_RcieEn_OFFSET 23
+#define D0F0x64_x1C_RcieEn_WIDTH 1
+#define D0F0x64_x1C_RcieEn_MASK 0x800000
+#define D0F0x64_x1C_Reserved_31_24_OFFSET 24
+#define D0F0x64_x1C_Reserved_31_24_WIDTH 8
+#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000
+
+/// D0F0x64_x1C
typedef union {
struct { ///<
- UINT32 Tom2_35_32_:4 ; ///<
- UINT32 Reserved_31_4:28; ///<
+ UINT32 WriteDis:1 ; ///<
+ UINT32 F0NonlegacyDeviceTypeEn:1 ; ///<
+ UINT32 F064BarEn:1 ; ///<
+ UINT32 MemApSize:3 ; ///<
+ UINT32 RegApSize:1 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 AudioEn:1 ; ///<
+ UINT32 MsiDis:1 ; ///<
+ UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///<
+ UINT32 Audio64BarEn:1 ; ///<
+ UINT32 Reserved_15_12:4 ; ///<
+ UINT32 IoBarDis:1 ; ///<
+ UINT32 F0En:1 ; ///<
+ UINT32 Reserved_22_18:5 ; ///<
+ UINT32 RcieEn:1 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x64_x1A_STRUCT;
+} D0F0x64_x1C_STRUCT;
// **** D0F0x64_x1D Register Definition ****
// Address
UINT32 Value; ///<
} D0F0x64_x20_STRUCT;
+// **** D0F0x64_x22 Register Definition ****
+// Address
+#define D0F0x64_x22_ADDRESS 0x22
+
+// Type
+#define D0F0x64_x22_TYPE TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x22_Reserved_3_0_OFFSET 0
+#define D0F0x64_x22_Reserved_3_0_WIDTH 4
+#define D0F0x64_x22_Reserved_3_0_MASK 0xf
+#define D0F0x64_x22_OffHysteresis_OFFSET 4
+#define D0F0x64_x22_OffHysteresis_WIDTH 8
+#define D0F0x64_x22_OffHysteresis_MASK 0xff0
+#define D0F0x64_x22_Reserved_25_12_OFFSET 12
+#define D0F0x64_x22_Reserved_25_12_WIDTH 14
+#define D0F0x64_x22_Reserved_25_12_MASK 0x3fff000
+#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26
+#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1
+#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000
+#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27
+#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1
+#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000
+#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28
+#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1
+#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000
+#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29
+#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1
+#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000
+#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30
+#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1
+#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000
+#define D0F0x64_x22_Reserved_31_31_OFFSET 31
+#define D0F0x64_x22_Reserved_31_31_WIDTH 1
+#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000
+
+/// D0F0x64_x22
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 OffHysteresis:8 ; ///<
+ UINT32 Reserved_25_12:14; ///<
+ UINT32 SoftOverrideClk4:1 ; ///<
+ UINT32 SoftOverrideClk3:1 ; ///<
+ UINT32 SoftOverrideClk2:1 ; ///<
+ UINT32 SoftOverrideClk1:1 ; ///<
+ UINT32 SoftOverrideClk0:1 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x64_x22_STRUCT;
+
+// **** D0F0x64_x23 Register Definition ****
+// Address
+#define D0F0x64_x23_ADDRESS 0x23
+
+// Type
+#define D0F0x64_x23_TYPE TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x23_Reserved_3_0_OFFSET 0
+#define D0F0x64_x23_Reserved_3_0_WIDTH 4
+#define D0F0x64_x23_Reserved_3_0_MASK 0xf
+#define D0F0x64_x23_OffHysteresis_OFFSET 4
+#define D0F0x64_x23_OffHysteresis_WIDTH 8
+#define D0F0x64_x23_OffHysteresis_MASK 0xff0
+#define D0F0x64_x23_Reserved_25_12_OFFSET 12
+#define D0F0x64_x23_Reserved_25_12_WIDTH 14
+#define D0F0x64_x23_Reserved_25_12_MASK 0x3fff000
+#define D0F0x64_x23_SoftOverrideClk4_OFFSET 26
+#define D0F0x64_x23_SoftOverrideClk4_WIDTH 1
+#define D0F0x64_x23_SoftOverrideClk4_MASK 0x4000000
+#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27
+#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1
+#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000
+#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28
+#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1
+#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000
+#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29
+#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1
+#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000
+#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30
+#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1
+#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000
+#define D0F0x64_x23_Reserved_31_31_OFFSET 31
+#define D0F0x64_x23_Reserved_31_31_WIDTH 1
+#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000
+
+/// D0F0x64_x23
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 OffHysteresis:8 ; ///<
+ UINT32 Reserved_25_12:14; ///<
+ UINT32 SoftOverrideClk4:1 ; ///<
+ UINT32 SoftOverrideClk3:1 ; ///<
+ UINT32 SoftOverrideClk2:1 ; ///<
+ UINT32 SoftOverrideClk1:1 ; ///<
+ UINT32 SoftOverrideClk0:1 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x64_x23_STRUCT;
+
+// **** D0F0x64_x24 Register Definition ****
+// Address
+#define D0F0x64_x24_ADDRESS 0x24
+
+// Type
+#define D0F0x64_x24_TYPE TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x24_Reserved_3_0_OFFSET 0
+#define D0F0x64_x24_Reserved_3_0_WIDTH 4
+#define D0F0x64_x24_Reserved_3_0_MASK 0xf
+#define D0F0x64_x24_OffHysteresis_OFFSET 4
+#define D0F0x64_x24_OffHysteresis_WIDTH 8
+#define D0F0x64_x24_OffHysteresis_MASK 0xff0
+#define D0F0x64_x24_Reserved_28_12_OFFSET 12
+#define D0F0x64_x24_Reserved_28_12_WIDTH 17
+#define D0F0x64_x24_Reserved_28_12_MASK 0x1ffff000
+#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29
+#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1
+#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000
+#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30
+#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1
+#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000
+#define D0F0x64_x24_Reserved_31_31_OFFSET 31
+#define D0F0x64_x24_Reserved_31_31_WIDTH 1
+#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000
+
+/// D0F0x64_x24
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 OffHysteresis:8 ; ///<
+ UINT32 Reserved_28_12:17; ///<
+ UINT32 SoftOverrideClk1:1 ; ///<
+ UINT32 SoftOverrideClk0:1 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x64_x24_STRUCT;
+
+
// **** D0F0x64_x46 Register Definition ****
// Address
#define D0F0x64_x46_ADDRESS 0x46
#define D0F0x98_x2C_ADDRESS 0x2c
// Type
-#define D0F0x98_x2C_TYPE TYPE_D0F0x98
+#define D0F0x98_x2C_TYPE TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x2C_Reserved_0_0_OFFSET 0
+#define D0F0x98_x2C_Reserved_0_0_WIDTH 1
+#define D0F0x98_x2C_Reserved_0_0_MASK 0x1
+#define D0F0x98_x2C_DynWakeEn_OFFSET 1
+#define D0F0x98_x2C_DynWakeEn_WIDTH 1
+#define D0F0x98_x2C_DynWakeEn_MASK 0x2
+#define D0F0x98_x2C_Reserved_15_2_OFFSET 2
+#define D0F0x98_x2C_Reserved_15_2_WIDTH 14
+#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc
+#define D0F0x98_x2C_WakeHysteresis_OFFSET 16
+#define D0F0x98_x2C_WakeHysteresis_WIDTH 16
+#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000
+
+/// D0F0x98_x2C
+typedef union {
+ struct { ///<
+ UINT32 Reserved_0_0:1 ; ///<
+ UINT32 DynWakeEn:1 ; ///<
+ UINT32 Reserved_15_2:14; ///<
+ UINT32 WakeHysteresis:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x98_x2C_STRUCT;
+
+// **** D0F0x98_x49 Register Definition ****
+// Address
+#define D0F0x98_x49_ADDRESS 0x49
+
+// Type
+#define D0F0x98_x49_TYPE TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x49_Reserved_3_0_OFFSET 0
+#define D0F0x98_x49_Reserved_3_0_WIDTH 4
+#define D0F0x98_x49_Reserved_3_0_MASK 0xf
+#define D0F0x98_x49_OffHysteresis_OFFSET 4
+#define D0F0x98_x49_OffHysteresis_WIDTH 8
+#define D0F0x98_x49_OffHysteresis_MASK 0xff0
+#define D0F0x98_x49_Reserved_23_12_OFFSET 12
+#define D0F0x98_x49_Reserved_23_12_WIDTH 12
+#define D0F0x98_x49_Reserved_23_12_MASK 0xfff000
+#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24
+#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000
+#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25
+#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000
+#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26
+#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000
+#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27
+#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000
+#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28
+#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000
+#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29
+#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000
+#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30
+#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1
+#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000
+#define D0F0x98_x49_Reserved_31_31_OFFSET 31
+#define D0F0x98_x49_Reserved_31_31_WIDTH 1
+#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000
+
+/// D0F0x98_x49
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 OffHysteresis:8 ; ///<
+ UINT32 Reserved_23_12:12; ///<
+ UINT32 SoftOverrideClk6:1 ; ///<
+ UINT32 SoftOverrideClk5:1 ; ///<
+ UINT32 SoftOverrideClk4:1 ; ///<
+ UINT32 SoftOverrideClk3:1 ; ///<
+ UINT32 SoftOverrideClk2:1 ; ///<
+ UINT32 SoftOverrideClk1:1 ; ///<
+ UINT32 SoftOverrideClk0:1 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x98_x49_STRUCT;
+
+// **** D0F0x98_x4A Register Definition ****
+// Address
+#define D0F0x98_x4A_ADDRESS 0x4a
+
+// Type
+#define D0F0x98_x4A_TYPE TYPE_D0F0x98
+// Field Data
+#define D0F0x98_x4A_Reserved_3_0_OFFSET 0
+#define D0F0x98_x4A_Reserved_3_0_WIDTH 4
+#define D0F0x98_x4A_Reserved_3_0_MASK 0xf
+#define D0F0x98_x4A_OffHysteresis_OFFSET 4
+#define D0F0x98_x4A_OffHysteresis_WIDTH 8
+#define D0F0x98_x4A_OffHysteresis_MASK 0xff0
+#define D0F0x98_x4A_Reserved_23_12_OFFSET 12
+#define D0F0x98_x4A_Reserved_23_12_WIDTH 12
+#define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000
+#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24
+#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000
+#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25
+#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000
+#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26
+#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000
+#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27
+#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000
+#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28
+#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000
+#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29
+#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000
+#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30
+#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1
+#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000
+#define D0F0x98_x4A_Reserved_31_31_OFFSET 31
+#define D0F0x98_x4A_Reserved_31_31_WIDTH 1
+#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000
+
+/// D0F0x98_x4A
+typedef union {
+ struct { ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 OffHysteresis:8 ; ///<
+ UINT32 Reserved_23_12:12; ///<
+ UINT32 SoftOverrideClk6:1 ; ///<
+ UINT32 SoftOverrideClk5:1 ; ///<
+ UINT32 SoftOverrideClk4:1 ; ///<
+ UINT32 SoftOverrideClk3:1 ; ///<
+ UINT32 SoftOverrideClk2:1 ; ///<
+ UINT32 SoftOverrideClk1:1 ; ///<
+ UINT32 SoftOverrideClk0:1 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0x98_x4A_STRUCT;
+
+// **** D0F0x98_x4B Register Definition ****
+// Address
+#define D0F0x98_x4B_ADDRESS 0x4b
+
+// Type
+#define D0F0x98_x4B_TYPE TYPE_D0F0x98
// Field Data
-#define D0F0x98_x2C_Reserved_0_0_OFFSET 0
-#define D0F0x98_x2C_Reserved_0_0_WIDTH 1
-#define D0F0x98_x2C_Reserved_0_0_MASK 0x1
-#define D0F0x98_x2C_DynWakeEn_OFFSET 1
-#define D0F0x98_x2C_DynWakeEn_WIDTH 1
-#define D0F0x98_x2C_DynWakeEn_MASK 0x2
-#define D0F0x98_x2C_Reserved_15_2_OFFSET 2
-#define D0F0x98_x2C_Reserved_15_2_WIDTH 14
-#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc
-#define D0F0x98_x2C_WakeHysteresis_OFFSET 16
-#define D0F0x98_x2C_WakeHysteresis_WIDTH 16
-#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000
+#define D0F0x98_x4B_Reserved_3_0_OFFSET 0
+#define D0F0x98_x4B_Reserved_3_0_WIDTH 4
+#define D0F0x98_x4B_Reserved_3_0_MASK 0xf
+#define D0F0x98_x4B_OffHysteresis_OFFSET 4
+#define D0F0x98_x4B_OffHysteresis_WIDTH 8
+#define D0F0x98_x4B_OffHysteresis_MASK 0xff0
+#define D0F0x98_x4B_Reserved_29_12_OFFSET 12
+#define D0F0x98_x4B_Reserved_29_12_WIDTH 18
+#define D0F0x98_x4B_Reserved_29_12_MASK 0x3ffff000
+#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30
+#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1
+#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000
+#define D0F0x98_x4B_Reserved_31_31_OFFSET 31
+#define D0F0x98_x4B_Reserved_31_31_WIDTH 1
+#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000
-/// D0F0x98_x2C
+/// D0F0x98_x4B
typedef union {
struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 DynWakeEn:1 ; ///<
- UINT32 Reserved_15_2:14; ///<
- UINT32 WakeHysteresis:16; ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 OffHysteresis:8 ; ///<
+ UINT32 Reserved_29_12:18; ///<
+ UINT32 SoftOverrideClk:1 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x98_x2C_STRUCT;
+} D0F0x98_x4B_STRUCT;
// **** D0F0xE4_WRAP_0080 Register Definition ****
// Address
UINT32 Reserved_31_6:26; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_0803_STRUCT;
+} D0F0xE4_WRAP_0803_STRUCT;
+
+// **** D0F0xE4_WRAP_0903 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_0903_ADDRESS 0x903
+
+// Type
+#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0
+#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5
+#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1
+#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20
+#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6
+#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26
+#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0
+
+/// D0F0xE4_WRAP_0903
+typedef union {
+ struct { ///<
+ UINT32 Reserved_4_0:5 ; ///<
+ UINT32 StrapBifDeemphasisSel:1 ; ///<
+ UINT32 Reserved_31_6:26; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_WRAP_0903_STRUCT;
+
+// **** D0F0xE4_WRAP_8002 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8002_ADDRESS 0x8002
+
+// Type
+#define D0F0xE4_WRAP_8002_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8002_SubsystemVendorID_OFFSET 0
+#define D0F0xE4_WRAP_8002_SubsystemVendorID_WIDTH 16
+#define D0F0xE4_WRAP_8002_SubsystemVendorID_MASK 0xffff
+#define D0F0xE4_WRAP_8002_SubsystemID_OFFSET 16
+#define D0F0xE4_WRAP_8002_SubsystemID_WIDTH 16
+#define D0F0xE4_WRAP_8002_SubsystemID_MASK 0xffff0000
+
+/// D0F0xE4_WRAP_8002
+typedef union {
+ struct { ///<
+ UINT32 SubsystemVendorID:16; ///<
+ UINT32 SubsystemID:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_WRAP_8002_STRUCT;
+
+// **** D0F0xE4_WRAP_8011 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8011_ADDRESS 0x8011
+
+// Type
+#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6
+#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1
+#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80
+#define D0F0xE4_WRAP_8011_TxclkPermStop_OFFSET 8
+#define D0F0xE4_WRAP_8011_TxclkPermStop_WIDTH 1
+#define D0F0xE4_WRAP_8011_TxclkPermStop_MASK 0x100
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6
+#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1
+#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6
+#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000
+#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23
+#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1
+#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000
+#define D0F0xE4_WRAP_8011_Reserved_30_25_OFFSET 25
+#define D0F0xE4_WRAP_8011_Reserved_30_25_WIDTH 6
+#define D0F0xE4_WRAP_8011_Reserved_30_25_MASK 0x7e000000
+#define D0F0xE4_WRAP_8011_StrapBifValid_OFFSET 31
+#define D0F0xE4_WRAP_8011_StrapBifValid_WIDTH 1
+#define D0F0xE4_WRAP_8011_StrapBifValid_MASK 0x80000000
+
+/// D0F0xE4_WRAP_8011
+typedef union {
+ struct { ///<
+ UINT32 TxclkDynGateLatency:6 ; ///<
+ UINT32 TxclkPermGateEven:1 ; ///<
+ UINT32 TxclkDynGateEnable:1 ; ///<
+ UINT32 TxclkPermStop:1 ; ///<
+ UINT32 TxclkRegsGateEnable:1 ; ///<
+ UINT32 TxclkRegsGateLatency:6 ; ///<
+ UINT32 RcvrDetClkEnable:1 ; ///<
+ UINT32 TxclkPermGateLatency:6 ; ///<
+ UINT32 Reserved_23_23:1 ; ///<
+ UINT32 TxclkLcntGateEnable:1 ; ///<
+ UINT32 Reserved_30_25:6 ; ///<
+ UINT32 StrapBifValid:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_WRAP_8011_STRUCT;
+
+// **** D0F0xE4_WRAP_8012 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8012_ADDRESS 0x8012
+
+// Type
+#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f
+#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6
+#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1
+#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6
+#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00
+#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14
+#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2
+#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000
+#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22
+#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1
+#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6
+#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000
+#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30
+#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2
+#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000
+
+/// D0F0xE4_WRAP_8012
+typedef union {
+ struct { ///<
+ UINT32 Pif1xIdleGateLatency:6 ; ///<
+ UINT32 Reserved_6_6:1 ; ///<
+ UINT32 Pif1xIdleGateEnable:1 ; ///<
+ UINT32 Pif1xIdleResumeLatency:6 ; ///<
+ UINT32 Reserved_15_14:2 ; ///<
+ UINT32 Pif2p5xIdleGateLatency:6 ; ///<
+ UINT32 Reserved_22_22:1 ; ///<
+ UINT32 Pif2p5xIdleGateEnable:1 ; ///<
+ UINT32 Pif2p5xIdleResumeLatency:6 ; ///<
+ UINT32 Reserved_31_30:2 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_WRAP_8012_STRUCT;
+
+
+// **** D0F0xE4_WRAP_8013 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_8013_ADDRESS 0x8013
+
+// Field Data
+#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0
+#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1
+#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2
+#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2
+#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4
+#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3
+#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1
+#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10
+#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5
+#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20
+#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6
+#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40
+#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7
+#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1
+#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1
+#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200
+#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10
+#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400
+#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11
+#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800
+#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12
+#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000
+#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13
+#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3
+#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000
+#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16
+#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000
+#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17
+#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3
+#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000
+#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20
+#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1
+#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000
+#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21
+#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11
+#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000
+
+/// D0F0xE4_WRAP_8013
+typedef union {
+ struct { ///<
+ UINT32 MasterPciePllA:1 ; ///<
+ UINT32 MasterPciePllB:1 ; ///<
+ UINT32 MasterPciePllC:1 ; ///<
+ UINT32 MasterPciePllD:1 ; ///<
+ UINT32 ClkDividerResetOverrideA:1 ; ///<
+ UINT32 Reserved_5_5:1 ; ///<
+ UINT32 Reserved_6_6:1 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 TxclkSelCoreOverride:1 ; ///<
+ UINT32 TxclkSelPifAOverride:1 ; ///<
+ UINT32 Reserved_10_10:1 ; ///<
+ UINT32 Reserved_11_11:1 ; ///<
+ UINT32 Reserved_12_12:1 ; ///<
+ UINT32 Reserved_15_13:3 ; ///<
+ UINT32 Reserved_16_16:1 ; ///<
+ UINT32 Reserved_19_17:3 ; ///<
+ UINT32 Reserved_20_20:1 ; ///<
+ UINT32 Reserved_31_21:11; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_WRAP_8013_STRUCT;
-// **** D0F0xE4_WRAP_0903 Register Definition ****
+// **** D0F0xE4_WRAP_8014 Register Definition ****
// Address
-#define D0F0xE4_WRAP_0903_ADDRESS 0x903
+#define D0F0xE4_WRAP_8014_ADDRESS 0x8014
-// Type
-#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4
// Field Data
-#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0
-#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5
-#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f
-#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5
-#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1
-#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20
-#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6
-#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26
-#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2
+#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2
+#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4
+#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3
+#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8
+#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4
+#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10
+#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5
+#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20
+#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6
+#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40
+#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7
+#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80
+#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8
+#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100
+#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9
+#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200
+#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10
+#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400
+#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11
+#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1
+#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000
+#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13
+#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000
+#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14
+#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000
+#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15
+#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1
+#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000
+#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17
+#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000
+#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18
+#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000
+#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19
+#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1
+#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1
+#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000
+#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21
+#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11
+#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000
-/// D0F0xE4_WRAP_0903
+/// D0F0xE4_WRAP_8014
typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 StrapBifDeemphasisSel:1 ; ///<
- UINT32 Reserved_31_6:26; ///<
+ struct {
+ UINT32 TxclkPermGateEnable:1 ; ///<
+ UINT32 TxclkPrbsGateEnable:1 ; ///<
+ UINT32 DdiGatePifA1xEnable:1 ; ///<
+ UINT32 DdiGatePifB1xEnable:1 ; ///<
+ UINT32 DdiGatePifC1xEnable:1 ; ///<
+ UINT32 DdiGatePifD1xEnable:1 ; ///<
+ UINT32 DdiGateDigAEnable:1 ; ///<
+ UINT32 DdiGateDigBEnable:1 ; ///<
+ UINT32 DdiGatePifA2p5xEnable:1 ; ///<
+ UINT32 DdiGatePifB2p5xEnable:1 ; ///<
+ UINT32 DdiGatePifC2p5xEnable:1 ; ///<
+ UINT32 DdiGatePifD2p5xEnable:1 ; ///<
+ UINT32 PcieGatePifA1xEnable:1 ; ///<
+ UINT32 PcieGatePifB1xEnable:1 ; ///<
+ UINT32 PcieGatePifC1xEnable:1 ; ///<
+ UINT32 PcieGatePifD1xEnable:1 ; ///<
+ UINT32 PcieGatePifA2p5xEnable:1 ; ///<
+ UINT32 PcieGatePifB2p5xEnable:1 ; ///<
+ UINT32 PcieGatePifC2p5xEnable:1 ; ///<
+ UINT32 PcieGatePifD2p5xEnable:1 ; ///<
+ UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
+ UINT32 Reserved_31_21:11; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_0903_STRUCT;
+} D0F0xE4_WRAP_8014_STRUCT;
-// **** D0F0xE4_WRAP_8002 Register Definition ****
+// **** D0F0xE4_WRAP_8016 Register Definition ****
// Address
-#define D0F0xE4_WRAP_8002_ADDRESS 0x8002
+#define D0F0xE4_WRAP_8016_ADDRESS 0x8016
// Type
-#define D0F0xE4_WRAP_8002_TYPE TYPE_D0F0xE4
+#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4
// Field Data
-#define D0F0xE4_WRAP_8002_SubsystemVendorID_OFFSET 0
-#define D0F0xE4_WRAP_8002_SubsystemVendorID_WIDTH 16
-#define D0F0xE4_WRAP_8002_SubsystemVendorID_MASK 0xffff
-#define D0F0xE4_WRAP_8002_SubsystemID_OFFSET 16
-#define D0F0xE4_WRAP_8002_SubsystemID_WIDTH 16
-#define D0F0xE4_WRAP_8002_SubsystemID_MASK 0xffff0000
+#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0
+#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6
+#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f
+#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6
+#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16
+#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0
+#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22
+#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1
+#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1
+#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000
+#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24
+#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8
+#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000
-/// D0F0xE4_WRAP_8002
+/// D0F0xE4_WRAP_8016
typedef union {
struct { ///<
- UINT32 SubsystemVendorID:16; ///<
- UINT32 SubsystemID:16; ///<
+ UINT32 CalibAckLatency:6 ; ///<
+ UINT32 Reserved_21_6:16; ///<
+ UINT32 LclkGateFree:1 ; ///<
+ UINT32 LclkDynGateEnable:1 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_8002_STRUCT;
+} D0F0xE4_WRAP_8016_STRUCT;
// **** D0F0xE4_WRAP_8021 Register Definition ****
// Address
#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2
#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1
#define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4
-#define D0F0xE4_WRAP_8060_Reserved_31_3_OFFSET 3
-#define D0F0xE4_WRAP_8060_Reserved_31_3_WIDTH 29
-#define D0F0xE4_WRAP_8060_Reserved_31_3_MASK 0xfffffff8
+#define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3
+#define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13
+#define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8
+#define D0F0xE4_WRAP_8060_BifGlobalReset_OFFSET 16
+#define D0F0xE4_WRAP_8060_BifGlobalReset_WIDTH 1
+#define D0F0xE4_WRAP_8060_BifGlobalReset_MASK 0x10000
+#define D0F0xE4_WRAP_8060_BifCalibrationReset_OFFSET 17
+#define D0F0xE4_WRAP_8060_BifCalibrationReset_WIDTH 1
+#define D0F0xE4_WRAP_8060_BifCalibrationReset_MASK 0x20000
+#define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18
+#define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14
+#define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000
/// D0F0xE4_WRAP_8060
typedef union {
UINT32 Reconfigure:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 ResetComplete:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
+ UINT32 Reserved_15_3:13; ///<
+ UINT32 BifGlobalReset:1 ; ///<
+ UINT32 BifCalibrationReset:1 ; ///<
+ UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_WRAP_8060_STRUCT;
UINT32 Value; ///<
} D0F0xE4_WRAP_8062_STRUCT;
+// **** D0F0xE4_WRAP_80F0 Register Definition ****
+// Address
+#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0
+
+// Type
+#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0
+#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32
+#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff
+
+/// D0F0xE4_WRAP_80F0
+typedef union {
+ struct { ///<
+ UINT32 MicroSeconds:32; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_WRAP_80F0_STRUCT;
+
// **** D0F0xE4_x0108_8071 Register Definition ****
// Address
#define D0F0xE4_x0108_8071_ADDRESS 0x1088071
UINT32 Value; ///<
} D0F0xE4_CORE_0002_STRUCT;
+// **** D0F0xE4_CORE_0010 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0010_ADDRESS 0x10
+
+// Type
+#define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0
+#define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1
+#define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1
+#define D0F0xE4_CORE_0010_Reserved_8_1_OFFSET 1
+#define D0F0xE4_CORE_0010_Reserved_8_1_WIDTH 8
+#define D0F0xE4_CORE_0010_Reserved_8_1_MASK 0x1fe
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_OFFSET 9
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_WIDTH 1
+#define D0F0xE4_CORE_0010_UmiNpMemWrite_MASK 0x200
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_OFFSET 10
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_WIDTH 3
+#define D0F0xE4_CORE_0010_RxSbAdjPayloadSize_MASK 0x1c00
+#define D0F0xE4_CORE_0010_Reserved_31_13_OFFSET 13
+#define D0F0xE4_CORE_0010_Reserved_31_13_WIDTH 19
+#define D0F0xE4_CORE_0010_Reserved_31_13_MASK 0xffffe000
+
+/// D0F0xE4_CORE_0010
+typedef union {
+ struct { ///<
+ UINT32 HwInitWrLock:1 ; ///<
+ UINT32 Reserved_8_1:8 ; ///<
+ UINT32 UmiNpMemWrite:1 ; ///<
+ UINT32 RxSbAdjPayloadSize:3 ; ///<
+ UINT32 Reserved_31_13:19; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_CORE_0010_STRUCT;
+
// **** D0F0xE4_CORE_0011 Register Definition ****
// Address
#define D0F0xE4_CORE_0011_ADDRESS 0x11
UINT32 Value; ///<
} D0F0xE4_CORE_001C_STRUCT;
+// **** D0F0xE4_CORE_0020 Register Definition ****
+// Address
+#define D0F0xE4_CORE_0020_ADDRESS 0x20
+
+// Type
+#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0
+#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9
+#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1
+#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200
+#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10
+#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22
+#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00
+
+/// D0F0xE4_CORE_0020
+typedef union {
+ struct { ///<
+ UINT32 Reserved_8_0:9 ; ///<
+ UINT32 CiRcOrderingDis:1 ; ///<
+ UINT32 Reserved_31_10:22; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_CORE_0020_STRUCT;
+
// **** D0F0xE4_CORE_0040 Register Definition ****
// Address
#define D0F0xE4_CORE_0040_ADDRESS 0x40
/// D0F0xE4_CORE_0040
typedef union {
struct { ///<
- UINT32 Reserved_13_0:14; ///<
- UINT32 PElecIdleMode:2 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_13_0:14; ///<
+ UINT32 PElecIdleMode:2 ; ///<
+ UINT32 Reserved_31_16:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D0F0xE4_CORE_0040_STRUCT;
+
+// **** D0F0xE4_CORE_00B0 Register Definition ****
+// Address
+#define D0F0xE4_CORE_00B0_ADDRESS 0xb0
+
+// Type
+#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0
+#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2
+#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1
+#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4
+#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3
+#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29
+#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8
+
+/// D0F0xE4_CORE_00B0
+typedef union {
+ struct { ///<
+ UINT32 Reserved_1_0:2 ; ///<
+ UINT32 StrapF0MsiEn:1 ; ///<
+ UINT32 Reserved_31_3:29; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_CORE_0040_STRUCT;
+} D0F0xE4_CORE_00B0_STRUCT;
// **** D0F0xE4_CORE_00C0 Register Definition ****
// Address
UINT32 Value; ///<
} DxF0xE4_xA4_STRUCT;
+// **** DxF0xE4_xA5 Register Definition ****
+// Address
+#define DxF0xE4_xA5_ADDRESS 0xa5
+
+// Type
+#define DxF0xE4_xA5_TYPE TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xA5_LcCurrentState_OFFSET 0
+#define DxF0xE4_xA5_LcCurrentState_WIDTH 6
+#define DxF0xE4_xA5_LcCurrentState_MASK 0x3f
+#define DxF0xE4_xA5_Reserved_7_6_OFFSET 6
+#define DxF0xE4_xA5_Reserved_7_6_WIDTH 2
+#define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0
+#define DxF0xE4_xA5_LcPrevState1_OFFSET 8
+#define DxF0xE4_xA5_LcPrevState1_WIDTH 6
+#define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00
+#define DxF0xE4_xA5_Reserved_15_14_OFFSET 14
+#define DxF0xE4_xA5_Reserved_15_14_WIDTH 2
+#define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000
+#define DxF0xE4_xA5_LcPrevState2_OFFSET 16
+#define DxF0xE4_xA5_LcPrevState2_WIDTH 6
+#define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000
+#define DxF0xE4_xA5_Reserved_23_22_OFFSET 22
+#define DxF0xE4_xA5_Reserved_23_22_WIDTH 2
+#define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000
+#define DxF0xE4_xA5_LcPrevState3_OFFSET 24
+#define DxF0xE4_xA5_LcPrevState3_WIDTH 6
+#define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000
+#define DxF0xE4_xA5_Reserved_31_30_OFFSET 30
+#define DxF0xE4_xA5_Reserved_31_30_WIDTH 2
+#define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000
+
+/// DxF0xE4_xA5
+typedef union {
+ struct { ///<
+ UINT32 LcCurrentState:6 ; ///<
+ UINT32 Reserved_7_6:2 ; ///<
+ UINT32 LcPrevState1:6 ; ///<
+ UINT32 Reserved_15_14:2 ; ///<
+ UINT32 LcPrevState2:6 ; ///<
+ UINT32 Reserved_23_22:2 ; ///<
+ UINT32 LcPrevState3:6 ; ///<
+ UINT32 Reserved_31_30:2 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0xE4_xA5_STRUCT;
+
// **** DxF0xE4_xB1 Register Definition ****
// Address
#define DxF0xE4_xB1_ADDRESS 0xb1
UINT32 Value; ///<
} DxF0xE4_xB1_STRUCT;
+// **** DxF0xE4_xB5 Register Definition ****
+// Address
+#define DxF0xE4_xB5_ADDRESS 0xb5
+
+// Type
+#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4
+// Field Data
+#define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0
+#define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1
+#define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2
+#define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6
+#define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3
+#define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1
+#define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8
+#define DxF0xE4_xB5_Reserved_9_4_OFFSET 4
+#define DxF0xE4_xB5_Reserved_9_4_WIDTH 6
+#define DxF0xE4_xB5_Reserved_9_4_MASK 0x3f0
+#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10
+#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1
+#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400
+#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11
+#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1
+#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800
+#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12
+#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2
+#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000
+#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14
+#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2
+#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000
+#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16
+#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16
+#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000
+
+/// DxF0xE4_xB5
+typedef union {
+ struct { ///<
+ UINT32 LcSelectDeemphasis:1 ; ///<
+ UINT32 LcSelectDeemphasisCntl:2 ; ///<
+ UINT32 LcRcvdDeemphasis:1 ; ///<
+ UINT32 Reserved_9_4:6 ; ///<
+ UINT32 LcEnhancedHotPlugEn:1 ; ///<
+ UINT32 Reserved_11_11:1 ; ///<
+ UINT32 LcEhpRxPhyCmd:2 ; ///<
+ UINT32 LcEhpTxPhyCmd:2 ; ///<
+ UINT32 Reserved_31_16:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} DxF0xE4_xB5_STRUCT;
+
// **** DxF0xE4_xC0 Register Definition ****
// Address
#define DxF0xE4_xC0_ADDRESS 0xc0
UINT32 Value; ///<
} DxF0xE4_xC1_STRUCT;
+// **** SMUx01 Register Definition ****
+// Address
+#define SMUx01_ADDRESS 0x1
+
+// Type
+#define SMUx01_TYPE TYPE_SMU
+// Field Data
+#define SMUx01_RamSwitch_OFFSET 0
+#define SMUx01_RamSwitch_WIDTH 1
+#define SMUx01_RamSwitch_MASK 0x1
+#define SMUx01_Reset_OFFSET 1
+#define SMUx01_Reset_WIDTH 1
+#define SMUx01_Reset_MASK 0x2
+#define SMUx01_Reserved_17_2_OFFSET 2
+#define SMUx01_Reserved_17_2_WIDTH 16
+#define SMUx01_Reserved_17_2_MASK 0x3fffc
+#define SMUx01_VectorOverride_OFFSET 18
+#define SMUx01_VectorOverride_WIDTH 1
+#define SMUx01_VectorOverride_MASK 0x40000
+#define SMUx01_Reserved_31_19_OFFSET 19
+#define SMUx01_Reserved_31_19_WIDTH 13
+#define SMUx01_Reserved_31_19_MASK 0xfff80000
+
+/// SMUx01
+typedef union {
+ struct { ///<
+ UINT32 RamSwitch:1 ; ///<
+ UINT32 Reset:1 ; ///<
+ UINT32 Reserved_17_2:16; ///<
+ UINT32 VectorOverride:1 ; ///<
+ UINT32 Reserved_31_19:13; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx01_STRUCT;
+
+// **** SMUx03 Register Definition ****
+// Address
+#define SMUx03_ADDRESS 0x3
+
+// Type
+#define SMUx03_TYPE TYPE_SMU
+// Field Data
+#define SMUx03_IntReq_OFFSET 0
+#define SMUx03_IntReq_WIDTH 1
+#define SMUx03_IntReq_MASK 0x1
+#define SMUx03_IntAck_OFFSET 1
+#define SMUx03_IntAck_WIDTH 1
+#define SMUx03_IntAck_MASK 0x2
+#define SMUx03_IntDone_OFFSET 2
+#define SMUx03_IntDone_WIDTH 1
+#define SMUx03_IntDone_MASK 0x4
+#define SMUx03_ServiceIndex_OFFSET 3
+#define SMUx03_ServiceIndex_WIDTH 8
+#define SMUx03_ServiceIndex_MASK 0x7f8
+#define SMUx03_Reserved_31_11_OFFSET 11
+#define SMUx03_Reserved_31_11_WIDTH 21
+#define SMUx03_Reserved_31_11_MASK 0xfffff800
+
+/// SMUx03
+typedef union {
+ struct { ///<
+ UINT32 IntReq:1 ; ///<
+ UINT32 IntAck:1 ; ///<
+ UINT32 IntDone:1 ; ///<
+ UINT32 ServiceIndex:8 ; ///<
+ UINT32 Reserved_31_11:21; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx03_STRUCT;
+
+// **** SMUx05 Register Definition ****
+// Address
+#define SMUx05_ADDRESS 0x5
+
+// Type
+#define SMUx05_TYPE TYPE_SMU
+// Field Data
+#define SMUx05_McuRam_OFFSET 0
+#define SMUx05_McuRam_WIDTH 32
+#define SMUx05_McuRam_MASK 0xffffffff
+
+/// SMUx05
+typedef union {
+ struct { ///<
+ UINT32 McuRam:32; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx05_STRUCT;
+
+// **** SMUx0B_x8580 Register Definition ****
+// Address
+#define SMUx0B_x8580_ADDRESS 0x8580
+
+// Type
+#define SMUx0B_x8580_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x8580_Reserved_0_0_OFFSET 0
+#define SMUx0B_x8580_Reserved_0_0_WIDTH 1
+#define SMUx0B_x8580_Reserved_0_0_MASK 0x1
+#define SMUx0B_x8580_Reserved_9_1_OFFSET 1
+#define SMUx0B_x8580_Reserved_9_1_WIDTH 9
+#define SMUx0B_x8580_Reserved_9_1_MASK 0x3fe
+#define SMUx0B_x8580_Reserved_10_10_OFFSET 10
+#define SMUx0B_x8580_Reserved_10_10_WIDTH 1
+#define SMUx0B_x8580_Reserved_10_10_MASK 0x400
+#define SMUx0B_x8580_Reserved_11_11_OFFSET 11
+#define SMUx0B_x8580_Reserved_11_11_WIDTH 1
+#define SMUx0B_x8580_Reserved_11_11_MASK 0x800
+#define SMUx0B_x8580_Reserved_15_12_OFFSET 12
+#define SMUx0B_x8580_Reserved_15_12_WIDTH 4
+#define SMUx0B_x8580_Reserved_15_12_MASK 0xf000
+#define SMUx0B_x8580_Reserved_31_16_OFFSET 16
+#define SMUx0B_x8580_Reserved_31_16_WIDTH 16
+#define SMUx0B_x8580_Reserved_31_16_MASK 0xffff0000
+
+/// SMUx0B_x8580
+typedef union {
+ struct { ///<
+ UINT32 PdmEn:1 ; ///<
+ UINT32 Reserved_9_1:9 ; ///<
+ UINT32 PdmCacEn:1 ; ///<
+ UINT32 PdmParamLoc:1 ; ///<
+ UINT32 PdmUnit:4 ; ///<
+ UINT32 PdmPeriod:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x8580_STRUCT;
+
// **** SMUx0B_x8600 Register Definition ****
// Address
#define SMUx0B_x8600_ADDRESS 0x8600
#define SMUx0B_x86A0_Data_WIDTH 32
#define SMUx0B_x86A0_Data_MASK 0xffffffff
-/// SMUx0B_x86A0
+/// SMUx0B_x86A0
+typedef union {
+ struct { ///<
+ UINT32 Data:32; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x86A0_STRUCT;
+
+// **** SMUx1B Register Definition ****
+// Address
+#define SMUx1B_ADDRESS 0x1b
+
+// Type
+#define SMUx1B_TYPE TYPE_SMU
+// Field Data
+#define SMUx1B_LclkDpSlpDiv_OFFSET 0
+#define SMUx1B_LclkDpSlpDiv_WIDTH 3
+#define SMUx1B_LclkDpSlpDiv_MASK 0x7
+#define SMUx1B_RampDis_OFFSET 3
+#define SMUx1B_RampDis_WIDTH 1
+#define SMUx1B_RampDis_MASK 0x8
+#define SMUx1B_Reserved_7_4_OFFSET 4
+#define SMUx1B_Reserved_7_4_WIDTH 4
+#define SMUx1B_Reserved_7_4_MASK 0xf0
+#define SMUx1B_LclkDpSlpMask_OFFSET 8
+#define SMUx1B_LclkDpSlpMask_WIDTH 8
+#define SMUx1B_LclkDpSlpMask_MASK 0xff00
+
+/// SMUx1B
+typedef union {
+ struct { ///<
+ UINT32 LclkDpSlpDiv:3 ; ///<
+ UINT32 RampDis:1 ; ///<
+ UINT32 Reserved_7_4:4 ; ///<
+ UINT32 LclkDpSlpMask:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx1B_STRUCT;
+
+// **** SMUx1D Register Definition ****
+// Address
+#define SMUx1D_ADDRESS 0x1d
+
+// Type
+#define SMUx1D_TYPE TYPE_SMU
+// Field Data
+#define SMUx1D_LclkDpSlpHyst_OFFSET 0
+#define SMUx1D_LclkDpSlpHyst_WIDTH 12
+#define SMUx1D_LclkDpSlpHyst_MASK 0xfff
+#define SMUx1D_LclkDpSlpEn_OFFSET 12
+#define SMUx1D_LclkDpSlpEn_WIDTH 1
+#define SMUx1D_LclkDpSlpEn_MASK 0x1000
+#define SMUx1D_Reserved_15_13_OFFSET 13
+#define SMUx1D_Reserved_15_13_WIDTH 3
+#define SMUx1D_Reserved_15_13_MASK 0xe000
+
+/// SMUx1D
+typedef union {
+ struct { ///<
+ UINT32 LclkDpSlpHyst:12; ///<
+ UINT32 LclkDpSlpEn:1 ; ///<
+ UINT32 Reserved_15_13:3 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx1D_STRUCT;
+
+// **** SMUx6F Register Definition ****
+// Address
+#define SMUx6F_ADDRESS 0x6f
+
+// Type
+#define SMUx6F_TYPE TYPE_SMU
+// Field Data
+#define SMUx6F_OnDelay_OFFSET 0
+#define SMUx6F_OnDelay_WIDTH 4
+#define SMUx6F_OnDelay_MASK 0xf
+#define SMUx6F_OffDelay_OFFSET 4
+#define SMUx6F_OffDelay_WIDTH 8
+#define SMUx6F_OffDelay_MASK 0xff0
+#define SMUx6F_Reserved_20_12_OFFSET 12
+#define SMUx6F_Reserved_20_12_WIDTH 9
+#define SMUx6F_Reserved_20_12_MASK 0x1ff000
+#define SMUx6F_RampDis0_OFFSET 21
+#define SMUx6F_RampDis0_WIDTH 1
+#define SMUx6F_RampDis0_MASK 0x200000
+#define SMUx6F_RampDisReg_OFFSET 22
+#define SMUx6F_RampDisReg_WIDTH 1
+#define SMUx6F_RampDisReg_MASK 0x400000
+#define SMUx6F_Reserved_31_23_OFFSET 23
+#define SMUx6F_Reserved_31_23_WIDTH 9
+#define SMUx6F_Reserved_31_23_MASK 0xff800000
+
+/// SMUx6F
+typedef union {
+ struct { ///<
+ UINT32 OnDelay:4 ; ///<
+ UINT32 OffDelay:8 ; ///<
+ UINT32 Reserved_20_12:9 ; ///<
+ UINT32 RampDis0:1 ; ///<
+ UINT32 RampDisReg:1 ; ///<
+ UINT32 Reserved_31_23:9 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx6F_STRUCT;
+
+// **** SMUx71 Register Definition ****
+// Address
+#define SMUx71_ADDRESS 0x71
+
+// Type
+#define SMUx71_TYPE TYPE_SMU
+// Field Data
+#define SMUx71_OnDelay_OFFSET 0
+#define SMUx71_OnDelay_WIDTH 4
+#define SMUx71_OnDelay_MASK 0xf
+#define SMUx71_OffDelay_OFFSET 4
+#define SMUx71_OffDelay_WIDTH 8
+#define SMUx71_OffDelay_MASK 0xff0
+#define SMUx71_Reserved_19_12_OFFSET 12
+#define SMUx71_Reserved_19_12_WIDTH 8
+#define SMUx71_Reserved_19_12_MASK 0xff000
+#define SMUx71_RampDis1_OFFSET 20
+#define SMUx71_RampDis1_WIDTH 1
+#define SMUx71_RampDis1_MASK 0x100000
+#define SMUx71_RampDis0_OFFSET 21
+#define SMUx71_RampDis0_WIDTH 1
+#define SMUx71_RampDis0_MASK 0x200000
+#define SMUx71_RampDisReg_OFFSET 22
+#define SMUx71_RampDisReg_WIDTH 1
+#define SMUx71_RampDisReg_MASK 0x400000
+#define SMUx71_Reserved_31_23_OFFSET 23
+#define SMUx71_Reserved_31_23_WIDTH 9
+#define SMUx71_Reserved_31_23_MASK 0xff800000
+
+/// SMUx71
+typedef union {
+ struct { ///<
+ UINT32 OnDelay:4 ; ///<
+ UINT32 OffDelay:8 ; ///<
+ UINT32 Reserved_19_12:8 ; ///<
+ UINT32 RampDis1:1 ; ///<
+ UINT32 RampDis0:1 ; ///<
+ UINT32 RampDisReg:1 ; ///<
+ UINT32 Reserved_31_23:9 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx71_STRUCT;
+
+// **** SMUx73 Register Definition ****
+// Address
+#define SMUx73_ADDRESS 0x73
+
+// Type
+#define SMUx73_TYPE TYPE_SMU
+// Field Data
+#define SMUx73_DisLclkGating_OFFSET 0
+#define SMUx73_DisLclkGating_WIDTH 1
+#define SMUx73_DisLclkGating_MASK 0x1
+#define SMUx73_DisSclkGating_OFFSET 1
+#define SMUx73_DisSclkGating_WIDTH 1
+#define SMUx73_DisSclkGating_MASK 0x2
+#define SMUx73_Reserved_15_2_OFFSET 2
+#define SMUx73_Reserved_15_2_WIDTH 14
+#define SMUx73_Reserved_15_2_MASK 0xfffc
+
+/// SMUx73
typedef union {
struct { ///<
- UINT32 Data:32; ///<
+ UINT32 DisLclkGating:1 ; ///<
+ UINT32 DisSclkGating:1 ; ///<
+ UINT32 Reserved_15_2:14; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx0B_x86A0_STRUCT;
+} SMUx73_STRUCT;
// **** GMMx00 Register Definition ****
// Address
UINT32 Mcif:4 ; ///<
UINT32 Rlc:4 ; ///<
UINT32 Vip:4 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2018_STRUCT;
-
-// **** GMMx2020 Register Definition ****
-// Address
-#define GMMx2020_ADDRESS 0x2020
-
-// Type
-#define GMMx2020_TYPE TYPE_GMM
-// Field Data
-#define GMMx2020_UvdExt0_OFFSET 0
-#define GMMx2020_UvdExt0_WIDTH 4
-#define GMMx2020_UvdExt0_MASK 0xf
-#define GMMx2020_DrmDma_OFFSET 4
-#define GMMx2020_DrmDma_WIDTH 4
-#define GMMx2020_DrmDma_MASK 0xf0
-#define GMMx2020_Hdp_OFFSET 8
-#define GMMx2020_Hdp_WIDTH 4
-#define GMMx2020_Hdp_MASK 0xf00
-#define GMMx2020_Sem_OFFSET 12
-#define GMMx2020_Sem_WIDTH 4
-#define GMMx2020_Sem_MASK 0xf000
-#define GMMx2020_Umc_OFFSET 16
-#define GMMx2020_Umc_WIDTH 4
-#define GMMx2020_Umc_MASK 0xf0000
-#define GMMx2020_Uvd_OFFSET 20
-#define GMMx2020_Uvd_WIDTH 4
-#define GMMx2020_Uvd_MASK 0xf00000
-#define GMMx2020_Xdp_OFFSET 24
-#define GMMx2020_Xdp_WIDTH 4
-#define GMMx2020_Xdp_MASK 0xf000000
-#define GMMx2020_UvdExt1_OFFSET 28
-#define GMMx2020_UvdExt1_WIDTH 4
-#define GMMx2020_UvdExt1_MASK 0xf0000000
-
-/// GMMx2020
-typedef union {
- struct { ///<
- UINT32 UvdExt0:4 ; ///<
- UINT32 DrmDma:4 ; ///<
- UINT32 Hdp:4 ; ///<
- UINT32 Sem:4 ; ///<
- UINT32 Umc:4 ; ///<
- UINT32 Uvd:4 ; ///<
- UINT32 Xdp:4 ; ///<
- UINT32 UvdExt1:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2020_STRUCT;
-
-// **** GMMx2024 Register Definition ****
-// Address
-#define GMMx2024_ADDRESS 0x2024
-
-// Type
-#define GMMx2024_TYPE TYPE_GMM
-// Field Data
-#define GMMx2024_Base_OFFSET 0
-#define GMMx2024_Base_WIDTH 16
-#define GMMx2024_Base_MASK 0xffff
-#define GMMx2024_Top_OFFSET 16
-#define GMMx2024_Top_WIDTH 16
-#define GMMx2024_Top_MASK 0xffff0000
-
-/// GMMx2024
-typedef union {
- struct { ///<
- UINT32 Base:16; ///<
- UINT32 Top:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2024_STRUCT;
-
-// **** GMMx2028 Register Definition ****
-// Address
-#define GMMx2028_ADDRESS 0x2028
-
-// Type
-#define GMMx2028_TYPE TYPE_GMM
-// Field Data
-#define GMMx2028_SysTop_39_22__OFFSET 0
-#define GMMx2028_SysTop_39_22__WIDTH 18
-#define GMMx2028_SysTop_39_22__MASK 0x3ffff
-#define GMMx2028_Reserved_31_18_OFFSET 18
-#define GMMx2028_Reserved_31_18_WIDTH 14
-#define GMMx2028_Reserved_31_18_MASK 0xfffc0000
-
-/// GMMx2028
-typedef union {
- struct { ///<
- UINT32 SysTop_39_22_:18; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2028_STRUCT;
-
-// **** GMMx202C Register Definition ****
-// Address
-#define GMMx202C_ADDRESS 0x202c
-
-// Type
-#define GMMx202C_TYPE TYPE_GMM
-// Field Data
-#define GMMx202C_SysBot_39_22__OFFSET 0
-#define GMMx202C_SysBot_39_22__WIDTH 18
-#define GMMx202C_SysBot_39_22__MASK 0x3ffff
-#define GMMx202C_Reserved_31_18_OFFSET 18
-#define GMMx202C_Reserved_31_18_WIDTH 14
-#define GMMx202C_Reserved_31_18_MASK 0xfffc0000
-
-/// GMMx202C
-typedef union {
- struct { ///<
- UINT32 SysBot_39_22_:18; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx202C_STRUCT;
-
-// **** GMMx20B4 Register Definition ****
-// Address
-#define GMMx20B4_ADDRESS 0x20b4
-
-// Type
-#define GMMx20B4_TYPE TYPE_GMM
-// Field Data
-#define GMMx20B4_StutterMode_OFFSET 0
-#define GMMx20B4_StutterMode_WIDTH 2
-#define GMMx20B4_StutterMode_MASK 0x3
-#define GMMx20B4_GateOverride_OFFSET 2
-#define GMMx20B4_GateOverride_WIDTH 1
-#define GMMx20B4_GateOverride_MASK 0x4
-#define GMMx20B4_Reserved_31_3_OFFSET 3
-#define GMMx20B4_Reserved_31_3_WIDTH 29
-#define GMMx20B4_Reserved_31_3_MASK 0xfffffff8
-
-/// GMMx20B4
-typedef union {
- struct { ///<
- UINT32 StutterMode:2 ; ///<
- UINT32 GateOverride:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20B4_STRUCT;
-
-// **** GMMx20B8 Register Definition ****
-// Address
-#define GMMx20B8_ADDRESS 0x20b8
-
-// Type
-#define GMMx20B8_TYPE TYPE_GMM
-// Field Data
-#define GMMx20B8_Reserved_17_0_OFFSET 0
-#define GMMx20B8_Reserved_17_0_WIDTH 18
-#define GMMx20B8_Reserved_17_0_MASK 0x3ffff
-#define GMMx20B8_Enable_OFFSET 18
-#define GMMx20B8_Enable_WIDTH 1
-#define GMMx20B8_Enable_MASK 0x40000
-#define GMMx20B8_Reserved_31_19_OFFSET 19
-#define GMMx20B8_Reserved_31_19_WIDTH 13
-#define GMMx20B8_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx20B8
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20B8_STRUCT;
-
-// **** GMMx20BC Register Definition ****
-// Address
-#define GMMx20BC_ADDRESS 0x20bc
-
-// Type
-#define GMMx20BC_TYPE TYPE_GMM
-// Field Data
-#define GMMx20BC_Reserved_17_0_OFFSET 0
-#define GMMx20BC_Reserved_17_0_WIDTH 18
-#define GMMx20BC_Reserved_17_0_MASK 0x3ffff
-#define GMMx20BC_Enable_OFFSET 18
-#define GMMx20BC_Enable_WIDTH 1
-#define GMMx20BC_Enable_MASK 0x40000
-#define GMMx20BC_Reserved_31_19_OFFSET 19
-#define GMMx20BC_Reserved_31_19_WIDTH 13
-#define GMMx20BC_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx20BC
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20BC_STRUCT;
-
-// **** GMMx20C0 Register Definition ****
-// Address
-#define GMMx20C0_ADDRESS 0x20c0
-
-// Type
-#define GMMx20C0_TYPE TYPE_GMM
-// Field Data
-#define GMMx20C0_Reserved_17_0_OFFSET 0
-#define GMMx20C0_Reserved_17_0_WIDTH 18
-#define GMMx20C0_Reserved_17_0_MASK 0x3ffff
-#define GMMx20C0_Enable_OFFSET 18
-#define GMMx20C0_Enable_WIDTH 1
-#define GMMx20C0_Enable_MASK 0x40000
-#define GMMx20C0_Reserved_31_19_OFFSET 19
-#define GMMx20C0_Reserved_31_19_WIDTH 13
-#define GMMx20C0_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx20C0
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20C0_STRUCT;
-
-// **** GMMx20D4 Register Definition ****
-// Address
-#define GMMx20D4_ADDRESS 0x20d4
-
-// Type
-#define GMMx20D4_TYPE TYPE_GMM
-// Field Data
-#define GMMx20D4_LocalBlackout_OFFSET 0
-#define GMMx20D4_LocalBlackout_WIDTH 1
-#define GMMx20D4_LocalBlackout_MASK 0x1
-#define GMMx20D4_Reserved_31_1_OFFSET 1
-#define GMMx20D4_Reserved_31_1_WIDTH 31
-#define GMMx20D4_Reserved_31_1_MASK 0xfffffffe
-
-/// GMMx20D4
-typedef union {
- struct { ///<
- UINT32 LocalBlackout:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx20D4_STRUCT;
+} GMMx2018_STRUCT;
-// **** GMMx20EC Register Definition ****
+// **** GMMx201C Register Definition ****
// Address
-#define GMMx20EC_ADDRESS 0x20ec
+#define GMMx201C_ADDRESS 0x201c
// Type
-#define GMMx20EC_TYPE TYPE_GMM
-// Field Data
-#define GMMx20EC_RemoteBlackout_OFFSET 0
-#define GMMx20EC_RemoteBlackout_WIDTH 1
-#define GMMx20EC_RemoteBlackout_MASK 0x1
-#define GMMx20EC_LocalBlackout_OFFSET 1
-#define GMMx20EC_LocalBlackout_WIDTH 1
-#define GMMx20EC_LocalBlackout_MASK 0x2
-#define GMMx20EC_Reserved_31_2_OFFSET 2
-#define GMMx20EC_Reserved_31_2_WIDTH 30
-#define GMMx20EC_Reserved_31_2_MASK 0xfffffffc
-
-/// GMMx20EC
+#define GMMx201C_TYPE TYPE_GMM
+// Field Data
+#define GMMx201C_UvdExt0_OFFSET 0
+#define GMMx201C_UvdExt0_WIDTH 4
+#define GMMx201C_UvdExt0_MASK 0xf
+#define GMMx201C_DrmDma_OFFSET 4
+#define GMMx201C_DrmDma_WIDTH 4
+#define GMMx201C_DrmDma_MASK 0xf0
+#define GMMx201C_Hdp_OFFSET 8
+#define GMMx201C_Hdp_WIDTH 4
+#define GMMx201C_Hdp_MASK 0xf00
+#define GMMx201C_Sem_OFFSET 12
+#define GMMx201C_Sem_WIDTH 4
+#define GMMx201C_Sem_MASK 0xf000
+#define GMMx201C_Umc_OFFSET 16
+#define GMMx201C_Umc_WIDTH 4
+#define GMMx201C_Umc_MASK 0xf0000
+#define GMMx201C_Uvd_OFFSET 20
+#define GMMx201C_Uvd_WIDTH 4
+#define GMMx201C_Uvd_MASK 0xf00000
+#define GMMx201C_UvdExt1_OFFSET 24
+#define GMMx201C_UvdExt1_WIDTH 4
+#define GMMx201C_UvdExt1_MASK 0xf000000
+#define GMMx201C_Reserved_31_28_OFFSET 28
+#define GMMx201C_Reserved_31_28_WIDTH 4
+#define GMMx201C_Reserved_31_28_MASK 0xf0000000
+
+/// GMMx201C
typedef union {
struct { ///<
- UINT32 RemoteBlackout:1 ; ///<
- UINT32 LocalBlackout:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
+ UINT32 UvdExt0:4 ; ///<
+ UINT32 DrmDma:4 ; ///<
+ UINT32 Hdp:4 ; ///<
+ UINT32 Sem:4 ; ///<
+ UINT32 Umc:4 ; ///<
+ UINT32 Uvd:4 ; ///<
+ UINT32 UvdExt1:4 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx20EC_STRUCT;
+} GMMx201C_STRUCT;
-// **** GMMx21A4 Register Definition ****
+// **** GMMx2020 Register Definition ****
// Address
-#define GMMx21A4_ADDRESS 0x21a4
+#define GMMx2020_ADDRESS 0x2020
// Type
-#define GMMx21A4_TYPE TYPE_GMM
+#define GMMx2020_TYPE TYPE_GMM
// Field Data
-#define GMMx21A4_Enable_OFFSET 0
-#define GMMx21A4_Enable_WIDTH 1
-#define GMMx21A4_Enable_MASK 0x1
-#define GMMx21A4_Prescale_OFFSET 1
-#define GMMx21A4_Prescale_WIDTH 2
-#define GMMx21A4_Prescale_MASK 0x6
-#define GMMx21A4_BlackoutExempt_OFFSET 3
-#define GMMx21A4_BlackoutExempt_WIDTH 1
-#define GMMx21A4_BlackoutExempt_MASK 0x8
-#define GMMx21A4_StallMode_OFFSET 4
-#define GMMx21A4_StallMode_WIDTH 2
-#define GMMx21A4_StallMode_MASK 0x30
-#define GMMx21A4_StallOverride_OFFSET 6
-#define GMMx21A4_StallOverride_WIDTH 1
-#define GMMx21A4_StallOverride_MASK 0x40
-#define GMMx21A4_MaxBurst_OFFSET 7
-#define GMMx21A4_MaxBurst_WIDTH 4
-#define GMMx21A4_MaxBurst_MASK 0x780
-#define GMMx21A4_LazyTimer_OFFSET 11
-#define GMMx21A4_LazyTimer_WIDTH 4
-#define GMMx21A4_LazyTimer_MASK 0x7800
-#define GMMx21A4_StallOverrideWtm_OFFSET 15
-#define GMMx21A4_StallOverrideWtm_WIDTH 1
-#define GMMx21A4_StallOverrideWtm_MASK 0x8000
-#define GMMx21A4_Reserved_31_16_OFFSET 16
-#define GMMx21A4_Reserved_31_16_WIDTH 16
-#define GMMx21A4_Reserved_31_16_MASK 0xffff0000
+#define GMMx2020_UvdExt0_OFFSET 0
+#define GMMx2020_UvdExt0_WIDTH 4
+#define GMMx2020_UvdExt0_MASK 0xf
+#define GMMx2020_DrmDma_OFFSET 4
+#define GMMx2020_DrmDma_WIDTH 4
+#define GMMx2020_DrmDma_MASK 0xf0
+#define GMMx2020_Hdp_OFFSET 8
+#define GMMx2020_Hdp_WIDTH 4
+#define GMMx2020_Hdp_MASK 0xf00
+#define GMMx2020_Sem_OFFSET 12
+#define GMMx2020_Sem_WIDTH 4
+#define GMMx2020_Sem_MASK 0xf000
+#define GMMx2020_Umc_OFFSET 16
+#define GMMx2020_Umc_WIDTH 4
+#define GMMx2020_Umc_MASK 0xf0000
+#define GMMx2020_Uvd_OFFSET 20
+#define GMMx2020_Uvd_WIDTH 4
+#define GMMx2020_Uvd_MASK 0xf00000
+#define GMMx2020_Xdp_OFFSET 24
+#define GMMx2020_Xdp_WIDTH 4
+#define GMMx2020_Xdp_MASK 0xf000000
+#define GMMx2020_UvdExt1_OFFSET 28
+#define GMMx2020_UvdExt1_WIDTH 4
+#define GMMx2020_UvdExt1_MASK 0xf0000000
-/// GMMx21A4
+/// GMMx2020
typedef union {
struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 UvdExt0:4 ; ///<
+ UINT32 DrmDma:4 ; ///<
+ UINT32 Hdp:4 ; ///<
+ UINT32 Sem:4 ; ///<
+ UINT32 Umc:4 ; ///<
+ UINT32 Uvd:4 ; ///<
+ UINT32 Xdp:4 ; ///<
+ UINT32 UvdExt1:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21A4_STRUCT;
+} GMMx2020_STRUCT;
-// **** GMMx21A8 Register Definition ****
+// **** GMMx2024 Register Definition ****
// Address
-#define GMMx21A8_ADDRESS 0x21a8
+#define GMMx2024_ADDRESS 0x2024
// Type
-#define GMMx21A8_TYPE TYPE_GMM
+#define GMMx2024_TYPE TYPE_GMM
// Field Data
-#define GMMx21A8_Enable_OFFSET 0
-#define GMMx21A8_Enable_WIDTH 1
-#define GMMx21A8_Enable_MASK 0x1
-#define GMMx21A8_Prescale_OFFSET 1
-#define GMMx21A8_Prescale_WIDTH 2
-#define GMMx21A8_Prescale_MASK 0x6
-#define GMMx21A8_BlackoutExempt_OFFSET 3
-#define GMMx21A8_BlackoutExempt_WIDTH 1
-#define GMMx21A8_BlackoutExempt_MASK 0x8
-#define GMMx21A8_StallMode_OFFSET 4
-#define GMMx21A8_StallMode_WIDTH 2
-#define GMMx21A8_StallMode_MASK 0x30
-#define GMMx21A8_StallOverride_OFFSET 6
-#define GMMx21A8_StallOverride_WIDTH 1
-#define GMMx21A8_StallOverride_MASK 0x40
-#define GMMx21A8_MaxBurst_OFFSET 7
-#define GMMx21A8_MaxBurst_WIDTH 4
-#define GMMx21A8_MaxBurst_MASK 0x780
-#define GMMx21A8_LazyTimer_OFFSET 11
-#define GMMx21A8_LazyTimer_WIDTH 4
-#define GMMx21A8_LazyTimer_MASK 0x7800
-#define GMMx21A8_StallOverrideWtm_OFFSET 15
-#define GMMx21A8_StallOverrideWtm_WIDTH 1
-#define GMMx21A8_StallOverrideWtm_MASK 0x8000
-#define GMMx21A8_Reserved_31_16_OFFSET 16
-#define GMMx21A8_Reserved_31_16_WIDTH 16
-#define GMMx21A8_Reserved_31_16_MASK 0xffff0000
+#define GMMx2024_Base_OFFSET 0
+#define GMMx2024_Base_WIDTH 16
+#define GMMx2024_Base_MASK 0xffff
+#define GMMx2024_Top_OFFSET 16
+#define GMMx2024_Top_WIDTH 16
+#define GMMx2024_Top_MASK 0xffff0000
-/// GMMx21A8
+/// GMMx2024
typedef union {
struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Base:16; ///<
+ UINT32 Top:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21A8_STRUCT;
+} GMMx2024_STRUCT;
-// **** GMMx21AC Register Definition ****
+// **** GMMx2028 Register Definition ****
// Address
-#define GMMx21AC_ADDRESS 0x21ac
+#define GMMx2028_ADDRESS 0x2028
// Type
-#define GMMx21AC_TYPE TYPE_GMM
+#define GMMx2028_TYPE TYPE_GMM
// Field Data
-#define GMMx21AC_Enable_OFFSET 0
-#define GMMx21AC_Enable_WIDTH 1
-#define GMMx21AC_Enable_MASK 0x1
-#define GMMx21AC_Prescale_OFFSET 1
-#define GMMx21AC_Prescale_WIDTH 2
-#define GMMx21AC_Prescale_MASK 0x6
-#define GMMx21AC_BlackoutExempt_OFFSET 3
-#define GMMx21AC_BlackoutExempt_WIDTH 1
-#define GMMx21AC_BlackoutExempt_MASK 0x8
-#define GMMx21AC_StallMode_OFFSET 4
-#define GMMx21AC_StallMode_WIDTH 2
-#define GMMx21AC_StallMode_MASK 0x30
-#define GMMx21AC_StallOverride_OFFSET 6
-#define GMMx21AC_StallOverride_WIDTH 1
-#define GMMx21AC_StallOverride_MASK 0x40
-#define GMMx21AC_MaxBurst_OFFSET 7
-#define GMMx21AC_MaxBurst_WIDTH 4
-#define GMMx21AC_MaxBurst_MASK 0x780
-#define GMMx21AC_LazyTimer_OFFSET 11
-#define GMMx21AC_LazyTimer_WIDTH 4
-#define GMMx21AC_LazyTimer_MASK 0x7800
-#define GMMx21AC_StallOverrideWtm_OFFSET 15
-#define GMMx21AC_StallOverrideWtm_WIDTH 1
-#define GMMx21AC_StallOverrideWtm_MASK 0x8000
-#define GMMx21AC_Reserved_31_16_OFFSET 16
-#define GMMx21AC_Reserved_31_16_WIDTH 16
-#define GMMx21AC_Reserved_31_16_MASK 0xffff0000
+#define GMMx2028_SysTop_39_22__OFFSET 0
+#define GMMx2028_SysTop_39_22__WIDTH 18
+#define GMMx2028_SysTop_39_22__MASK 0x3ffff
+#define GMMx2028_Reserved_31_18_OFFSET 18
+#define GMMx2028_Reserved_31_18_WIDTH 14
+#define GMMx2028_Reserved_31_18_MASK 0xfffc0000
-/// GMMx21AC
+/// GMMx2028
typedef union {
struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 SysTop_39_22_:18; ///<
+ UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21AC_STRUCT;
+} GMMx2028_STRUCT;
-// **** GMMx21B0 Register Definition ****
+// **** GMMx202C Register Definition ****
// Address
-#define GMMx21B0_ADDRESS 0x21b0
+#define GMMx202C_ADDRESS 0x202c
// Type
-#define GMMx21B0_TYPE TYPE_GMM
+#define GMMx202C_TYPE TYPE_GMM
// Field Data
-#define GMMx21B0_Enable_OFFSET 0
-#define GMMx21B0_Enable_WIDTH 1
-#define GMMx21B0_Enable_MASK 0x1
-#define GMMx21B0_Prescale_OFFSET 1
-#define GMMx21B0_Prescale_WIDTH 2
-#define GMMx21B0_Prescale_MASK 0x6
-#define GMMx21B0_BlackoutExempt_OFFSET 3
-#define GMMx21B0_BlackoutExempt_WIDTH 1
-#define GMMx21B0_BlackoutExempt_MASK 0x8
-#define GMMx21B0_StallMode_OFFSET 4
-#define GMMx21B0_StallMode_WIDTH 2
-#define GMMx21B0_StallMode_MASK 0x30
-#define GMMx21B0_StallOverride_OFFSET 6
-#define GMMx21B0_StallOverride_WIDTH 1
-#define GMMx21B0_StallOverride_MASK 0x40
-#define GMMx21B0_MaxBurst_OFFSET 7
-#define GMMx21B0_MaxBurst_WIDTH 4
-#define GMMx21B0_MaxBurst_MASK 0x780
-#define GMMx21B0_LazyTimer_OFFSET 11
-#define GMMx21B0_LazyTimer_WIDTH 4
-#define GMMx21B0_LazyTimer_MASK 0x7800
-#define GMMx21B0_StallOverrideWtm_OFFSET 15
-#define GMMx21B0_StallOverrideWtm_WIDTH 1
-#define GMMx21B0_StallOverrideWtm_MASK 0x8000
-#define GMMx21B0_Reserved_31_16_OFFSET 16
-#define GMMx21B0_Reserved_31_16_WIDTH 16
-#define GMMx21B0_Reserved_31_16_MASK 0xffff0000
+#define GMMx202C_SysBot_39_22__OFFSET 0
+#define GMMx202C_SysBot_39_22__WIDTH 18
+#define GMMx202C_SysBot_39_22__MASK 0x3ffff
+#define GMMx202C_Reserved_31_18_OFFSET 18
+#define GMMx202C_Reserved_31_18_WIDTH 14
+#define GMMx202C_Reserved_31_18_MASK 0xfffc0000
-/// GMMx21B0
+/// GMMx202C
typedef union {
struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 SysBot_39_22_:18; ///<
+ UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21B0_STRUCT;
+} GMMx202C_STRUCT;
-// **** GMMx21B4 Register Definition ****
+// **** GMMx20B4 Register Definition ****
// Address
-#define GMMx21B4_ADDRESS 0x21b4
+#define GMMx20B4_ADDRESS 0x20b4
// Type
-#define GMMx21B4_TYPE TYPE_GMM
+#define GMMx20B4_TYPE TYPE_GMM
// Field Data
-#define GMMx21B4_Enable_OFFSET 0
-#define GMMx21B4_Enable_WIDTH 1
-#define GMMx21B4_Enable_MASK 0x1
-#define GMMx21B4_Prescale_OFFSET 1
-#define GMMx21B4_Prescale_WIDTH 2
-#define GMMx21B4_Prescale_MASK 0x6
-#define GMMx21B4_BlackoutExempt_OFFSET 3
-#define GMMx21B4_BlackoutExempt_WIDTH 1
-#define GMMx21B4_BlackoutExempt_MASK 0x8
-#define GMMx21B4_StallMode_OFFSET 4
-#define GMMx21B4_StallMode_WIDTH 2
-#define GMMx21B4_StallMode_MASK 0x30
-#define GMMx21B4_StallOverride_OFFSET 6
-#define GMMx21B4_StallOverride_WIDTH 1
-#define GMMx21B4_StallOverride_MASK 0x40
-#define GMMx21B4_MaxBurst_OFFSET 7
-#define GMMx21B4_MaxBurst_WIDTH 4
-#define GMMx21B4_MaxBurst_MASK 0x780
-#define GMMx21B4_LazyTimer_OFFSET 11
-#define GMMx21B4_LazyTimer_WIDTH 4
-#define GMMx21B4_LazyTimer_MASK 0x7800
-#define GMMx21B4_StallOverrideWtm_OFFSET 15
-#define GMMx21B4_StallOverrideWtm_WIDTH 1
-#define GMMx21B4_StallOverrideWtm_MASK 0x8000
-#define GMMx21B4_Reserved_31_16_OFFSET 16
-#define GMMx21B4_Reserved_31_16_WIDTH 16
-#define GMMx21B4_Reserved_31_16_MASK 0xffff0000
+#define GMMx20B4_StutterMode_OFFSET 0
+#define GMMx20B4_StutterMode_WIDTH 2
+#define GMMx20B4_StutterMode_MASK 0x3
+#define GMMx20B4_GateOverride_OFFSET 2
+#define GMMx20B4_GateOverride_WIDTH 1
+#define GMMx20B4_GateOverride_MASK 0x4
+#define GMMx20B4_Reserved_31_3_OFFSET 3
+#define GMMx20B4_Reserved_31_3_WIDTH 29
+#define GMMx20B4_Reserved_31_3_MASK 0xfffffff8
-/// GMMx21B4
+/// GMMx20B4
+typedef union {
+ struct { ///<
+ UINT32 StutterMode:2 ; ///<
+ UINT32 GateOverride:1 ; ///<
+ UINT32 Reserved_31_3:29; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx20B4_STRUCT;
+
+// **** GMMx20B8 Register Definition ****
+// Address
+#define GMMx20B8_ADDRESS 0x20b8
+
+// Type
+#define GMMx20B8_TYPE TYPE_GMM
+// Field Data
+#define GMMx20B8_Reserved_17_0_OFFSET 0
+#define GMMx20B8_Reserved_17_0_WIDTH 18
+#define GMMx20B8_Reserved_17_0_MASK 0x3ffff
+#define GMMx20B8_Enable_OFFSET 18
+#define GMMx20B8_Enable_WIDTH 1
+#define GMMx20B8_Enable_MASK 0x40000
+#define GMMx20B8_Reserved_31_19_OFFSET 19
+#define GMMx20B8_Reserved_31_19_WIDTH 13
+#define GMMx20B8_Reserved_31_19_MASK 0xfff80000
+
+/// GMMx20B8
typedef union {
struct { ///<
+ UINT32 Reserved_17_0:18; ///<
UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21B4_STRUCT;
+} GMMx20B8_STRUCT;
-// **** GMMx21B8 Register Definition ****
+// **** GMMx20BC Register Definition ****
// Address
-#define GMMx21B8_ADDRESS 0x21b8
+#define GMMx20BC_ADDRESS 0x20bc
// Type
-#define GMMx21B8_TYPE TYPE_GMM
+#define GMMx20BC_TYPE TYPE_GMM
// Field Data
-#define GMMx21B8_Enable_OFFSET 0
-#define GMMx21B8_Enable_WIDTH 1
-#define GMMx21B8_Enable_MASK 0x1
-#define GMMx21B8_Prescale_OFFSET 1
-#define GMMx21B8_Prescale_WIDTH 2
-#define GMMx21B8_Prescale_MASK 0x6
-#define GMMx21B8_BlackoutExempt_OFFSET 3
-#define GMMx21B8_BlackoutExempt_WIDTH 1
-#define GMMx21B8_BlackoutExempt_MASK 0x8
-#define GMMx21B8_StallMode_OFFSET 4
-#define GMMx21B8_StallMode_WIDTH 2
-#define GMMx21B8_StallMode_MASK 0x30
-#define GMMx21B8_StallOverride_OFFSET 6
-#define GMMx21B8_StallOverride_WIDTH 1
-#define GMMx21B8_StallOverride_MASK 0x40
-#define GMMx21B8_MaxBurst_OFFSET 7
-#define GMMx21B8_MaxBurst_WIDTH 4
-#define GMMx21B8_MaxBurst_MASK 0x780
-#define GMMx21B8_LazyTimer_OFFSET 11
-#define GMMx21B8_LazyTimer_WIDTH 4
-#define GMMx21B8_LazyTimer_MASK 0x7800
-#define GMMx21B8_StallOverrideWtm_OFFSET 15
-#define GMMx21B8_StallOverrideWtm_WIDTH 1
-#define GMMx21B8_StallOverrideWtm_MASK 0x8000
-#define GMMx21B8_Reserved_31_16_OFFSET 16
-#define GMMx21B8_Reserved_31_16_WIDTH 16
-#define GMMx21B8_Reserved_31_16_MASK 0xffff0000
+#define GMMx20BC_Reserved_17_0_OFFSET 0
+#define GMMx20BC_Reserved_17_0_WIDTH 18
+#define GMMx20BC_Reserved_17_0_MASK 0x3ffff
+#define GMMx20BC_Enable_OFFSET 18
+#define GMMx20BC_Enable_WIDTH 1
+#define GMMx20BC_Enable_MASK 0x40000
+#define GMMx20BC_Reserved_31_19_OFFSET 19
+#define GMMx20BC_Reserved_31_19_WIDTH 13
+#define GMMx20BC_Reserved_31_19_MASK 0xfff80000
-/// GMMx21B8
+/// GMMx20BC
typedef union {
struct { ///<
+ UINT32 Reserved_17_0:18; ///<
UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21B8_STRUCT;
+} GMMx20BC_STRUCT;
-// **** GMMx21BC Register Definition ****
+// **** GMMx20C0 Register Definition ****
// Address
-#define GMMx21BC_ADDRESS 0x21bc
+#define GMMx20C0_ADDRESS 0x20c0
// Type
-#define GMMx21BC_TYPE TYPE_GMM
+#define GMMx20C0_TYPE TYPE_GMM
// Field Data
-#define GMMx21BC_Enable_OFFSET 0
-#define GMMx21BC_Enable_WIDTH 1
-#define GMMx21BC_Enable_MASK 0x1
-#define GMMx21BC_Prescale_OFFSET 1
-#define GMMx21BC_Prescale_WIDTH 2
-#define GMMx21BC_Prescale_MASK 0x6
-#define GMMx21BC_BlackoutExempt_OFFSET 3
-#define GMMx21BC_BlackoutExempt_WIDTH 1
-#define GMMx21BC_BlackoutExempt_MASK 0x8
-#define GMMx21BC_StallMode_OFFSET 4
-#define GMMx21BC_StallMode_WIDTH 2
-#define GMMx21BC_StallMode_MASK 0x30
-#define GMMx21BC_StallOverride_OFFSET 6
-#define GMMx21BC_StallOverride_WIDTH 1
-#define GMMx21BC_StallOverride_MASK 0x40
-#define GMMx21BC_MaxBurst_OFFSET 7
-#define GMMx21BC_MaxBurst_WIDTH 4
-#define GMMx21BC_MaxBurst_MASK 0x780
-#define GMMx21BC_LazyTimer_OFFSET 11
-#define GMMx21BC_LazyTimer_WIDTH 4
-#define GMMx21BC_LazyTimer_MASK 0x7800
-#define GMMx21BC_StallOverrideWtm_OFFSET 15
-#define GMMx21BC_StallOverrideWtm_WIDTH 1
-#define GMMx21BC_StallOverrideWtm_MASK 0x8000
-#define GMMx21BC_Reserved_31_16_OFFSET 16
-#define GMMx21BC_Reserved_31_16_WIDTH 16
-#define GMMx21BC_Reserved_31_16_MASK 0xffff0000
+#define GMMx20C0_Reserved_17_0_OFFSET 0
+#define GMMx20C0_Reserved_17_0_WIDTH 18
+#define GMMx20C0_Reserved_17_0_MASK 0x3ffff
+#define GMMx20C0_Enable_OFFSET 18
+#define GMMx20C0_Enable_WIDTH 1
+#define GMMx20C0_Enable_MASK 0x40000
+#define GMMx20C0_Reserved_31_19_OFFSET 19
+#define GMMx20C0_Reserved_31_19_WIDTH 13
+#define GMMx20C0_Reserved_31_19_MASK 0xfff80000
-/// GMMx21BC
+/// GMMx20C0
typedef union {
struct { ///<
+ UINT32 Reserved_17_0:18; ///<
UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21BC_STRUCT;
+} GMMx20C0_STRUCT;
-// **** GMMx21C0 Register Definition ****
+// **** GMMx20D4 Register Definition ****
// Address
-#define GMMx21C0_ADDRESS 0x21c0
+#define GMMx20D4_ADDRESS 0x20d4
// Type
-#define GMMx21C0_TYPE TYPE_GMM
+#define GMMx20D4_TYPE TYPE_GMM
// Field Data
-#define GMMx21C0_Enable_OFFSET 0
-#define GMMx21C0_Enable_WIDTH 1
-#define GMMx21C0_Enable_MASK 0x1
-#define GMMx21C0_Prescale_OFFSET 1
-#define GMMx21C0_Prescale_WIDTH 2
-#define GMMx21C0_Prescale_MASK 0x6
-#define GMMx21C0_BlackoutExempt_OFFSET 3
-#define GMMx21C0_BlackoutExempt_WIDTH 1
-#define GMMx21C0_BlackoutExempt_MASK 0x8
-#define GMMx21C0_StallMode_OFFSET 4
-#define GMMx21C0_StallMode_WIDTH 2
-#define GMMx21C0_StallMode_MASK 0x30
-#define GMMx21C0_StallOverride_OFFSET 6
-#define GMMx21C0_StallOverride_WIDTH 1
-#define GMMx21C0_StallOverride_MASK 0x40
-#define GMMx21C0_MaxBurst_OFFSET 7
-#define GMMx21C0_MaxBurst_WIDTH 4
-#define GMMx21C0_MaxBurst_MASK 0x780
-#define GMMx21C0_LazyTimer_OFFSET 11
-#define GMMx21C0_LazyTimer_WIDTH 4
-#define GMMx21C0_LazyTimer_MASK 0x7800
-#define GMMx21C0_StallOverrideWtm_OFFSET 15
-#define GMMx21C0_StallOverrideWtm_WIDTH 1
-#define GMMx21C0_StallOverrideWtm_MASK 0x8000
-#define GMMx21C0_Reserved_31_16_OFFSET 16
-#define GMMx21C0_Reserved_31_16_WIDTH 16
-#define GMMx21C0_Reserved_31_16_MASK 0xffff0000
+#define GMMx20D4_LocalBlackout_OFFSET 0
+#define GMMx20D4_LocalBlackout_WIDTH 1
+#define GMMx20D4_LocalBlackout_MASK 0x1
+#define GMMx20D4_Reserved_31_1_OFFSET 1
+#define GMMx20D4_Reserved_31_1_WIDTH 31
+#define GMMx20D4_Reserved_31_1_MASK 0xfffffffe
+
+/// GMMx20D4
+typedef union {
+ struct { ///<
+ UINT32 LocalBlackout:1 ; ///<
+ UINT32 Reserved_31_1:31; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx20D4_STRUCT;
-/// GMMx21C0
+// **** GMMx20EC Register Definition ****
+// Address
+#define GMMx20EC_ADDRESS 0x20ec
+
+// Type
+#define GMMx20EC_TYPE TYPE_GMM
+// Field Data
+#define GMMx20EC_RemoteBlackout_OFFSET 0
+#define GMMx20EC_RemoteBlackout_WIDTH 1
+#define GMMx20EC_RemoteBlackout_MASK 0x1
+#define GMMx20EC_LocalBlackout_OFFSET 1
+#define GMMx20EC_LocalBlackout_WIDTH 1
+#define GMMx20EC_LocalBlackout_MASK 0x2
+#define GMMx20EC_Reserved_31_2_OFFSET 2
+#define GMMx20EC_Reserved_31_2_WIDTH 30
+#define GMMx20EC_Reserved_31_2_MASK 0xfffffffc
+
+/// GMMx20EC
+typedef union {
+ struct { ///<
+ UINT32 RemoteBlackout:1 ; ///<
+ UINT32 LocalBlackout:1 ; ///<
+ UINT32 Reserved_31_2:30; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx20EC_STRUCT;
+
+// **** GMMx2160 Register Definition ****
+// Address
+#define GMMx2160_ADDRESS 0x2160
+
+// Type
+#define GMMx2160_TYPE TYPE_GMM
+// Field Data
+#define GMMx2160_Enable_OFFSET 0
+#define GMMx2160_Enable_WIDTH 1
+#define GMMx2160_Enable_MASK 0x1
+#define GMMx2160_Prescale_OFFSET 1
+#define GMMx2160_Prescale_WIDTH 2
+#define GMMx2160_Prescale_MASK 0x6
+#define GMMx2160_BlackoutExempt_OFFSET 3
+#define GMMx2160_BlackoutExempt_WIDTH 1
+#define GMMx2160_BlackoutExempt_MASK 0x8
+#define GMMx2160_StallMode_OFFSET 4
+#define GMMx2160_StallMode_WIDTH 2
+#define GMMx2160_StallMode_MASK 0x30
+#define GMMx2160_StallOverride_OFFSET 6
+#define GMMx2160_StallOverride_WIDTH 1
+#define GMMx2160_StallOverride_MASK 0x40
+#define GMMx2160_MaxBurst_OFFSET 7
+#define GMMx2160_MaxBurst_WIDTH 4
+#define GMMx2160_MaxBurst_MASK 0x780
+#define GMMx2160_LazyTimer_OFFSET 11
+#define GMMx2160_LazyTimer_WIDTH 4
+#define GMMx2160_LazyTimer_MASK 0x7800
+#define GMMx2160_StallOverrideWtm_OFFSET 15
+#define GMMx2160_StallOverrideWtm_WIDTH 1
+#define GMMx2160_StallOverrideWtm_MASK 0x8000
+#define GMMx2160_Reserved_19_16_OFFSET 16
+#define GMMx2160_Reserved_19_16_WIDTH 4
+#define GMMx2160_Reserved_19_16_MASK 0xf0000
+#define GMMx2160_Reserved_31_20_OFFSET 20
+#define GMMx2160_Reserved_31_20_WIDTH 12
+#define GMMx2160_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2160
typedef union {
struct { ///<
UINT32 Enable:1 ; ///<
UINT32 MaxBurst:4 ; ///<
UINT32 LazyTimer:4 ; ///<
UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21C0_STRUCT;
-
-// **** GMMx21C4 Register Definition ****
-// Address
-#define GMMx21C4_ADDRESS 0x21c4
-
-// Type
-#define GMMx21C4_TYPE TYPE_GMM
-// Field Data
-#define GMMx21C4_Enable_OFFSET 0
-#define GMMx21C4_Enable_WIDTH 1
-#define GMMx21C4_Enable_MASK 0x1
-#define GMMx21C4_Prescale_OFFSET 1
-#define GMMx21C4_Prescale_WIDTH 2
-#define GMMx21C4_Prescale_MASK 0x6
-#define GMMx21C4_BlackoutExempt_OFFSET 3
-#define GMMx21C4_BlackoutExempt_WIDTH 1
-#define GMMx21C4_BlackoutExempt_MASK 0x8
-#define GMMx21C4_StallMode_OFFSET 4
-#define GMMx21C4_StallMode_WIDTH 2
-#define GMMx21C4_StallMode_MASK 0x30
-#define GMMx21C4_StallOverride_OFFSET 6
-#define GMMx21C4_StallOverride_WIDTH 1
-#define GMMx21C4_StallOverride_MASK 0x40
-#define GMMx21C4_MaxBurst_OFFSET 7
-#define GMMx21C4_MaxBurst_WIDTH 4
-#define GMMx21C4_MaxBurst_MASK 0x780
-#define GMMx21C4_LazyTimer_OFFSET 11
-#define GMMx21C4_LazyTimer_WIDTH 4
-#define GMMx21C4_LazyTimer_MASK 0x7800
-#define GMMx21C4_StallOverrideWtm_OFFSET 15
-#define GMMx21C4_StallOverrideWtm_WIDTH 1
-#define GMMx21C4_StallOverrideWtm_MASK 0x8000
-#define GMMx21C4_Reserved_31_16_OFFSET 16
-#define GMMx21C4_Reserved_31_16_WIDTH 16
-#define GMMx21C4_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21C4
+} GMMx2160_STRUCT;
+
+// **** GMMx2164 Register Definition ****
+// Address
+#define GMMx2164_ADDRESS 0x2164
+
+// Type
+#define GMMx2164_TYPE TYPE_GMM
+// Field Data
+#define GMMx2164_Enable_OFFSET 0
+#define GMMx2164_Enable_WIDTH 1
+#define GMMx2164_Enable_MASK 0x1
+#define GMMx2164_Prescale_OFFSET 1
+#define GMMx2164_Prescale_WIDTH 2
+#define GMMx2164_Prescale_MASK 0x6
+#define GMMx2164_BlackoutExempt_OFFSET 3
+#define GMMx2164_BlackoutExempt_WIDTH 1
+#define GMMx2164_BlackoutExempt_MASK 0x8
+#define GMMx2164_StallMode_OFFSET 4
+#define GMMx2164_StallMode_WIDTH 2
+#define GMMx2164_StallMode_MASK 0x30
+#define GMMx2164_StallOverride_OFFSET 6
+#define GMMx2164_StallOverride_WIDTH 1
+#define GMMx2164_StallOverride_MASK 0x40
+#define GMMx2164_MaxBurst_OFFSET 7
+#define GMMx2164_MaxBurst_WIDTH 4
+#define GMMx2164_MaxBurst_MASK 0x780
+#define GMMx2164_LazyTimer_OFFSET 11
+#define GMMx2164_LazyTimer_WIDTH 4
+#define GMMx2164_LazyTimer_MASK 0x7800
+#define GMMx2164_StallOverrideWtm_OFFSET 15
+#define GMMx2164_StallOverrideWtm_WIDTH 1
+#define GMMx2164_StallOverrideWtm_MASK 0x8000
+#define GMMx2164_Reserved_19_16_OFFSET 16
+#define GMMx2164_Reserved_19_16_WIDTH 4
+#define GMMx2164_Reserved_19_16_MASK 0xf0000
+#define GMMx2164_Reserved_31_20_OFFSET 20
+#define GMMx2164_Reserved_31_20_WIDTH 12
+#define GMMx2164_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2164
typedef union {
struct { ///<
UINT32 Enable:1 ; ///<
UINT32 MaxBurst:4 ; ///<
UINT32 LazyTimer:4 ; ///<
UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21C4_STRUCT;
-
-// **** GMMx21C8 Register Definition ****
-// Address
-#define GMMx21C8_ADDRESS 0x21c8
-
-// Type
-#define GMMx21C8_TYPE TYPE_GMM
-// Field Data
-#define GMMx21C8_Enable_OFFSET 0
-#define GMMx21C8_Enable_WIDTH 1
-#define GMMx21C8_Enable_MASK 0x1
-#define GMMx21C8_Prescale_OFFSET 1
-#define GMMx21C8_Prescale_WIDTH 2
-#define GMMx21C8_Prescale_MASK 0x6
-#define GMMx21C8_BlackoutExempt_OFFSET 3
-#define GMMx21C8_BlackoutExempt_WIDTH 1
-#define GMMx21C8_BlackoutExempt_MASK 0x8
-#define GMMx21C8_StallMode_OFFSET 4
-#define GMMx21C8_StallMode_WIDTH 2
-#define GMMx21C8_StallMode_MASK 0x30
-#define GMMx21C8_StallOverride_OFFSET 6
-#define GMMx21C8_StallOverride_WIDTH 1
-#define GMMx21C8_StallOverride_MASK 0x40
-#define GMMx21C8_MaxBurst_OFFSET 7
-#define GMMx21C8_MaxBurst_WIDTH 4
-#define GMMx21C8_MaxBurst_MASK 0x780
-#define GMMx21C8_LazyTimer_OFFSET 11
-#define GMMx21C8_LazyTimer_WIDTH 4
-#define GMMx21C8_LazyTimer_MASK 0x7800
-#define GMMx21C8_StallOverrideWtm_OFFSET 15
-#define GMMx21C8_StallOverrideWtm_WIDTH 1
-#define GMMx21C8_StallOverrideWtm_MASK 0x8000
-#define GMMx21C8_Reserved_31_16_OFFSET 16
-#define GMMx21C8_Reserved_31_16_WIDTH 16
-#define GMMx21C8_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21C8
+} GMMx2164_STRUCT;
+
+// **** GMMx2168 Register Definition ****
+// Address
+#define GMMx2168_ADDRESS 0x2168
+
+// Type
+#define GMMx2168_TYPE TYPE_GMM
+// Field Data
+#define GMMx2168_Enable_OFFSET 0
+#define GMMx2168_Enable_WIDTH 1
+#define GMMx2168_Enable_MASK 0x1
+#define GMMx2168_Prescale_OFFSET 1
+#define GMMx2168_Prescale_WIDTH 2
+#define GMMx2168_Prescale_MASK 0x6
+#define GMMx2168_BlackoutExempt_OFFSET 3
+#define GMMx2168_BlackoutExempt_WIDTH 1
+#define GMMx2168_BlackoutExempt_MASK 0x8
+#define GMMx2168_StallMode_OFFSET 4
+#define GMMx2168_StallMode_WIDTH 2
+#define GMMx2168_StallMode_MASK 0x30
+#define GMMx2168_StallOverride_OFFSET 6
+#define GMMx2168_StallOverride_WIDTH 1
+#define GMMx2168_StallOverride_MASK 0x40
+#define GMMx2168_MaxBurst_OFFSET 7
+#define GMMx2168_MaxBurst_WIDTH 4
+#define GMMx2168_MaxBurst_MASK 0x780
+#define GMMx2168_LazyTimer_OFFSET 11
+#define GMMx2168_LazyTimer_WIDTH 4
+#define GMMx2168_LazyTimer_MASK 0x7800
+#define GMMx2168_StallOverrideWtm_OFFSET 15
+#define GMMx2168_StallOverrideWtm_WIDTH 1
+#define GMMx2168_StallOverrideWtm_MASK 0x8000
+#define GMMx2168_Reserved_19_16_OFFSET 16
+#define GMMx2168_Reserved_19_16_WIDTH 4
+#define GMMx2168_Reserved_19_16_MASK 0xf0000
+#define GMMx2168_Reserved_31_20_OFFSET 20
+#define GMMx2168_Reserved_31_20_WIDTH 12
+#define GMMx2168_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2168
typedef union {
struct { ///<
UINT32 Enable:1 ; ///<
UINT32 MaxBurst:4 ; ///<
UINT32 LazyTimer:4 ; ///<
UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21C8_STRUCT;
-
-// **** GMMx21CC Register Definition ****
-// Address
-#define GMMx21CC_ADDRESS 0x21cc
-
-// Type
-#define GMMx21CC_TYPE TYPE_GMM
-// Field Data
-#define GMMx21CC_Enable_OFFSET 0
-#define GMMx21CC_Enable_WIDTH 1
-#define GMMx21CC_Enable_MASK 0x1
-#define GMMx21CC_Prescale_OFFSET 1
-#define GMMx21CC_Prescale_WIDTH 2
-#define GMMx21CC_Prescale_MASK 0x6
-#define GMMx21CC_BlackoutExempt_OFFSET 3
-#define GMMx21CC_BlackoutExempt_WIDTH 1
-#define GMMx21CC_BlackoutExempt_MASK 0x8
-#define GMMx21CC_StallMode_OFFSET 4
-#define GMMx21CC_StallMode_WIDTH 2
-#define GMMx21CC_StallMode_MASK 0x30
-#define GMMx21CC_StallOverride_OFFSET 6
-#define GMMx21CC_StallOverride_WIDTH 1
-#define GMMx21CC_StallOverride_MASK 0x40
-#define GMMx21CC_MaxBurst_OFFSET 7
-#define GMMx21CC_MaxBurst_WIDTH 4
-#define GMMx21CC_MaxBurst_MASK 0x780
-#define GMMx21CC_LazyTimer_OFFSET 11
-#define GMMx21CC_LazyTimer_WIDTH 4
-#define GMMx21CC_LazyTimer_MASK 0x7800
-#define GMMx21CC_StallOverrideWtm_OFFSET 15
-#define GMMx21CC_StallOverrideWtm_WIDTH 1
-#define GMMx21CC_StallOverrideWtm_MASK 0x8000
-#define GMMx21CC_Reserved_31_16_OFFSET 16
-#define GMMx21CC_Reserved_31_16_WIDTH 16
-#define GMMx21CC_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21CC
+} GMMx2168_STRUCT;
+
+// **** GMMx216C Register Definition ****
+// Address
+#define GMMx216C_ADDRESS 0x216c
+
+// Type
+#define GMMx216C_TYPE TYPE_GMM
+// Field Data
+#define GMMx216C_Enable_OFFSET 0
+#define GMMx216C_Enable_WIDTH 1
+#define GMMx216C_Enable_MASK 0x1
+#define GMMx216C_Prescale_OFFSET 1
+#define GMMx216C_Prescale_WIDTH 2
+#define GMMx216C_Prescale_MASK 0x6
+#define GMMx216C_BlackoutExempt_OFFSET 3
+#define GMMx216C_BlackoutExempt_WIDTH 1
+#define GMMx216C_BlackoutExempt_MASK 0x8
+#define GMMx216C_StallMode_OFFSET 4
+#define GMMx216C_StallMode_WIDTH 2
+#define GMMx216C_StallMode_MASK 0x30
+#define GMMx216C_StallOverride_OFFSET 6
+#define GMMx216C_StallOverride_WIDTH 1
+#define GMMx216C_StallOverride_MASK 0x40
+#define GMMx216C_MaxBurst_OFFSET 7
+#define GMMx216C_MaxBurst_WIDTH 4
+#define GMMx216C_MaxBurst_MASK 0x780
+#define GMMx216C_LazyTimer_OFFSET 11
+#define GMMx216C_LazyTimer_WIDTH 4
+#define GMMx216C_LazyTimer_MASK 0x7800
+#define GMMx216C_StallOverrideWtm_OFFSET 15
+#define GMMx216C_StallOverrideWtm_WIDTH 1
+#define GMMx216C_StallOverrideWtm_MASK 0x8000
+#define GMMx216C_Reserved_19_16_OFFSET 16
+#define GMMx216C_Reserved_19_16_WIDTH 4
+#define GMMx216C_Reserved_19_16_MASK 0xf0000
+#define GMMx216C_Reserved_31_20_OFFSET 20
+#define GMMx216C_Reserved_31_20_WIDTH 12
+#define GMMx216C_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx216C
typedef union {
struct { ///<
UINT32 Enable:1 ; ///<
UINT32 MaxBurst:4 ; ///<
UINT32 LazyTimer:4 ; ///<
UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21CC_STRUCT;
-
-// **** GMMx21D0 Register Definition ****
-// Address
-#define GMMx21D0_ADDRESS 0x21d0
-
-// Type
-#define GMMx21D0_TYPE TYPE_GMM
-// Field Data
-#define GMMx21D0_Enable_OFFSET 0
-#define GMMx21D0_Enable_WIDTH 1
-#define GMMx21D0_Enable_MASK 0x1
-#define GMMx21D0_Prescale_OFFSET 1
-#define GMMx21D0_Prescale_WIDTH 2
-#define GMMx21D0_Prescale_MASK 0x6
-#define GMMx21D0_BlackoutExempt_OFFSET 3
-#define GMMx21D0_BlackoutExempt_WIDTH 1
-#define GMMx21D0_BlackoutExempt_MASK 0x8
-#define GMMx21D0_StallMode_OFFSET 4
-#define GMMx21D0_StallMode_WIDTH 2
-#define GMMx21D0_StallMode_MASK 0x30
-#define GMMx21D0_StallOverride_OFFSET 6
-#define GMMx21D0_StallOverride_WIDTH 1
-#define GMMx21D0_StallOverride_MASK 0x40
-#define GMMx21D0_MaxBurst_OFFSET 7
-#define GMMx21D0_MaxBurst_WIDTH 4
-#define GMMx21D0_MaxBurst_MASK 0x780
-#define GMMx21D0_LazyTimer_OFFSET 11
-#define GMMx21D0_LazyTimer_WIDTH 4
-#define GMMx21D0_LazyTimer_MASK 0x7800
-#define GMMx21D0_StallOverrideWtm_OFFSET 15
-#define GMMx21D0_StallOverrideWtm_WIDTH 1
-#define GMMx21D0_StallOverrideWtm_MASK 0x8000
-#define GMMx21D0_Reserved_31_16_OFFSET 16
-#define GMMx21D0_Reserved_31_16_WIDTH 16
-#define GMMx21D0_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21D0
+} GMMx216C_STRUCT;
+
+// **** GMMx2170 Register Definition ****
+// Address
+#define GMMx2170_ADDRESS 0x2170
+
+// Type
+#define GMMx2170_TYPE TYPE_GMM
+// Field Data
+#define GMMx2170_Enable_OFFSET 0
+#define GMMx2170_Enable_WIDTH 1
+#define GMMx2170_Enable_MASK 0x1
+#define GMMx2170_Prescale_OFFSET 1
+#define GMMx2170_Prescale_WIDTH 2
+#define GMMx2170_Prescale_MASK 0x6
+#define GMMx2170_BlackoutExempt_OFFSET 3
+#define GMMx2170_BlackoutExempt_WIDTH 1
+#define GMMx2170_BlackoutExempt_MASK 0x8
+#define GMMx2170_StallMode_OFFSET 4
+#define GMMx2170_StallMode_WIDTH 2
+#define GMMx2170_StallMode_MASK 0x30
+#define GMMx2170_StallOverride_OFFSET 6
+#define GMMx2170_StallOverride_WIDTH 1
+#define GMMx2170_StallOverride_MASK 0x40
+#define GMMx2170_MaxBurst_OFFSET 7
+#define GMMx2170_MaxBurst_WIDTH 4
+#define GMMx2170_MaxBurst_MASK 0x780
+#define GMMx2170_LazyTimer_OFFSET 11
+#define GMMx2170_LazyTimer_WIDTH 4
+#define GMMx2170_LazyTimer_MASK 0x7800
+#define GMMx2170_StallOverrideWtm_OFFSET 15
+#define GMMx2170_StallOverrideWtm_WIDTH 1
+#define GMMx2170_StallOverrideWtm_MASK 0x8000
+#define GMMx2170_Reserved_19_16_OFFSET 16
+#define GMMx2170_Reserved_19_16_WIDTH 4
+#define GMMx2170_Reserved_19_16_MASK 0xf0000
+#define GMMx2170_Reserved_31_20_OFFSET 20
+#define GMMx2170_Reserved_31_20_WIDTH 12
+#define GMMx2170_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2170
typedef union {
struct { ///<
UINT32 Enable:1 ; ///<
UINT32 MaxBurst:4 ; ///<
UINT32 LazyTimer:4 ; ///<
UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx21D0_STRUCT;
-
-// **** GMMx25C0 Register Definition ****
-// Address
-#define GMMx25C0_ADDRESS 0x25c0
-
-// Type
-#define GMMx25C0_TYPE TYPE_GMM
-// Field Data
-#define GMMx25C0_BlackoutRd_OFFSET 0
-#define GMMx25C0_BlackoutRd_WIDTH 1
-#define GMMx25C0_BlackoutRd_MASK 0x1
-#define GMMx25C0_BlackoutWr_OFFSET 1
-#define GMMx25C0_BlackoutWr_WIDTH 1
-#define GMMx25C0_BlackoutWr_MASK 0x2
-#define GMMx25C0_Reserved_31_2_OFFSET 2
-#define GMMx25C0_Reserved_31_2_WIDTH 30
-#define GMMx25C0_Reserved_31_2_MASK 0xfffffffc
-
-/// GMMx25C0
+} GMMx2170_STRUCT;
+
+// **** GMMx2174 Register Definition ****
+// Address
+#define GMMx2174_ADDRESS 0x2174
+
+// Type
+#define GMMx2174_TYPE TYPE_GMM
+// Field Data
+#define GMMx2174_Enable_OFFSET 0
+#define GMMx2174_Enable_WIDTH 1
+#define GMMx2174_Enable_MASK 0x1
+#define GMMx2174_Prescale_OFFSET 1
+#define GMMx2174_Prescale_WIDTH 2
+#define GMMx2174_Prescale_MASK 0x6
+#define GMMx2174_BlackoutExempt_OFFSET 3
+#define GMMx2174_BlackoutExempt_WIDTH 1
+#define GMMx2174_BlackoutExempt_MASK 0x8
+#define GMMx2174_StallMode_OFFSET 4
+#define GMMx2174_StallMode_WIDTH 2
+#define GMMx2174_StallMode_MASK 0x30
+#define GMMx2174_StallOverride_OFFSET 6
+#define GMMx2174_StallOverride_WIDTH 1
+#define GMMx2174_StallOverride_MASK 0x40
+#define GMMx2174_MaxBurst_OFFSET 7
+#define GMMx2174_MaxBurst_WIDTH 4
+#define GMMx2174_MaxBurst_MASK 0x780
+#define GMMx2174_LazyTimer_OFFSET 11
+#define GMMx2174_LazyTimer_WIDTH 4
+#define GMMx2174_LazyTimer_MASK 0x7800
+#define GMMx2174_StallOverrideWtm_OFFSET 15
+#define GMMx2174_StallOverrideWtm_WIDTH 1
+#define GMMx2174_StallOverrideWtm_MASK 0x8000
+#define GMMx2174_Reserved_19_16_OFFSET 16
+#define GMMx2174_Reserved_19_16_WIDTH 4
+#define GMMx2174_Reserved_19_16_MASK 0xf0000
+#define GMMx2174_Reserved_31_20_OFFSET 20
+#define GMMx2174_Reserved_31_20_WIDTH 12
+#define GMMx2174_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2174
typedef union {
struct { ///<
- UINT32 BlackoutRd:1 ; ///<
- UINT32 BlackoutWr:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx25C0_STRUCT;
-
-// **** GMMx25C8 Register Definition ****
-// Address
-#define GMMx25C8_ADDRESS 0x25c8
-
-// Type
-#define GMMx25C8_TYPE TYPE_GMM
-// Field Data
-#define GMMx25C8_ReadLcl_OFFSET 0
-#define GMMx25C8_ReadLcl_WIDTH 8
-#define GMMx25C8_ReadLcl_MASK 0xff
-#define GMMx25C8_ReadHub_OFFSET 8
-#define GMMx25C8_ReadHub_WIDTH 8
-#define GMMx25C8_ReadHub_MASK 0xff00
-#define GMMx25C8_ReadPri_OFFSET 16
-#define GMMx25C8_ReadPri_WIDTH 8
-#define GMMx25C8_ReadPri_MASK 0xff0000
-#define GMMx25C8_LclPri_OFFSET 24
-#define GMMx25C8_LclPri_WIDTH 1
-#define GMMx25C8_LclPri_MASK 0x1000000
-#define GMMx25C8_HubPri_OFFSET 25
-#define GMMx25C8_HubPri_WIDTH 1
-#define GMMx25C8_HubPri_MASK 0x2000000
-#define GMMx25C8_Reserved_31_26_OFFSET 26
-#define GMMx25C8_Reserved_31_26_WIDTH 6
-#define GMMx25C8_Reserved_31_26_MASK 0xfc000000
-
-/// GMMx25C8
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx2174_STRUCT;
+
+// **** GMMx2178 Register Definition ****
+// Address
+#define GMMx2178_ADDRESS 0x2178
+
+// Type
+#define GMMx2178_TYPE TYPE_GMM
+// Field Data
+#define GMMx2178_Enable_OFFSET 0
+#define GMMx2178_Enable_WIDTH 1
+#define GMMx2178_Enable_MASK 0x1
+#define GMMx2178_Prescale_OFFSET 1
+#define GMMx2178_Prescale_WIDTH 2
+#define GMMx2178_Prescale_MASK 0x6
+#define GMMx2178_BlackoutExempt_OFFSET 3
+#define GMMx2178_BlackoutExempt_WIDTH 1
+#define GMMx2178_BlackoutExempt_MASK 0x8
+#define GMMx2178_StallMode_OFFSET 4
+#define GMMx2178_StallMode_WIDTH 2
+#define GMMx2178_StallMode_MASK 0x30
+#define GMMx2178_StallOverride_OFFSET 6
+#define GMMx2178_StallOverride_WIDTH 1
+#define GMMx2178_StallOverride_MASK 0x40
+#define GMMx2178_MaxBurst_OFFSET 7
+#define GMMx2178_MaxBurst_WIDTH 4
+#define GMMx2178_MaxBurst_MASK 0x780
+#define GMMx2178_LazyTimer_OFFSET 11
+#define GMMx2178_LazyTimer_WIDTH 4
+#define GMMx2178_LazyTimer_MASK 0x7800
+#define GMMx2178_StallOverrideWtm_OFFSET 15
+#define GMMx2178_StallOverrideWtm_WIDTH 1
+#define GMMx2178_StallOverrideWtm_MASK 0x8000
+#define GMMx2178_Reserved_19_16_OFFSET 16
+#define GMMx2178_Reserved_19_16_WIDTH 4
+#define GMMx2178_Reserved_19_16_MASK 0xf0000
+#define GMMx2178_Reserved_31_20_OFFSET 20
+#define GMMx2178_Reserved_31_20_WIDTH 12
+#define GMMx2178_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2178
typedef union {
struct { ///<
- UINT32 ReadLcl:8 ; ///<
- UINT32 ReadHub:8 ; ///<
- UINT32 ReadPri:8 ; ///<
- UINT32 LclPri:1 ; ///<
- UINT32 HubPri:1 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx25C8_STRUCT;
+} GMMx2178_STRUCT;
-// **** GMMx25CC Register Definition ****
+// **** GMMx217C Register Definition ****
// Address
-#define GMMx25CC_ADDRESS 0x25cc
+#define GMMx217C_ADDRESS 0x217c
// Type
-#define GMMx25CC_TYPE TYPE_GMM
-// Field Data
-#define GMMx25CC_WriteLcl_OFFSET 0
-#define GMMx25CC_WriteLcl_WIDTH 8
-#define GMMx25CC_WriteLcl_MASK 0xff
-#define GMMx25CC_WriteHub_OFFSET 8
-#define GMMx25CC_WriteHub_WIDTH 8
-#define GMMx25CC_WriteHub_MASK 0xff00
-#define GMMx25CC_HubPri_OFFSET 16
-#define GMMx25CC_HubPri_WIDTH 1
-#define GMMx25CC_HubPri_MASK 0x10000
-#define GMMx25CC_Reserved_31_17_OFFSET 17
-#define GMMx25CC_Reserved_31_17_WIDTH 15
-#define GMMx25CC_Reserved_31_17_MASK 0xfffe0000
-
-/// GMMx25CC
+#define GMMx217C_TYPE TYPE_GMM
+// Field Data
+#define GMMx217C_Enable_OFFSET 0
+#define GMMx217C_Enable_WIDTH 1
+#define GMMx217C_Enable_MASK 0x1
+#define GMMx217C_Prescale_OFFSET 1
+#define GMMx217C_Prescale_WIDTH 2
+#define GMMx217C_Prescale_MASK 0x6
+#define GMMx217C_BlackoutExempt_OFFSET 3
+#define GMMx217C_BlackoutExempt_WIDTH 1
+#define GMMx217C_BlackoutExempt_MASK 0x8
+#define GMMx217C_StallMode_OFFSET 4
+#define GMMx217C_StallMode_WIDTH 2
+#define GMMx217C_StallMode_MASK 0x30
+#define GMMx217C_StallOverride_OFFSET 6
+#define GMMx217C_StallOverride_WIDTH 1
+#define GMMx217C_StallOverride_MASK 0x40
+#define GMMx217C_MaxBurst_OFFSET 7
+#define GMMx217C_MaxBurst_WIDTH 4
+#define GMMx217C_MaxBurst_MASK 0x780
+#define GMMx217C_LazyTimer_OFFSET 11
+#define GMMx217C_LazyTimer_WIDTH 4
+#define GMMx217C_LazyTimer_MASK 0x7800
+#define GMMx217C_StallOverrideWtm_OFFSET 15
+#define GMMx217C_StallOverrideWtm_WIDTH 1
+#define GMMx217C_StallOverrideWtm_MASK 0x8000
+#define GMMx217C_Reserved_19_16_OFFSET 16
+#define GMMx217C_Reserved_19_16_WIDTH 4
+#define GMMx217C_Reserved_19_16_MASK 0xf0000
+#define GMMx217C_Reserved_31_20_OFFSET 20
+#define GMMx217C_Reserved_31_20_WIDTH 12
+#define GMMx217C_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx217C
typedef union {
struct { ///<
- UINT32 WriteLcl:8 ; ///<
- UINT32 WriteHub:8 ; ///<
- UINT32 HubPri:1 ; ///<
- UINT32 Reserved_31_17:15; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx25CC_STRUCT;
-
-// **** GMMx2610 Register Definition ****
-// Address
-#define GMMx2610_ADDRESS 0x2610
-
-// Type
-#define GMMx2610_TYPE TYPE_GMM
-// Field Data
-#define GMMx2610_TctFetch0_OFFSET 0
-#define GMMx2610_TctFetch0_WIDTH 4
-#define GMMx2610_TctFetch0_MASK 0xf
-#define GMMx2610_TcvFetch0_OFFSET 4
-#define GMMx2610_TcvFetch0_WIDTH 4
-#define GMMx2610_TcvFetch0_MASK 0xf0
-#define GMMx2610_Vc0_OFFSET 8
-#define GMMx2610_Vc0_WIDTH 4
-#define GMMx2610_Vc0_MASK 0xf00
-#define GMMx2610_Cb0_OFFSET 12
-#define GMMx2610_Cb0_WIDTH 4
-#define GMMx2610_Cb0_MASK 0xf000
-#define GMMx2610_CbcMask0_OFFSET 16
-#define GMMx2610_CbcMask0_WIDTH 4
-#define GMMx2610_CbcMask0_MASK 0xf0000
-#define GMMx2610_CbfMask0_OFFSET 20
-#define GMMx2610_CbfMask0_WIDTH 4
-#define GMMx2610_CbfMask0_MASK 0xf00000
-#define GMMx2610_Db0_OFFSET 24
-#define GMMx2610_Db0_WIDTH 4
-#define GMMx2610_Db0_MASK 0xf000000
-#define GMMx2610_DbhTile0_OFFSET 28
-#define GMMx2610_DbhTile0_WIDTH 4
-#define GMMx2610_DbhTile0_MASK 0xf0000000
-
-/// GMMx2610
+} GMMx217C_STRUCT;
+
+// **** GMMx2180 Register Definition ****
+// Address
+#define GMMx2180_ADDRESS 0x2180
+
+// Type
+#define GMMx2180_TYPE TYPE_GMM
+// Field Data
+#define GMMx2180_Enable_OFFSET 0
+#define GMMx2180_Enable_WIDTH 1
+#define GMMx2180_Enable_MASK 0x1
+#define GMMx2180_Prescale_OFFSET 1
+#define GMMx2180_Prescale_WIDTH 2
+#define GMMx2180_Prescale_MASK 0x6
+#define GMMx2180_BlackoutExempt_OFFSET 3
+#define GMMx2180_BlackoutExempt_WIDTH 1
+#define GMMx2180_BlackoutExempt_MASK 0x8
+#define GMMx2180_StallMode_OFFSET 4
+#define GMMx2180_StallMode_WIDTH 2
+#define GMMx2180_StallMode_MASK 0x30
+#define GMMx2180_StallOverride_OFFSET 6
+#define GMMx2180_StallOverride_WIDTH 1
+#define GMMx2180_StallOverride_MASK 0x40
+#define GMMx2180_MaxBurst_OFFSET 7
+#define GMMx2180_MaxBurst_WIDTH 4
+#define GMMx2180_MaxBurst_MASK 0x780
+#define GMMx2180_LazyTimer_OFFSET 11
+#define GMMx2180_LazyTimer_WIDTH 4
+#define GMMx2180_LazyTimer_MASK 0x7800
+#define GMMx2180_StallOverrideWtm_OFFSET 15
+#define GMMx2180_StallOverrideWtm_WIDTH 1
+#define GMMx2180_StallOverrideWtm_MASK 0x8000
+#define GMMx2180_Reserved_19_16_OFFSET 16
+#define GMMx2180_Reserved_19_16_WIDTH 4
+#define GMMx2180_Reserved_19_16_MASK 0xf0000
+#define GMMx2180_Reserved_31_20_OFFSET 20
+#define GMMx2180_Reserved_31_20_WIDTH 12
+#define GMMx2180_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2180
typedef union {
struct { ///<
- UINT32 TctFetch0:4 ; ///<
- UINT32 TcvFetch0:4 ; ///<
- UINT32 Vc0:4 ; ///<
- UINT32 Cb0:4 ; ///<
- UINT32 CbcMask0:4 ; ///<
- UINT32 CbfMask0:4 ; ///<
- UINT32 Db0:4 ; ///<
- UINT32 DbhTile0:4 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2610_STRUCT;
-
-// **** GMMx2614 Register Definition ****
-// Address
-#define GMMx2614_ADDRESS 0x2614
-
-// Type
-#define GMMx2614_TYPE TYPE_GMM
-// Field Data
-#define GMMx2614_Cb0_OFFSET 0
-#define GMMx2614_Cb0_WIDTH 4
-#define GMMx2614_Cb0_MASK 0xf
-#define GMMx2614_CbcMask0_OFFSET 4
-#define GMMx2614_CbcMask0_WIDTH 4
-#define GMMx2614_CbcMask0_MASK 0xf0
-#define GMMx2614_CbfMask0_OFFSET 8
-#define GMMx2614_CbfMask0_WIDTH 4
-#define GMMx2614_CbfMask0_MASK 0xf00
-#define GMMx2614_Db0_OFFSET 12
-#define GMMx2614_Db0_WIDTH 4
-#define GMMx2614_Db0_MASK 0xf000
-#define GMMx2614_DbhTile0_OFFSET 16
-#define GMMx2614_DbhTile0_WIDTH 4
-#define GMMx2614_DbhTile0_MASK 0xf0000
-#define GMMx2614_Sx0_OFFSET 20
-#define GMMx2614_Sx0_WIDTH 4
-#define GMMx2614_Sx0_MASK 0xf00000
-#define GMMx2614_Bcast0_OFFSET 24
-#define GMMx2614_Bcast0_WIDTH 4
-#define GMMx2614_Bcast0_MASK 0xf000000
-#define GMMx2614_Cbimmed0_OFFSET 28
-#define GMMx2614_Cbimmed0_WIDTH 4
-#define GMMx2614_Cbimmed0_MASK 0xf0000000
-
-/// GMMx2614
+} GMMx2180_STRUCT;
+
+// **** GMMx2184 Register Definition ****
+// Address
+#define GMMx2184_ADDRESS 0x2184
+
+// Type
+#define GMMx2184_TYPE TYPE_GMM
+// Field Data
+#define GMMx2184_Enable_OFFSET 0
+#define GMMx2184_Enable_WIDTH 1
+#define GMMx2184_Enable_MASK 0x1
+#define GMMx2184_Prescale_OFFSET 1
+#define GMMx2184_Prescale_WIDTH 2
+#define GMMx2184_Prescale_MASK 0x6
+#define GMMx2184_BlackoutExempt_OFFSET 3
+#define GMMx2184_BlackoutExempt_WIDTH 1
+#define GMMx2184_BlackoutExempt_MASK 0x8
+#define GMMx2184_StallMode_OFFSET 4
+#define GMMx2184_StallMode_WIDTH 2
+#define GMMx2184_StallMode_MASK 0x30
+#define GMMx2184_StallOverride_OFFSET 6
+#define GMMx2184_StallOverride_WIDTH 1
+#define GMMx2184_StallOverride_MASK 0x40
+#define GMMx2184_MaxBurst_OFFSET 7
+#define GMMx2184_MaxBurst_WIDTH 4
+#define GMMx2184_MaxBurst_MASK 0x780
+#define GMMx2184_LazyTimer_OFFSET 11
+#define GMMx2184_LazyTimer_WIDTH 4
+#define GMMx2184_LazyTimer_MASK 0x7800
+#define GMMx2184_StallOverrideWtm_OFFSET 15
+#define GMMx2184_StallOverrideWtm_WIDTH 1
+#define GMMx2184_StallOverrideWtm_MASK 0x8000
+#define GMMx2184_Reserved_19_16_OFFSET 16
+#define GMMx2184_Reserved_19_16_WIDTH 4
+#define GMMx2184_Reserved_19_16_MASK 0xf0000
+#define GMMx2184_Reserved_31_20_OFFSET 20
+#define GMMx2184_Reserved_31_20_WIDTH 12
+#define GMMx2184_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2184
typedef union {
struct { ///<
- UINT32 Cb0:4 ; ///<
- UINT32 CbcMask0:4 ; ///<
- UINT32 CbfMask0:4 ; ///<
- UINT32 Db0:4 ; ///<
- UINT32 DbhTile0:4 ; ///<
- UINT32 Sx0:4 ; ///<
- UINT32 Bcast0:4 ; ///<
- UINT32 Cbimmed0:4 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2614_STRUCT;
+} GMMx2184_STRUCT;
-// **** GMMx2618 Register Definition ****
+// **** GMMx2188 Register Definition ****
// Address
-#define GMMx2618_ADDRESS 0x2618
+#define GMMx2188_ADDRESS 0x2188
// Type
-#define GMMx2618_TYPE TYPE_GMM
-// Field Data
-#define GMMx2618_DbstEn0_OFFSET 0
-#define GMMx2618_DbstEn0_WIDTH 4
-#define GMMx2618_DbstEn0_MASK 0xf
-#define GMMx2618_TcvFetch1_OFFSET 4
-#define GMMx2618_TcvFetch1_WIDTH 4
-#define GMMx2618_TcvFetch1_MASK 0xf0
-#define GMMx2618_TctFetch1_OFFSET 8
-#define GMMx2618_TctFetch1_WIDTH 4
-#define GMMx2618_TctFetch1_MASK 0xf00
-#define GMMx2618_Vc1_OFFSET 12
-#define GMMx2618_Vc1_WIDTH 4
-#define GMMx2618_Vc1_MASK 0xf000
-#define GMMx2618_Reserved_31_16_OFFSET 16
-#define GMMx2618_Reserved_31_16_WIDTH 16
-#define GMMx2618_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx2618
+#define GMMx2188_TYPE TYPE_GMM
+// Field Data
+#define GMMx2188_Enable_OFFSET 0
+#define GMMx2188_Enable_WIDTH 1
+#define GMMx2188_Enable_MASK 0x1
+#define GMMx2188_Prescale_OFFSET 1
+#define GMMx2188_Prescale_WIDTH 2
+#define GMMx2188_Prescale_MASK 0x6
+#define GMMx2188_BlackoutExempt_OFFSET 3
+#define GMMx2188_BlackoutExempt_WIDTH 1
+#define GMMx2188_BlackoutExempt_MASK 0x8
+#define GMMx2188_StallMode_OFFSET 4
+#define GMMx2188_StallMode_WIDTH 2
+#define GMMx2188_StallMode_MASK 0x30
+#define GMMx2188_StallOverride_OFFSET 6
+#define GMMx2188_StallOverride_WIDTH 1
+#define GMMx2188_StallOverride_MASK 0x40
+#define GMMx2188_MaxBurst_OFFSET 7
+#define GMMx2188_MaxBurst_WIDTH 4
+#define GMMx2188_MaxBurst_MASK 0x780
+#define GMMx2188_LazyTimer_OFFSET 11
+#define GMMx2188_LazyTimer_WIDTH 4
+#define GMMx2188_LazyTimer_MASK 0x7800
+#define GMMx2188_StallOverrideWtm_OFFSET 15
+#define GMMx2188_StallOverrideWtm_WIDTH 1
+#define GMMx2188_StallOverrideWtm_MASK 0x8000
+#define GMMx2188_ReqLimit_OFFSET 16
+#define GMMx2188_ReqLimit_WIDTH 4
+#define GMMx2188_ReqLimit_MASK 0xf0000
+#define GMMx2188_Reserved_31_20_OFFSET 20
+#define GMMx2188_Reserved_31_20_WIDTH 12
+#define GMMx2188_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx2188
typedef union {
struct { ///<
- UINT32 DbstEn0:4 ; ///<
- UINT32 TcvFetch1:4 ; ///<
- UINT32 TctFetch1:4 ; ///<
- UINT32 Vc1:4 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 ReqLimit:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2618_STRUCT;
+} GMMx2188_STRUCT;
+
+// **** GMMx218C Register Definition ****
+// Address
+#define GMMx218C_ADDRESS 0x218c
+
+// Type
+#define GMMx218C_TYPE TYPE_GMM
+// Field Data
+#define GMMx218C_Enable_OFFSET 0
+#define GMMx218C_Enable_WIDTH 1
+#define GMMx218C_Enable_MASK 0x1
+#define GMMx218C_Prescale_OFFSET 1
+#define GMMx218C_Prescale_WIDTH 2
+#define GMMx218C_Prescale_MASK 0x6
+#define GMMx218C_BlackoutExempt_OFFSET 3
+#define GMMx218C_BlackoutExempt_WIDTH 1
+#define GMMx218C_BlackoutExempt_MASK 0x8
+#define GMMx218C_StallMode_OFFSET 4
+#define GMMx218C_StallMode_WIDTH 2
+#define GMMx218C_StallMode_MASK 0x30
+#define GMMx218C_StallOverride_OFFSET 6
+#define GMMx218C_StallOverride_WIDTH 1
+#define GMMx218C_StallOverride_MASK 0x40
+#define GMMx218C_MaxBurst_OFFSET 7
+#define GMMx218C_MaxBurst_WIDTH 4
+#define GMMx218C_MaxBurst_MASK 0x780
+#define GMMx218C_LazyTimer_OFFSET 11
+#define GMMx218C_LazyTimer_WIDTH 4
+#define GMMx218C_LazyTimer_MASK 0x7800
+#define GMMx218C_StallOverrideWtm_OFFSET 15
+#define GMMx218C_StallOverrideWtm_WIDTH 1
+#define GMMx218C_StallOverrideWtm_MASK 0x8000
+#define GMMx218C_Reserved_19_16_OFFSET 16
+#define GMMx218C_Reserved_19_16_WIDTH 4
+#define GMMx218C_Reserved_19_16_MASK 0xf0000
+#define GMMx218C_Reserved_31_20_OFFSET 20
+#define GMMx218C_Reserved_31_20_WIDTH 12
+#define GMMx218C_Reserved_31_20_MASK 0xfff00000
+
+/// GMMx218C
+typedef union {
+ struct { ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_19_16:4 ; ///<
+ UINT32 Reserved_31_20:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx218C_STRUCT;
-// **** GMMx261C Register Definition ****
+// **** GMMx2190 Register Definition ****
// Address
-#define GMMx261C_ADDRESS 0x261c
+#define GMMx2190_ADDRESS 0x2190
// Type
-#define GMMx261C_TYPE TYPE_GMM
+#define GMMx2190_TYPE TYPE_GMM
// Field Data
-#define GMMx261C_DbstEn0_OFFSET 0
-#define GMMx261C_DbstEn0_WIDTH 4
-#define GMMx261C_DbstEn0_MASK 0xf
-#define GMMx261C_Reserved_31_4_OFFSET 4
-#define GMMx261C_Reserved_31_4_WIDTH 28
-#define GMMx261C_Reserved_31_4_MASK 0xfffffff0
+#define GMMx2190_Enable_OFFSET 0
+#define GMMx2190_Enable_WIDTH 1
+#define GMMx2190_Enable_MASK 0x1
+#define GMMx2190_Reserved_1_1_OFFSET 1
+#define GMMx2190_Reserved_1_1_WIDTH 1
+#define GMMx2190_Reserved_1_1_MASK 0x2
+#define GMMx2190_StallMode_OFFSET 2
+#define GMMx2190_StallMode_WIDTH 1
+#define GMMx2190_StallMode_MASK 0x4
+#define GMMx2190_MaxBurst_OFFSET 3
+#define GMMx2190_MaxBurst_WIDTH 4
+#define GMMx2190_MaxBurst_MASK 0x78
+#define GMMx2190_AskCredits_OFFSET 7
+#define GMMx2190_AskCredits_WIDTH 6
+#define GMMx2190_AskCredits_MASK 0x1f80
+#define GMMx2190_LazyTimer_OFFSET 13
+#define GMMx2190_LazyTimer_WIDTH 4
+#define GMMx2190_LazyTimer_MASK 0x1e000
+#define GMMx2190_StallThreshold_OFFSET 17
+#define GMMx2190_StallThreshold_WIDTH 6
+#define GMMx2190_StallThreshold_MASK 0x7e0000
+#define GMMx2190_Reserved_31_23_OFFSET 23
+#define GMMx2190_Reserved_31_23_WIDTH 9
+#define GMMx2190_Reserved_31_23_MASK 0xff800000
-/// GMMx261C
+/// GMMx2190
typedef union {
struct { ///<
- UINT32 DbstEn0:4 ; ///<
- UINT32 Reserved_31_4:28; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Reserved_1_1:1 ; ///<
+ UINT32 StallMode:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 AskCredits:6 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallThreshold:6 ; ///<
+ UINT32 Reserved_31_23:9 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx261C_STRUCT;
+} GMMx2190_STRUCT;
-// **** GMMx2638 Register Definition ****
+// **** GMMx2194 Register Definition ****
// Address
-#define GMMx2638_ADDRESS 0x2638
+#define GMMx2194_ADDRESS 0x2194
// Type
-#define GMMx2638_TYPE TYPE_GMM
+#define GMMx2194_TYPE TYPE_GMM
// Field Data
-#define GMMx2638_Reserved_17_0_OFFSET 0
-#define GMMx2638_Reserved_17_0_WIDTH 18
-#define GMMx2638_Reserved_17_0_MASK 0x3ffff
-#define GMMx2638_Enable_OFFSET 18
-#define GMMx2638_Enable_WIDTH 1
-#define GMMx2638_Enable_MASK 0x40000
-#define GMMx2638_Reserved_31_19_OFFSET 19
-#define GMMx2638_Reserved_31_19_WIDTH 13
-#define GMMx2638_Reserved_31_19_MASK 0xfff80000
+#define GMMx2194_Enable_OFFSET 0
+#define GMMx2194_Enable_WIDTH 1
+#define GMMx2194_Enable_MASK 0x1
+#define GMMx2194_Reserved_1_1_OFFSET 1
+#define GMMx2194_Reserved_1_1_WIDTH 1
+#define GMMx2194_Reserved_1_1_MASK 0x2
+#define GMMx2194_StallMode_OFFSET 2
+#define GMMx2194_StallMode_WIDTH 1
+#define GMMx2194_StallMode_MASK 0x4
+#define GMMx2194_MaxBurst_OFFSET 3
+#define GMMx2194_MaxBurst_WIDTH 4
+#define GMMx2194_MaxBurst_MASK 0x78
+#define GMMx2194_AskCredits_OFFSET 7
+#define GMMx2194_AskCredits_WIDTH 6
+#define GMMx2194_AskCredits_MASK 0x1f80
+#define GMMx2194_LazyTimer_OFFSET 13
+#define GMMx2194_LazyTimer_WIDTH 4
+#define GMMx2194_LazyTimer_MASK 0x1e000
+#define GMMx2194_StallThreshold_OFFSET 17
+#define GMMx2194_StallThreshold_WIDTH 6
+#define GMMx2194_StallThreshold_MASK 0x7e0000
+#define GMMx2194_Reserved_31_23_OFFSET 23
+#define GMMx2194_Reserved_31_23_WIDTH 9
+#define GMMx2194_Reserved_31_23_MASK 0xff800000
+
+/// GMMx2194
+typedef union {
+ struct { ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Reserved_1_1:1 ; ///<
+ UINT32 StallMode:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 AskCredits:6 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallThreshold:6 ; ///<
+ UINT32 Reserved_31_23:9 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx2194_STRUCT;
-/// GMMx2638
+// **** GMMx2198 Register Definition ****
+// Address
+#define GMMx2198_ADDRESS 0x2198
+
+// Type
+#define GMMx2198_TYPE TYPE_GMM
+// Field Data
+#define GMMx2198_Enable_OFFSET 0
+#define GMMx2198_Enable_WIDTH 1
+#define GMMx2198_Enable_MASK 0x1
+#define GMMx2198_Reserved_1_1_OFFSET 1
+#define GMMx2198_Reserved_1_1_WIDTH 1
+#define GMMx2198_Reserved_1_1_MASK 0x2
+#define GMMx2198_StallMode_OFFSET 2
+#define GMMx2198_StallMode_WIDTH 1
+#define GMMx2198_StallMode_MASK 0x4
+#define GMMx2198_MaxBurst_OFFSET 3
+#define GMMx2198_MaxBurst_WIDTH 4
+#define GMMx2198_MaxBurst_MASK 0x78
+#define GMMx2198_AskCredits_OFFSET 7
+#define GMMx2198_AskCredits_WIDTH 6
+#define GMMx2198_AskCredits_MASK 0x1f80
+#define GMMx2198_LazyTimer_OFFSET 13
+#define GMMx2198_LazyTimer_WIDTH 4
+#define GMMx2198_LazyTimer_MASK 0x1e000
+#define GMMx2198_StallThreshold_OFFSET 17
+#define GMMx2198_StallThreshold_WIDTH 6
+#define GMMx2198_StallThreshold_MASK 0x7e0000
+#define GMMx2198_Reserved_31_23_OFFSET 23
+#define GMMx2198_Reserved_31_23_WIDTH 9
+#define GMMx2198_Reserved_31_23_MASK 0xff800000
+
+/// GMMx2198
typedef union {
struct { ///<
- UINT32 Reserved_17_0:18; ///<
UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
+ UINT32 Reserved_1_1:1 ; ///<
+ UINT32 StallMode:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 AskCredits:6 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallThreshold:6 ; ///<
+ UINT32 Reserved_31_23:9 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2638_STRUCT;
+} GMMx2198_STRUCT;
-// **** GMMx263C Register Definition ****
+// **** GMMx219C Register Definition ****
// Address
-#define GMMx263C_ADDRESS 0x263c
+#define GMMx219C_ADDRESS 0x219c
// Type
-#define GMMx263C_TYPE TYPE_GMM
+#define GMMx219C_TYPE TYPE_GMM
// Field Data
-#define GMMx263C_Reserved_17_0_OFFSET 0
-#define GMMx263C_Reserved_17_0_WIDTH 18
-#define GMMx263C_Reserved_17_0_MASK 0x3ffff
-#define GMMx263C_Enable_OFFSET 18
-#define GMMx263C_Enable_WIDTH 1
-#define GMMx263C_Enable_MASK 0x40000
-#define GMMx263C_Reserved_31_19_OFFSET 19
-#define GMMx263C_Reserved_31_19_WIDTH 13
-#define GMMx263C_Reserved_31_19_MASK 0xfff80000
+#define GMMx219C_Enable_OFFSET 0
+#define GMMx219C_Enable_WIDTH 1
+#define GMMx219C_Enable_MASK 0x1
+#define GMMx219C_Reserved_1_1_OFFSET 1
+#define GMMx219C_Reserved_1_1_WIDTH 1
+#define GMMx219C_Reserved_1_1_MASK 0x2
+#define GMMx219C_StallMode_OFFSET 2
+#define GMMx219C_StallMode_WIDTH 1
+#define GMMx219C_StallMode_MASK 0x4
+#define GMMx219C_MaxBurst_OFFSET 3
+#define GMMx219C_MaxBurst_WIDTH 4
+#define GMMx219C_MaxBurst_MASK 0x78
+#define GMMx219C_AskCredits_OFFSET 7
+#define GMMx219C_AskCredits_WIDTH 6
+#define GMMx219C_AskCredits_MASK 0x1f80
+#define GMMx219C_LazyTimer_OFFSET 13
+#define GMMx219C_LazyTimer_WIDTH 4
+#define GMMx219C_LazyTimer_MASK 0x1e000
+#define GMMx219C_StallThreshold_OFFSET 17
+#define GMMx219C_StallThreshold_WIDTH 6
+#define GMMx219C_StallThreshold_MASK 0x7e0000
+#define GMMx219C_Reserved_31_23_OFFSET 23
+#define GMMx219C_Reserved_31_23_WIDTH 9
+#define GMMx219C_Reserved_31_23_MASK 0xff800000
-/// GMMx263C
+/// GMMx219C
typedef union {
struct { ///<
- UINT32 Reserved_17_0:18; ///<
UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
+ UINT32 Reserved_1_1:1 ; ///<
+ UINT32 StallMode:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 AskCredits:6 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallThreshold:6 ; ///<
+ UINT32 Reserved_31_23:9 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx263C_STRUCT;
+} GMMx219C_STRUCT;
-// **** GMMx2640 Register Definition ****
+// **** GMMx21A4 Register Definition ****
// Address
-#define GMMx2640_ADDRESS 0x2640
+#define GMMx21A4_ADDRESS 0x21a4
// Type
-#define GMMx2640_TYPE TYPE_GMM
+#define GMMx21A4_TYPE TYPE_GMM
// Field Data
-#define GMMx2640_Reserved_17_0_OFFSET 0
-#define GMMx2640_Reserved_17_0_WIDTH 18
-#define GMMx2640_Reserved_17_0_MASK 0x3ffff
-#define GMMx2640_Enable_OFFSET 18
-#define GMMx2640_Enable_WIDTH 1
-#define GMMx2640_Enable_MASK 0x40000
-#define GMMx2640_Reserved_31_19_OFFSET 19
-#define GMMx2640_Reserved_31_19_WIDTH 13
-#define GMMx2640_Reserved_31_19_MASK 0xfff80000
+#define GMMx21A4_Enable_OFFSET 0
+#define GMMx21A4_Enable_WIDTH 1
+#define GMMx21A4_Enable_MASK 0x1
+#define GMMx21A4_Prescale_OFFSET 1
+#define GMMx21A4_Prescale_WIDTH 2
+#define GMMx21A4_Prescale_MASK 0x6
+#define GMMx21A4_BlackoutExempt_OFFSET 3
+#define GMMx21A4_BlackoutExempt_WIDTH 1
+#define GMMx21A4_BlackoutExempt_MASK 0x8
+#define GMMx21A4_StallMode_OFFSET 4
+#define GMMx21A4_StallMode_WIDTH 2
+#define GMMx21A4_StallMode_MASK 0x30
+#define GMMx21A4_StallOverride_OFFSET 6
+#define GMMx21A4_StallOverride_WIDTH 1
+#define GMMx21A4_StallOverride_MASK 0x40
+#define GMMx21A4_MaxBurst_OFFSET 7
+#define GMMx21A4_MaxBurst_WIDTH 4
+#define GMMx21A4_MaxBurst_MASK 0x780
+#define GMMx21A4_LazyTimer_OFFSET 11
+#define GMMx21A4_LazyTimer_WIDTH 4
+#define GMMx21A4_LazyTimer_MASK 0x7800
+#define GMMx21A4_StallOverrideWtm_OFFSET 15
+#define GMMx21A4_StallOverrideWtm_WIDTH 1
+#define GMMx21A4_StallOverrideWtm_MASK 0x8000
+#define GMMx21A4_Reserved_31_16_OFFSET 16
+#define GMMx21A4_Reserved_31_16_WIDTH 16
+#define GMMx21A4_Reserved_31_16_MASK 0xffff0000
-/// GMMx2640
+/// GMMx21A4
typedef union {
struct { ///<
- UINT32 Reserved_17_0:18; ///<
UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2640_STRUCT;
+} GMMx21A4_STRUCT;
-// **** GMMx277C Register Definition ****
+// **** GMMx21A8 Register Definition ****
// Address
-#define GMMx277C_ADDRESS 0x277c
+#define GMMx21A8_ADDRESS 0x21a8
// Type
-#define GMMx277C_TYPE TYPE_GMM
+#define GMMx21A8_TYPE TYPE_GMM
// Field Data
-#define GMMx277C_ActRd_OFFSET 0
-#define GMMx277C_ActRd_WIDTH 8
-#define GMMx277C_ActRd_MASK 0xff
-#define GMMx277C_ActWr_OFFSET 8
-#define GMMx277C_ActWr_WIDTH 8
-#define GMMx277C_ActWr_MASK 0xff00
-#define GMMx277C_RasMActRd_OFFSET 16
-#define GMMx277C_RasMActRd_WIDTH 8
-#define GMMx277C_RasMActRd_MASK 0xff0000
-#define GMMx277C_RasMActWr_OFFSET 24
-#define GMMx277C_RasMActWr_WIDTH 8
-#define GMMx277C_RasMActWr_MASK 0xff000000
+#define GMMx21A8_Enable_OFFSET 0
+#define GMMx21A8_Enable_WIDTH 1
+#define GMMx21A8_Enable_MASK 0x1
+#define GMMx21A8_Prescale_OFFSET 1
+#define GMMx21A8_Prescale_WIDTH 2
+#define GMMx21A8_Prescale_MASK 0x6
+#define GMMx21A8_BlackoutExempt_OFFSET 3
+#define GMMx21A8_BlackoutExempt_WIDTH 1
+#define GMMx21A8_BlackoutExempt_MASK 0x8
+#define GMMx21A8_StallMode_OFFSET 4
+#define GMMx21A8_StallMode_WIDTH 2
+#define GMMx21A8_StallMode_MASK 0x30
+#define GMMx21A8_StallOverride_OFFSET 6
+#define GMMx21A8_StallOverride_WIDTH 1
+#define GMMx21A8_StallOverride_MASK 0x40
+#define GMMx21A8_MaxBurst_OFFSET 7
+#define GMMx21A8_MaxBurst_WIDTH 4
+#define GMMx21A8_MaxBurst_MASK 0x780
+#define GMMx21A8_LazyTimer_OFFSET 11
+#define GMMx21A8_LazyTimer_WIDTH 4
+#define GMMx21A8_LazyTimer_MASK 0x7800
+#define GMMx21A8_StallOverrideWtm_OFFSET 15
+#define GMMx21A8_StallOverrideWtm_WIDTH 1
+#define GMMx21A8_StallOverrideWtm_MASK 0x8000
+#define GMMx21A8_Reserved_31_16_OFFSET 16
+#define GMMx21A8_Reserved_31_16_WIDTH 16
+#define GMMx21A8_Reserved_31_16_MASK 0xffff0000
-/// GMMx277C
+/// GMMx21A8
typedef union {
struct { ///<
- UINT32 ActRd:8 ; ///<
- UINT32 ActWr:8 ; ///<
- UINT32 RasMActRd:8 ; ///<
- UINT32 RasMActWr:8 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx277C_STRUCT;
+} GMMx21A8_STRUCT;
-// **** GMMx2780 Register Definition ****
+// **** GMMx21AC Register Definition ****
// Address
-#define GMMx2780_ADDRESS 0x2780
+#define GMMx21AC_ADDRESS 0x21ac
// Type
-#define GMMx2780_TYPE TYPE_GMM
+#define GMMx21AC_TYPE TYPE_GMM
// Field Data
-#define GMMx2780_Ras2Ras_OFFSET 0
-#define GMMx2780_Ras2Ras_WIDTH 8
-#define GMMx2780_Ras2Ras_MASK 0xff
-#define GMMx2780_Rp_OFFSET 8
-#define GMMx2780_Rp_WIDTH 8
-#define GMMx2780_Rp_MASK 0xff00
-#define GMMx2780_WrPlusRp_OFFSET 16
-#define GMMx2780_WrPlusRp_WIDTH 8
-#define GMMx2780_WrPlusRp_MASK 0xff0000
-#define GMMx2780_BusTurn_OFFSET 24
-#define GMMx2780_BusTurn_WIDTH 8
-#define GMMx2780_BusTurn_MASK 0xff000000
+#define GMMx21AC_Enable_OFFSET 0
+#define GMMx21AC_Enable_WIDTH 1
+#define GMMx21AC_Enable_MASK 0x1
+#define GMMx21AC_Prescale_OFFSET 1
+#define GMMx21AC_Prescale_WIDTH 2
+#define GMMx21AC_Prescale_MASK 0x6
+#define GMMx21AC_BlackoutExempt_OFFSET 3
+#define GMMx21AC_BlackoutExempt_WIDTH 1
+#define GMMx21AC_BlackoutExempt_MASK 0x8
+#define GMMx21AC_StallMode_OFFSET 4
+#define GMMx21AC_StallMode_WIDTH 2
+#define GMMx21AC_StallMode_MASK 0x30
+#define GMMx21AC_StallOverride_OFFSET 6
+#define GMMx21AC_StallOverride_WIDTH 1
+#define GMMx21AC_StallOverride_MASK 0x40
+#define GMMx21AC_MaxBurst_OFFSET 7
+#define GMMx21AC_MaxBurst_WIDTH 4
+#define GMMx21AC_MaxBurst_MASK 0x780
+#define GMMx21AC_LazyTimer_OFFSET 11
+#define GMMx21AC_LazyTimer_WIDTH 4
+#define GMMx21AC_LazyTimer_MASK 0x7800
+#define GMMx21AC_StallOverrideWtm_OFFSET 15
+#define GMMx21AC_StallOverrideWtm_WIDTH 1
+#define GMMx21AC_StallOverrideWtm_MASK 0x8000
+#define GMMx21AC_Reserved_31_16_OFFSET 16
+#define GMMx21AC_Reserved_31_16_WIDTH 16
+#define GMMx21AC_Reserved_31_16_MASK 0xffff0000
-/// GMMx2780
+/// GMMx21AC
typedef union {
struct { ///<
- UINT32 Ras2Ras:8 ; ///<
- UINT32 Rp:8 ; ///<
- UINT32 WrPlusRp:8 ; ///<
- UINT32 BusTurn:8 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2780_STRUCT;
+} GMMx21AC_STRUCT;
-// **** GMMx2784 Register Definition ****
+// **** GMMx21B0 Register Definition ****
// Address
-#define GMMx2784_ADDRESS 0x2784
+#define GMMx21B0_ADDRESS 0x21b0
// Type
-#define GMMx2784_TYPE TYPE_GMM
+#define GMMx21B0_TYPE TYPE_GMM
// Field Data
-#define GMMx2784_WtMode_OFFSET 0
-#define GMMx2784_WtMode_WIDTH 2
-#define GMMx2784_WtMode_MASK 0x3
-#define GMMx2784_HarshPri_OFFSET 2
-#define GMMx2784_HarshPri_WIDTH 1
-#define GMMx2784_HarshPri_MASK 0x4
-#define GMMx2784_Reserved_31_3_OFFSET 3
-#define GMMx2784_Reserved_31_3_WIDTH 29
-#define GMMx2784_Reserved_31_3_MASK 0xfffffff8
+#define GMMx21B0_Enable_OFFSET 0
+#define GMMx21B0_Enable_WIDTH 1
+#define GMMx21B0_Enable_MASK 0x1
+#define GMMx21B0_Prescale_OFFSET 1
+#define GMMx21B0_Prescale_WIDTH 2
+#define GMMx21B0_Prescale_MASK 0x6
+#define GMMx21B0_BlackoutExempt_OFFSET 3
+#define GMMx21B0_BlackoutExempt_WIDTH 1
+#define GMMx21B0_BlackoutExempt_MASK 0x8
+#define GMMx21B0_StallMode_OFFSET 4
+#define GMMx21B0_StallMode_WIDTH 2
+#define GMMx21B0_StallMode_MASK 0x30
+#define GMMx21B0_StallOverride_OFFSET 6
+#define GMMx21B0_StallOverride_WIDTH 1
+#define GMMx21B0_StallOverride_MASK 0x40
+#define GMMx21B0_MaxBurst_OFFSET 7
+#define GMMx21B0_MaxBurst_WIDTH 4
+#define GMMx21B0_MaxBurst_MASK 0x780
+#define GMMx21B0_LazyTimer_OFFSET 11
+#define GMMx21B0_LazyTimer_WIDTH 4
+#define GMMx21B0_LazyTimer_MASK 0x7800
+#define GMMx21B0_StallOverrideWtm_OFFSET 15
+#define GMMx21B0_StallOverrideWtm_WIDTH 1
+#define GMMx21B0_StallOverrideWtm_MASK 0x8000
+#define GMMx21B0_Reserved_31_16_OFFSET 16
+#define GMMx21B0_Reserved_31_16_WIDTH 16
+#define GMMx21B0_Reserved_31_16_MASK 0xffff0000
-/// GMMx2784
+/// GMMx21B0
typedef union {
struct { ///<
- UINT32 WtMode:2 ; ///<
- UINT32 HarshPri:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2784_STRUCT;
+} GMMx21B0_STRUCT;
-// **** GMMx2788 Register Definition ****
+// **** GMMx21B4 Register Definition ****
// Address
-#define GMMx2788_ADDRESS 0x2788
+#define GMMx21B4_ADDRESS 0x21b4
// Type
-#define GMMx2788_TYPE TYPE_GMM
+#define GMMx21B4_TYPE TYPE_GMM
// Field Data
-#define GMMx2788_WtMode_OFFSET 0
-#define GMMx2788_WtMode_WIDTH 2
-#define GMMx2788_WtMode_MASK 0x3
-#define GMMx2788_HarshPri_OFFSET 2
-#define GMMx2788_HarshPri_WIDTH 1
-#define GMMx2788_HarshPri_MASK 0x4
-#define GMMx2788_Reserved_31_3_OFFSET 3
-#define GMMx2788_Reserved_31_3_WIDTH 29
-#define GMMx2788_Reserved_31_3_MASK 0xfffffff8
+#define GMMx21B4_Enable_OFFSET 0
+#define GMMx21B4_Enable_WIDTH 1
+#define GMMx21B4_Enable_MASK 0x1
+#define GMMx21B4_Prescale_OFFSET 1
+#define GMMx21B4_Prescale_WIDTH 2
+#define GMMx21B4_Prescale_MASK 0x6
+#define GMMx21B4_BlackoutExempt_OFFSET 3
+#define GMMx21B4_BlackoutExempt_WIDTH 1
+#define GMMx21B4_BlackoutExempt_MASK 0x8
+#define GMMx21B4_StallMode_OFFSET 4
+#define GMMx21B4_StallMode_WIDTH 2
+#define GMMx21B4_StallMode_MASK 0x30
+#define GMMx21B4_StallOverride_OFFSET 6
+#define GMMx21B4_StallOverride_WIDTH 1
+#define GMMx21B4_StallOverride_MASK 0x40
+#define GMMx21B4_MaxBurst_OFFSET 7
+#define GMMx21B4_MaxBurst_WIDTH 4
+#define GMMx21B4_MaxBurst_MASK 0x780
+#define GMMx21B4_LazyTimer_OFFSET 11
+#define GMMx21B4_LazyTimer_WIDTH 4
+#define GMMx21B4_LazyTimer_MASK 0x7800
+#define GMMx21B4_StallOverrideWtm_OFFSET 15
+#define GMMx21B4_StallOverrideWtm_WIDTH 1
+#define GMMx21B4_StallOverrideWtm_MASK 0x8000
+#define GMMx21B4_Reserved_31_16_OFFSET 16
+#define GMMx21B4_Reserved_31_16_WIDTH 16
+#define GMMx21B4_Reserved_31_16_MASK 0xffff0000
-/// GMMx2788
+/// GMMx21B4
typedef union {
struct { ///<
- UINT32 WtMode:2 ; ///<
- UINT32 HarshPri:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2788_STRUCT;
+} GMMx21B4_STRUCT;
-// **** GMMx279C Register Definition ****
+// **** GMMx21B8 Register Definition ****
// Address
-#define GMMx279C_ADDRESS 0x279c
+#define GMMx21B8_ADDRESS 0x21b8
// Type
-#define GMMx279C_TYPE TYPE_GMM
+#define GMMx21B8_TYPE TYPE_GMM
// Field Data
-#define GMMx279C_Group0_OFFSET 0
-#define GMMx279C_Group0_WIDTH 8
-#define GMMx279C_Group0_MASK 0xff
-#define GMMx279C_Group1_OFFSET 8
-#define GMMx279C_Group1_WIDTH 8
-#define GMMx279C_Group1_MASK 0xff00
-#define GMMx279C_Group2_OFFSET 16
-#define GMMx279C_Group2_WIDTH 8
-#define GMMx279C_Group2_MASK 0xff0000
-#define GMMx279C_Group3_OFFSET 24
-#define GMMx279C_Group3_WIDTH 8
-#define GMMx279C_Group3_MASK 0xff000000
+#define GMMx21B8_Enable_OFFSET 0
+#define GMMx21B8_Enable_WIDTH 1
+#define GMMx21B8_Enable_MASK 0x1
+#define GMMx21B8_Prescale_OFFSET 1
+#define GMMx21B8_Prescale_WIDTH 2
+#define GMMx21B8_Prescale_MASK 0x6
+#define GMMx21B8_BlackoutExempt_OFFSET 3
+#define GMMx21B8_BlackoutExempt_WIDTH 1
+#define GMMx21B8_BlackoutExempt_MASK 0x8
+#define GMMx21B8_StallMode_OFFSET 4
+#define GMMx21B8_StallMode_WIDTH 2
+#define GMMx21B8_StallMode_MASK 0x30
+#define GMMx21B8_StallOverride_OFFSET 6
+#define GMMx21B8_StallOverride_WIDTH 1
+#define GMMx21B8_StallOverride_MASK 0x40
+#define GMMx21B8_MaxBurst_OFFSET 7
+#define GMMx21B8_MaxBurst_WIDTH 4
+#define GMMx21B8_MaxBurst_MASK 0x780
+#define GMMx21B8_LazyTimer_OFFSET 11
+#define GMMx21B8_LazyTimer_WIDTH 4
+#define GMMx21B8_LazyTimer_MASK 0x7800
+#define GMMx21B8_StallOverrideWtm_OFFSET 15
+#define GMMx21B8_StallOverrideWtm_WIDTH 1
+#define GMMx21B8_StallOverrideWtm_MASK 0x8000
+#define GMMx21B8_Reserved_31_16_OFFSET 16
+#define GMMx21B8_Reserved_31_16_WIDTH 16
+#define GMMx21B8_Reserved_31_16_MASK 0xffff0000
-/// GMMx279C
+/// GMMx21B8
typedef union {
struct { ///<
- UINT32 Group0:8 ; ///<
- UINT32 Group1:8 ; ///<
- UINT32 Group2:8 ; ///<
- UINT32 Group3:8 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx279C_STRUCT;
+} GMMx21B8_STRUCT;
-// **** GMMx27A0 Register Definition ****
+// **** GMMx21BC Register Definition ****
// Address
-#define GMMx27A0_ADDRESS 0x27a0
+#define GMMx21BC_ADDRESS 0x21bc
// Type
-#define GMMx27A0_TYPE TYPE_GMM
+#define GMMx21BC_TYPE TYPE_GMM
// Field Data
-#define GMMx27A0_Group0_OFFSET 0
-#define GMMx27A0_Group0_WIDTH 8
-#define GMMx27A0_Group0_MASK 0xff
-#define GMMx27A0_Group1_OFFSET 8
-#define GMMx27A0_Group1_WIDTH 8
-#define GMMx27A0_Group1_MASK 0xff00
-#define GMMx27A0_Group2_OFFSET 16
-#define GMMx27A0_Group2_WIDTH 8
-#define GMMx27A0_Group2_MASK 0xff0000
-#define GMMx27A0_Group3_OFFSET 24
-#define GMMx27A0_Group3_WIDTH 8
-#define GMMx27A0_Group3_MASK 0xff000000
+#define GMMx21BC_Enable_OFFSET 0
+#define GMMx21BC_Enable_WIDTH 1
+#define GMMx21BC_Enable_MASK 0x1
+#define GMMx21BC_Prescale_OFFSET 1
+#define GMMx21BC_Prescale_WIDTH 2
+#define GMMx21BC_Prescale_MASK 0x6
+#define GMMx21BC_BlackoutExempt_OFFSET 3
+#define GMMx21BC_BlackoutExempt_WIDTH 1
+#define GMMx21BC_BlackoutExempt_MASK 0x8
+#define GMMx21BC_StallMode_OFFSET 4
+#define GMMx21BC_StallMode_WIDTH 2
+#define GMMx21BC_StallMode_MASK 0x30
+#define GMMx21BC_StallOverride_OFFSET 6
+#define GMMx21BC_StallOverride_WIDTH 1
+#define GMMx21BC_StallOverride_MASK 0x40
+#define GMMx21BC_MaxBurst_OFFSET 7
+#define GMMx21BC_MaxBurst_WIDTH 4
+#define GMMx21BC_MaxBurst_MASK 0x780
+#define GMMx21BC_LazyTimer_OFFSET 11
+#define GMMx21BC_LazyTimer_WIDTH 4
+#define GMMx21BC_LazyTimer_MASK 0x7800
+#define GMMx21BC_StallOverrideWtm_OFFSET 15
+#define GMMx21BC_StallOverrideWtm_WIDTH 1
+#define GMMx21BC_StallOverrideWtm_MASK 0x8000
+#define GMMx21BC_Reserved_31_16_OFFSET 16
+#define GMMx21BC_Reserved_31_16_WIDTH 16
+#define GMMx21BC_Reserved_31_16_MASK 0xffff0000
-/// GMMx27A0
+/// GMMx21BC
typedef union {
struct { ///<
- UINT32 Group0:8 ; ///<
- UINT32 Group1:8 ; ///<
- UINT32 Group2:8 ; ///<
- UINT32 Group3:8 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx27A0_STRUCT;
+} GMMx21BC_STRUCT;
-// **** GMMx27CC Register Definition ****
+// **** GMMx21C0 Register Definition ****
// Address
-#define GMMx27CC_ADDRESS 0x27cc
+#define GMMx21C0_ADDRESS 0x21c0
// Type
-#define GMMx27CC_TYPE TYPE_GMM
+#define GMMx21C0_TYPE TYPE_GMM
// Field Data
-#define GMMx27CC_StreakLimit_OFFSET 0
-#define GMMx27CC_StreakLimit_WIDTH 8
-#define GMMx27CC_StreakLimit_MASK 0xff
-#define GMMx27CC_StreakLimitUber_OFFSET 8
-#define GMMx27CC_StreakLimitUber_WIDTH 8
-#define GMMx27CC_StreakLimitUber_MASK 0xff00
-#define GMMx27CC_StreakBreak_OFFSET 16
-#define GMMx27CC_StreakBreak_WIDTH 1
-#define GMMx27CC_StreakBreak_MASK 0x10000
-#define GMMx27CC_StreakUber_OFFSET 17
-#define GMMx27CC_StreakUber_WIDTH 1
-#define GMMx27CC_StreakUber_MASK 0x20000
-#define GMMx27CC_Reserved_31_18_OFFSET 18
-#define GMMx27CC_Reserved_31_18_WIDTH 14
-#define GMMx27CC_Reserved_31_18_MASK 0xfffc0000
+#define GMMx21C0_Enable_OFFSET 0
+#define GMMx21C0_Enable_WIDTH 1
+#define GMMx21C0_Enable_MASK 0x1
+#define GMMx21C0_Prescale_OFFSET 1
+#define GMMx21C0_Prescale_WIDTH 2
+#define GMMx21C0_Prescale_MASK 0x6
+#define GMMx21C0_BlackoutExempt_OFFSET 3
+#define GMMx21C0_BlackoutExempt_WIDTH 1
+#define GMMx21C0_BlackoutExempt_MASK 0x8
+#define GMMx21C0_StallMode_OFFSET 4
+#define GMMx21C0_StallMode_WIDTH 2
+#define GMMx21C0_StallMode_MASK 0x30
+#define GMMx21C0_StallOverride_OFFSET 6
+#define GMMx21C0_StallOverride_WIDTH 1
+#define GMMx21C0_StallOverride_MASK 0x40
+#define GMMx21C0_MaxBurst_OFFSET 7
+#define GMMx21C0_MaxBurst_WIDTH 4
+#define GMMx21C0_MaxBurst_MASK 0x780
+#define GMMx21C0_LazyTimer_OFFSET 11
+#define GMMx21C0_LazyTimer_WIDTH 4
+#define GMMx21C0_LazyTimer_MASK 0x7800
+#define GMMx21C0_StallOverrideWtm_OFFSET 15
+#define GMMx21C0_StallOverrideWtm_WIDTH 1
+#define GMMx21C0_StallOverrideWtm_MASK 0x8000
+#define GMMx21C0_Reserved_31_16_OFFSET 16
+#define GMMx21C0_Reserved_31_16_WIDTH 16
+#define GMMx21C0_Reserved_31_16_MASK 0xffff0000
-/// GMMx27CC
-typedef union {
- struct { ///<
- UINT32 StreakLimit:8 ; ///<
- UINT32 StreakLimitUber:8 ; ///<
- UINT32 StreakBreak:1 ; ///<
- UINT32 StreakUber:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
+/// GMMx21C0
+typedef union {
+ struct { ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx27CC_STRUCT;
+} GMMx21C0_STRUCT;
-// **** GMMx27D0 Register Definition ****
+// **** GMMx21C4 Register Definition ****
// Address
-#define GMMx27D0_ADDRESS 0x27d0
+#define GMMx21C4_ADDRESS 0x21c4
// Type
-#define GMMx27D0_TYPE TYPE_GMM
+#define GMMx21C4_TYPE TYPE_GMM
// Field Data
-#define GMMx27D0_StreakLimit_OFFSET 0
-#define GMMx27D0_StreakLimit_WIDTH 8
-#define GMMx27D0_StreakLimit_MASK 0xff
-#define GMMx27D0_StreakLimitUber_OFFSET 8
-#define GMMx27D0_StreakLimitUber_WIDTH 8
-#define GMMx27D0_StreakLimitUber_MASK 0xff00
-#define GMMx27D0_StreakBreak_OFFSET 16
-#define GMMx27D0_StreakBreak_WIDTH 1
-#define GMMx27D0_StreakBreak_MASK 0x10000
-#define GMMx27D0_StreakUber_OFFSET 17
-#define GMMx27D0_StreakUber_WIDTH 1
-#define GMMx27D0_StreakUber_MASK 0x20000
-#define GMMx27D0_Reserved_31_18_OFFSET 18
-#define GMMx27D0_Reserved_31_18_WIDTH 14
-#define GMMx27D0_Reserved_31_18_MASK 0xfffc0000
+#define GMMx21C4_Enable_OFFSET 0
+#define GMMx21C4_Enable_WIDTH 1
+#define GMMx21C4_Enable_MASK 0x1
+#define GMMx21C4_Prescale_OFFSET 1
+#define GMMx21C4_Prescale_WIDTH 2
+#define GMMx21C4_Prescale_MASK 0x6
+#define GMMx21C4_BlackoutExempt_OFFSET 3
+#define GMMx21C4_BlackoutExempt_WIDTH 1
+#define GMMx21C4_BlackoutExempt_MASK 0x8
+#define GMMx21C4_StallMode_OFFSET 4
+#define GMMx21C4_StallMode_WIDTH 2
+#define GMMx21C4_StallMode_MASK 0x30
+#define GMMx21C4_StallOverride_OFFSET 6
+#define GMMx21C4_StallOverride_WIDTH 1
+#define GMMx21C4_StallOverride_MASK 0x40
+#define GMMx21C4_MaxBurst_OFFSET 7
+#define GMMx21C4_MaxBurst_WIDTH 4
+#define GMMx21C4_MaxBurst_MASK 0x780
+#define GMMx21C4_LazyTimer_OFFSET 11
+#define GMMx21C4_LazyTimer_WIDTH 4
+#define GMMx21C4_LazyTimer_MASK 0x7800
+#define GMMx21C4_StallOverrideWtm_OFFSET 15
+#define GMMx21C4_StallOverrideWtm_WIDTH 1
+#define GMMx21C4_StallOverrideWtm_MASK 0x8000
+#define GMMx21C4_Reserved_31_16_OFFSET 16
+#define GMMx21C4_Reserved_31_16_WIDTH 16
+#define GMMx21C4_Reserved_31_16_MASK 0xffff0000
-/// GMMx27D0
+/// GMMx21C4
typedef union {
struct { ///<
- UINT32 StreakLimit:8 ; ///<
- UINT32 StreakLimitUber:8 ; ///<
- UINT32 StreakBreak:1 ; ///<
- UINT32 StreakUber:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx27D0_STRUCT;
+} GMMx21C4_STRUCT;
-// **** GMMx27DC Register Definition ****
+// **** GMMx21C8 Register Definition ****
// Address
-#define GMMx27DC_ADDRESS 0x27dc
+#define GMMx21C8_ADDRESS 0x21c8
// Type
-#define GMMx27DC_TYPE TYPE_GMM
+#define GMMx21C8_TYPE TYPE_GMM
// Field Data
-#define GMMx27DC_Lcl_OFFSET 0
-#define GMMx27DC_Lcl_WIDTH 8
-#define GMMx27DC_Lcl_MASK 0xff
-#define GMMx27DC_Hub_OFFSET 8
-#define GMMx27DC_Hub_WIDTH 8
-#define GMMx27DC_Hub_MASK 0xff00
-#define GMMx27DC_Disp_OFFSET 16
-#define GMMx27DC_Disp_WIDTH 8
-#define GMMx27DC_Disp_MASK 0xff0000
-#define GMMx27DC_Reserved_31_24_OFFSET 24
-#define GMMx27DC_Reserved_31_24_WIDTH 8
-#define GMMx27DC_Reserved_31_24_MASK 0xff000000
+#define GMMx21C8_Enable_OFFSET 0
+#define GMMx21C8_Enable_WIDTH 1
+#define GMMx21C8_Enable_MASK 0x1
+#define GMMx21C8_Prescale_OFFSET 1
+#define GMMx21C8_Prescale_WIDTH 2
+#define GMMx21C8_Prescale_MASK 0x6
+#define GMMx21C8_BlackoutExempt_OFFSET 3
+#define GMMx21C8_BlackoutExempt_WIDTH 1
+#define GMMx21C8_BlackoutExempt_MASK 0x8
+#define GMMx21C8_StallMode_OFFSET 4
+#define GMMx21C8_StallMode_WIDTH 2
+#define GMMx21C8_StallMode_MASK 0x30
+#define GMMx21C8_StallOverride_OFFSET 6
+#define GMMx21C8_StallOverride_WIDTH 1
+#define GMMx21C8_StallOverride_MASK 0x40
+#define GMMx21C8_MaxBurst_OFFSET 7
+#define GMMx21C8_MaxBurst_WIDTH 4
+#define GMMx21C8_MaxBurst_MASK 0x780
+#define GMMx21C8_LazyTimer_OFFSET 11
+#define GMMx21C8_LazyTimer_WIDTH 4
+#define GMMx21C8_LazyTimer_MASK 0x7800
+#define GMMx21C8_StallOverrideWtm_OFFSET 15
+#define GMMx21C8_StallOverrideWtm_WIDTH 1
+#define GMMx21C8_StallOverrideWtm_MASK 0x8000
+#define GMMx21C8_Reserved_31_16_OFFSET 16
+#define GMMx21C8_Reserved_31_16_WIDTH 16
+#define GMMx21C8_Reserved_31_16_MASK 0xffff0000
-/// GMMx27DC
+/// GMMx21C8
typedef union {
struct { ///<
- UINT32 Lcl:8 ; ///<
- UINT32 Hub:8 ; ///<
- UINT32 Disp:8 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx27DC_STRUCT;
+} GMMx21C8_STRUCT;
-// **** GMMx27E0 Register Definition ****
+// **** GMMx21CC Register Definition ****
// Address
-#define GMMx27E0_ADDRESS 0x27e0
+#define GMMx21CC_ADDRESS 0x21cc
// Type
-#define GMMx27E0_TYPE TYPE_GMM
+#define GMMx21CC_TYPE TYPE_GMM
// Field Data
-#define GMMx27E0_Lcl_OFFSET 0
-#define GMMx27E0_Lcl_WIDTH 8
-#define GMMx27E0_Lcl_MASK 0xff
-#define GMMx27E0_Hub_OFFSET 8
-#define GMMx27E0_Hub_WIDTH 8
-#define GMMx27E0_Hub_MASK 0xff00
-#define GMMx27E0_Reserved_31_16_OFFSET 16
-#define GMMx27E0_Reserved_31_16_WIDTH 16
-#define GMMx27E0_Reserved_31_16_MASK 0xffff0000
+#define GMMx21CC_Enable_OFFSET 0
+#define GMMx21CC_Enable_WIDTH 1
+#define GMMx21CC_Enable_MASK 0x1
+#define GMMx21CC_Prescale_OFFSET 1
+#define GMMx21CC_Prescale_WIDTH 2
+#define GMMx21CC_Prescale_MASK 0x6
+#define GMMx21CC_BlackoutExempt_OFFSET 3
+#define GMMx21CC_BlackoutExempt_WIDTH 1
+#define GMMx21CC_BlackoutExempt_MASK 0x8
+#define GMMx21CC_StallMode_OFFSET 4
+#define GMMx21CC_StallMode_WIDTH 2
+#define GMMx21CC_StallMode_MASK 0x30
+#define GMMx21CC_StallOverride_OFFSET 6
+#define GMMx21CC_StallOverride_WIDTH 1
+#define GMMx21CC_StallOverride_MASK 0x40
+#define GMMx21CC_MaxBurst_OFFSET 7
+#define GMMx21CC_MaxBurst_WIDTH 4
+#define GMMx21CC_MaxBurst_MASK 0x780
+#define GMMx21CC_LazyTimer_OFFSET 11
+#define GMMx21CC_LazyTimer_WIDTH 4
+#define GMMx21CC_LazyTimer_MASK 0x7800
+#define GMMx21CC_StallOverrideWtm_OFFSET 15
+#define GMMx21CC_StallOverrideWtm_WIDTH 1
+#define GMMx21CC_StallOverrideWtm_MASK 0x8000
+#define GMMx21CC_Reserved_31_16_OFFSET 16
+#define GMMx21CC_Reserved_31_16_WIDTH 16
+#define GMMx21CC_Reserved_31_16_MASK 0xffff0000
-/// GMMx27E0
+/// GMMx21CC
typedef union {
struct { ///<
- UINT32 Lcl:8 ; ///<
- UINT32 Hub:8 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx27E0_STRUCT;
+} GMMx21CC_STRUCT;
-// **** GMMx2814 Register Definition ****
+// **** GMMx21D0 Register Definition ****
// Address
-#define GMMx2814_ADDRESS 0x2814
+#define GMMx21D0_ADDRESS 0x21d0
// Type
-#define GMMx2814_TYPE TYPE_GMM
+#define GMMx21D0_TYPE TYPE_GMM
// Field Data
-#define GMMx2814_WriteClks_OFFSET 0
-#define GMMx2814_WriteClks_WIDTH 9
-#define GMMx2814_WriteClks_MASK 0x1ff
-#define GMMx2814_UvdHarshPriority_OFFSET 9
-#define GMMx2814_UvdHarshPriority_WIDTH 1
-#define GMMx2814_UvdHarshPriority_MASK 0x200
-#define GMMx2814_Reserved_31_10_OFFSET 10
-#define GMMx2814_Reserved_31_10_WIDTH 22
-#define GMMx2814_Reserved_31_10_MASK 0xfffffc00
+#define GMMx21D0_Enable_OFFSET 0
+#define GMMx21D0_Enable_WIDTH 1
+#define GMMx21D0_Enable_MASK 0x1
+#define GMMx21D0_Prescale_OFFSET 1
+#define GMMx21D0_Prescale_WIDTH 2
+#define GMMx21D0_Prescale_MASK 0x6
+#define GMMx21D0_BlackoutExempt_OFFSET 3
+#define GMMx21D0_BlackoutExempt_WIDTH 1
+#define GMMx21D0_BlackoutExempt_MASK 0x8
+#define GMMx21D0_StallMode_OFFSET 4
+#define GMMx21D0_StallMode_WIDTH 2
+#define GMMx21D0_StallMode_MASK 0x30
+#define GMMx21D0_StallOverride_OFFSET 6
+#define GMMx21D0_StallOverride_WIDTH 1
+#define GMMx21D0_StallOverride_MASK 0x40
+#define GMMx21D0_MaxBurst_OFFSET 7
+#define GMMx21D0_MaxBurst_WIDTH 4
+#define GMMx21D0_MaxBurst_MASK 0x780
+#define GMMx21D0_LazyTimer_OFFSET 11
+#define GMMx21D0_LazyTimer_WIDTH 4
+#define GMMx21D0_LazyTimer_MASK 0x7800
+#define GMMx21D0_StallOverrideWtm_OFFSET 15
+#define GMMx21D0_StallOverrideWtm_WIDTH 1
+#define GMMx21D0_StallOverrideWtm_MASK 0x8000
+#define GMMx21D0_Reserved_31_16_OFFSET 16
+#define GMMx21D0_Reserved_31_16_WIDTH 16
+#define GMMx21D0_Reserved_31_16_MASK 0xffff0000
-/// GMMx2814
+/// GMMx21D0
typedef union {
struct { ///<
- UINT32 WriteClks:9 ; ///<
- UINT32 UvdHarshPriority:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Prescale:2 ; ///<
+ UINT32 BlackoutExempt:1 ; ///<
+ UINT32 StallMode:2 ; ///<
+ UINT32 StallOverride:1 ; ///<
+ UINT32 MaxBurst:4 ; ///<
+ UINT32 LazyTimer:4 ; ///<
+ UINT32 StallOverrideWtm:1 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2814_STRUCT;
+} GMMx21D0_STRUCT;
-// **** GMMx281C Register Definition ****
+// **** GMMx25C0 Register Definition ****
// Address
-#define GMMx281C_ADDRESS 0x281c
+#define GMMx25C0_ADDRESS 0x25c0
// Type
-#define GMMx281C_TYPE TYPE_GMM
+#define GMMx25C0_TYPE TYPE_GMM
// Field Data
-#define GMMx281C_CSEnable_OFFSET 0
-#define GMMx281C_CSEnable_WIDTH 1
-#define GMMx281C_CSEnable_MASK 0x1
-#define GMMx281C_Reserved_4_1_OFFSET 1
-#define GMMx281C_Reserved_4_1_WIDTH 4
-#define GMMx281C_Reserved_4_1_MASK 0x1e
-#define GMMx281C_BaseAddr_21_13__OFFSET 5
-#define GMMx281C_BaseAddr_21_13__WIDTH 9
-#define GMMx281C_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx281C_Reserved_18_14_OFFSET 14
-#define GMMx281C_Reserved_18_14_WIDTH 5
-#define GMMx281C_Reserved_18_14_MASK 0x7c000
-#define GMMx281C_BaseAddr_35_27__OFFSET 19
-#define GMMx281C_BaseAddr_35_27__WIDTH 9
-#define GMMx281C_BaseAddr_35_27__MASK 0xff80000
-#define GMMx281C_Reserved_31_28_OFFSET 28
-#define GMMx281C_Reserved_31_28_WIDTH 4
-#define GMMx281C_Reserved_31_28_MASK 0xf0000000
+#define GMMx25C0_BlackoutRd_OFFSET 0
+#define GMMx25C0_BlackoutRd_WIDTH 1
+#define GMMx25C0_BlackoutRd_MASK 0x1
+#define GMMx25C0_BlackoutWr_OFFSET 1
+#define GMMx25C0_BlackoutWr_WIDTH 1
+#define GMMx25C0_BlackoutWr_MASK 0x2
+#define GMMx25C0_Reserved_31_2_OFFSET 2
+#define GMMx25C0_Reserved_31_2_WIDTH 30
+#define GMMx25C0_Reserved_31_2_MASK 0xfffffffc
-/// GMMx281C
+/// GMMx25C0
typedef union {
struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 BlackoutRd:1 ; ///<
+ UINT32 BlackoutWr:1 ; ///<
+ UINT32 Reserved_31_2:30; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx281C_STRUCT;
+} GMMx25C0_STRUCT;
-// **** GMMx2824 Register Definition ****
+// **** GMMx25C8 Register Definition ****
// Address
-#define GMMx2824_ADDRESS 0x2824
+#define GMMx25C8_ADDRESS 0x25c8
// Type
-#define GMMx2824_TYPE TYPE_GMM
+#define GMMx25C8_TYPE TYPE_GMM
// Field Data
-#define GMMx2824_CSEnable_OFFSET 0
-#define GMMx2824_CSEnable_WIDTH 1
-#define GMMx2824_CSEnable_MASK 0x1
-#define GMMx2824_Reserved_4_1_OFFSET 1
-#define GMMx2824_Reserved_4_1_WIDTH 4
-#define GMMx2824_Reserved_4_1_MASK 0x1e
-#define GMMx2824_BaseAddr_21_13__OFFSET 5
-#define GMMx2824_BaseAddr_21_13__WIDTH 9
-#define GMMx2824_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx2824_Reserved_18_14_OFFSET 14
-#define GMMx2824_Reserved_18_14_WIDTH 5
-#define GMMx2824_Reserved_18_14_MASK 0x7c000
-#define GMMx2824_BaseAddr_35_27__OFFSET 19
-#define GMMx2824_BaseAddr_35_27__WIDTH 9
-#define GMMx2824_BaseAddr_35_27__MASK 0xff80000
-#define GMMx2824_Reserved_31_28_OFFSET 28
-#define GMMx2824_Reserved_31_28_WIDTH 4
-#define GMMx2824_Reserved_31_28_MASK 0xf0000000
+#define GMMx25C8_ReadLcl_OFFSET 0
+#define GMMx25C8_ReadLcl_WIDTH 8
+#define GMMx25C8_ReadLcl_MASK 0xff
+#define GMMx25C8_ReadHub_OFFSET 8
+#define GMMx25C8_ReadHub_WIDTH 8
+#define GMMx25C8_ReadHub_MASK 0xff00
+#define GMMx25C8_ReadPri_OFFSET 16
+#define GMMx25C8_ReadPri_WIDTH 8
+#define GMMx25C8_ReadPri_MASK 0xff0000
+#define GMMx25C8_LclPri_OFFSET 24
+#define GMMx25C8_LclPri_WIDTH 1
+#define GMMx25C8_LclPri_MASK 0x1000000
+#define GMMx25C8_HubPri_OFFSET 25
+#define GMMx25C8_HubPri_WIDTH 1
+#define GMMx25C8_HubPri_MASK 0x2000000
+#define GMMx25C8_Reserved_31_26_OFFSET 26
+#define GMMx25C8_Reserved_31_26_WIDTH 6
+#define GMMx25C8_Reserved_31_26_MASK 0xfc000000
-/// GMMx2824
+/// GMMx25C8
typedef union {
struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 ReadLcl:8 ; ///<
+ UINT32 ReadHub:8 ; ///<
+ UINT32 ReadPri:8 ; ///<
+ UINT32 LclPri:1 ; ///<
+ UINT32 HubPri:1 ; ///<
+ UINT32 Reserved_31_26:6 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2824_STRUCT;
+} GMMx25C8_STRUCT;
-// **** GMMx282C Register Definition ****
+// **** GMMx25CC Register Definition ****
// Address
-#define GMMx282C_ADDRESS 0x282c
+#define GMMx25CC_ADDRESS 0x25cc
// Type
-#define GMMx282C_TYPE TYPE_GMM
+#define GMMx25CC_TYPE TYPE_GMM
// Field Data
-#define GMMx282C_CSEnable_OFFSET 0
-#define GMMx282C_CSEnable_WIDTH 1
-#define GMMx282C_CSEnable_MASK 0x1
-#define GMMx282C_Reserved_4_1_OFFSET 1
-#define GMMx282C_Reserved_4_1_WIDTH 4
-#define GMMx282C_Reserved_4_1_MASK 0x1e
-#define GMMx282C_BaseAddr_21_13__OFFSET 5
-#define GMMx282C_BaseAddr_21_13__WIDTH 9
-#define GMMx282C_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx282C_Reserved_18_14_OFFSET 14
-#define GMMx282C_Reserved_18_14_WIDTH 5
-#define GMMx282C_Reserved_18_14_MASK 0x7c000
-#define GMMx282C_BaseAddr_35_27__OFFSET 19
-#define GMMx282C_BaseAddr_35_27__WIDTH 9
-#define GMMx282C_BaseAddr_35_27__MASK 0xff80000
-#define GMMx282C_Reserved_31_28_OFFSET 28
-#define GMMx282C_Reserved_31_28_WIDTH 4
-#define GMMx282C_Reserved_31_28_MASK 0xf0000000
+#define GMMx25CC_WriteLcl_OFFSET 0
+#define GMMx25CC_WriteLcl_WIDTH 8
+#define GMMx25CC_WriteLcl_MASK 0xff
+#define GMMx25CC_WriteHub_OFFSET 8
+#define GMMx25CC_WriteHub_WIDTH 8
+#define GMMx25CC_WriteHub_MASK 0xff00
+#define GMMx25CC_HubPri_OFFSET 16
+#define GMMx25CC_HubPri_WIDTH 1
+#define GMMx25CC_HubPri_MASK 0x10000
+#define GMMx25CC_Reserved_31_17_OFFSET 17
+#define GMMx25CC_Reserved_31_17_WIDTH 15
+#define GMMx25CC_Reserved_31_17_MASK 0xfffe0000
-/// GMMx282C
+/// GMMx25CC
typedef union {
struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 WriteLcl:8 ; ///<
+ UINT32 WriteHub:8 ; ///<
+ UINT32 HubPri:1 ; ///<
+ UINT32 Reserved_31_17:15; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx282C_STRUCT;
+} GMMx25CC_STRUCT;
-// **** GMMx2834 Register Definition ****
+// **** GMMx2610 Register Definition ****
// Address
-#define GMMx2834_ADDRESS 0x2834
+#define GMMx2610_ADDRESS 0x2610
// Type
-#define GMMx2834_TYPE TYPE_GMM
+#define GMMx2610_TYPE TYPE_GMM
// Field Data
-#define GMMx2834_CSEnable_OFFSET 0
-#define GMMx2834_CSEnable_WIDTH 1
-#define GMMx2834_CSEnable_MASK 0x1
-#define GMMx2834_Reserved_4_1_OFFSET 1
-#define GMMx2834_Reserved_4_1_WIDTH 4
-#define GMMx2834_Reserved_4_1_MASK 0x1e
-#define GMMx2834_BaseAddr_21_13__OFFSET 5
-#define GMMx2834_BaseAddr_21_13__WIDTH 9
-#define GMMx2834_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx2834_Reserved_18_14_OFFSET 14
-#define GMMx2834_Reserved_18_14_WIDTH 5
-#define GMMx2834_Reserved_18_14_MASK 0x7c000
-#define GMMx2834_BaseAddr_35_27__OFFSET 19
-#define GMMx2834_BaseAddr_35_27__WIDTH 9
-#define GMMx2834_BaseAddr_35_27__MASK 0xff80000
-#define GMMx2834_Reserved_31_28_OFFSET 28
-#define GMMx2834_Reserved_31_28_WIDTH 4
-#define GMMx2834_Reserved_31_28_MASK 0xf0000000
+#define GMMx2610_TctFetch0_OFFSET 0
+#define GMMx2610_TctFetch0_WIDTH 4
+#define GMMx2610_TctFetch0_MASK 0xf
+#define GMMx2610_TcvFetch0_OFFSET 4
+#define GMMx2610_TcvFetch0_WIDTH 4
+#define GMMx2610_TcvFetch0_MASK 0xf0
+#define GMMx2610_Vc0_OFFSET 8
+#define GMMx2610_Vc0_WIDTH 4
+#define GMMx2610_Vc0_MASK 0xf00
+#define GMMx2610_Cb0_OFFSET 12
+#define GMMx2610_Cb0_WIDTH 4
+#define GMMx2610_Cb0_MASK 0xf000
+#define GMMx2610_CbcMask0_OFFSET 16
+#define GMMx2610_CbcMask0_WIDTH 4
+#define GMMx2610_CbcMask0_MASK 0xf0000
+#define GMMx2610_CbfMask0_OFFSET 20
+#define GMMx2610_CbfMask0_WIDTH 4
+#define GMMx2610_CbfMask0_MASK 0xf00000
+#define GMMx2610_Db0_OFFSET 24
+#define GMMx2610_Db0_WIDTH 4
+#define GMMx2610_Db0_MASK 0xf000000
+#define GMMx2610_DbhTile0_OFFSET 28
+#define GMMx2610_DbhTile0_WIDTH 4
+#define GMMx2610_DbhTile0_MASK 0xf0000000
-/// GMMx2834
+/// GMMx2610
typedef union {
struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 TctFetch0:4 ; ///<
+ UINT32 TcvFetch0:4 ; ///<
+ UINT32 Vc0:4 ; ///<
+ UINT32 Cb0:4 ; ///<
+ UINT32 CbcMask0:4 ; ///<
+ UINT32 CbfMask0:4 ; ///<
+ UINT32 Db0:4 ; ///<
+ UINT32 DbhTile0:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2834_STRUCT;
+} GMMx2610_STRUCT;
-// **** GMMx283C Register Definition ****
+// **** GMMx2614 Register Definition ****
// Address
-#define GMMx283C_ADDRESS 0x283c
+#define GMMx2614_ADDRESS 0x2614
// Type
-#define GMMx283C_TYPE TYPE_GMM
+#define GMMx2614_TYPE TYPE_GMM
// Field Data
-#define GMMx283C_Reserved_4_0_OFFSET 0
-#define GMMx283C_Reserved_4_0_WIDTH 5
-#define GMMx283C_Reserved_4_0_MASK 0x1f
-#define GMMx283C_AddrMask_21_13__OFFSET 5
-#define GMMx283C_AddrMask_21_13__WIDTH 9
-#define GMMx283C_AddrMask_21_13__MASK 0x3fe0
-#define GMMx283C_Reserved_18_14_OFFSET 14
-#define GMMx283C_Reserved_18_14_WIDTH 5
-#define GMMx283C_Reserved_18_14_MASK 0x7c000
-#define GMMx283C_AddrMask_35_27__OFFSET 19
-#define GMMx283C_AddrMask_35_27__WIDTH 9
-#define GMMx283C_AddrMask_35_27__MASK 0xff80000
-#define GMMx283C_Reserved_28_28_OFFSET 28
-#define GMMx283C_Reserved_28_28_WIDTH 1
-#define GMMx283C_Reserved_28_28_MASK 0x10000000
-#define GMMx283C_Reserved_31_29_OFFSET 29
-#define GMMx283C_Reserved_31_29_WIDTH 3
-#define GMMx283C_Reserved_31_29_MASK 0xe0000000
+#define GMMx2614_Cb0_OFFSET 0
+#define GMMx2614_Cb0_WIDTH 4
+#define GMMx2614_Cb0_MASK 0xf
+#define GMMx2614_CbcMask0_OFFSET 4
+#define GMMx2614_CbcMask0_WIDTH 4
+#define GMMx2614_CbcMask0_MASK 0xf0
+#define GMMx2614_CbfMask0_OFFSET 8
+#define GMMx2614_CbfMask0_WIDTH 4
+#define GMMx2614_CbfMask0_MASK 0xf00
+#define GMMx2614_Db0_OFFSET 12
+#define GMMx2614_Db0_WIDTH 4
+#define GMMx2614_Db0_MASK 0xf000
+#define GMMx2614_DbhTile0_OFFSET 16
+#define GMMx2614_DbhTile0_WIDTH 4
+#define GMMx2614_DbhTile0_MASK 0xf0000
+#define GMMx2614_Sx0_OFFSET 20
+#define GMMx2614_Sx0_WIDTH 4
+#define GMMx2614_Sx0_MASK 0xf00000
+#define GMMx2614_Bcast0_OFFSET 24
+#define GMMx2614_Bcast0_WIDTH 4
+#define GMMx2614_Bcast0_MASK 0xf000000
+#define GMMx2614_Cbimmed0_OFFSET 28
+#define GMMx2614_Cbimmed0_WIDTH 4
+#define GMMx2614_Cbimmed0_MASK 0xf0000000
-/// GMMx283C
+/// GMMx2614
typedef union {
struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 AddrMask_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 AddrMask_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
+ UINT32 Cb0:4 ; ///<
+ UINT32 CbcMask0:4 ; ///<
+ UINT32 CbfMask0:4 ; ///<
+ UINT32 Db0:4 ; ///<
+ UINT32 DbhTile0:4 ; ///<
+ UINT32 Sx0:4 ; ///<
+ UINT32 Bcast0:4 ; ///<
+ UINT32 Cbimmed0:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx283C_STRUCT;
+} GMMx2614_STRUCT;
-// **** GMMx2840 Register Definition ****
+// **** GMMx2618 Register Definition ****
// Address
-#define GMMx2840_ADDRESS 0x2840
+#define GMMx2618_ADDRESS 0x2618
// Type
-#define GMMx2840_TYPE TYPE_GMM
+#define GMMx2618_TYPE TYPE_GMM
// Field Data
-#define GMMx2840_Reserved_4_0_OFFSET 0
-#define GMMx2840_Reserved_4_0_WIDTH 5
-#define GMMx2840_Reserved_4_0_MASK 0x1f
-#define GMMx2840_AddrMask_21_13__OFFSET 5
-#define GMMx2840_AddrMask_21_13__WIDTH 9
-#define GMMx2840_AddrMask_21_13__MASK 0x3fe0
-#define GMMx2840_Reserved_18_14_OFFSET 14
-#define GMMx2840_Reserved_18_14_WIDTH 5
-#define GMMx2840_Reserved_18_14_MASK 0x7c000
-#define GMMx2840_AddrMask_35_27__OFFSET 19
-#define GMMx2840_AddrMask_35_27__WIDTH 9
-#define GMMx2840_AddrMask_35_27__MASK 0xff80000
-#define GMMx2840_Reserved_28_28_OFFSET 28
-#define GMMx2840_Reserved_28_28_WIDTH 1
-#define GMMx2840_Reserved_28_28_MASK 0x10000000
-#define GMMx2840_Reserved_31_29_OFFSET 29
-#define GMMx2840_Reserved_31_29_WIDTH 3
-#define GMMx2840_Reserved_31_29_MASK 0xe0000000
+#define GMMx2618_DbstEn0_OFFSET 0
+#define GMMx2618_DbstEn0_WIDTH 4
+#define GMMx2618_DbstEn0_MASK 0xf
+#define GMMx2618_TcvFetch1_OFFSET 4
+#define GMMx2618_TcvFetch1_WIDTH 4
+#define GMMx2618_TcvFetch1_MASK 0xf0
+#define GMMx2618_TctFetch1_OFFSET 8
+#define GMMx2618_TctFetch1_WIDTH 4
+#define GMMx2618_TctFetch1_MASK 0xf00
+#define GMMx2618_Vc1_OFFSET 12
+#define GMMx2618_Vc1_WIDTH 4
+#define GMMx2618_Vc1_MASK 0xf000
+#define GMMx2618_Reserved_31_16_OFFSET 16
+#define GMMx2618_Reserved_31_16_WIDTH 16
+#define GMMx2618_Reserved_31_16_MASK 0xffff0000
-/// GMMx2840
+/// GMMx2618
typedef union {
struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 AddrMask_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 AddrMask_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
+ UINT32 DbstEn0:4 ; ///<
+ UINT32 TcvFetch1:4 ; ///<
+ UINT32 TctFetch1:4 ; ///<
+ UINT32 Vc1:4 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2840_STRUCT;
+} GMMx2618_STRUCT;
-// **** GMMx284C Register Definition ****
+// **** GMMx261C Register Definition ****
// Address
-#define GMMx284C_ADDRESS 0x284c
+#define GMMx261C_ADDRESS 0x261c
// Type
-#define GMMx284C_TYPE TYPE_GMM
+#define GMMx261C_TYPE TYPE_GMM
// Field Data
-#define GMMx284C_Dimm0AddrMap_OFFSET 0
-#define GMMx284C_Dimm0AddrMap_WIDTH 4
-#define GMMx284C_Dimm0AddrMap_MASK 0xf
-#define GMMx284C_Dimm1AddrMap_OFFSET 4
-#define GMMx284C_Dimm1AddrMap_WIDTH 4
-#define GMMx284C_Dimm1AddrMap_MASK 0xf0
-#define GMMx284C_Reserved_15_8_OFFSET 8
-#define GMMx284C_Reserved_15_8_WIDTH 8
-#define GMMx284C_Reserved_15_8_MASK 0xff00
-#define GMMx284C_BankSwizzleMode_OFFSET 16
-#define GMMx284C_BankSwizzleMode_WIDTH 1
-#define GMMx284C_BankSwizzleMode_MASK 0x10000
-#define GMMx284C_Reserved_18_17_OFFSET 17
-#define GMMx284C_Reserved_18_17_WIDTH 2
-#define GMMx284C_Reserved_18_17_MASK 0x60000
-#define GMMx284C_BankSwap_OFFSET 19
-#define GMMx284C_BankSwap_WIDTH 1
-#define GMMx284C_BankSwap_MASK 0x80000
-#define GMMx284C_Reserved_31_20_OFFSET 20
-#define GMMx284C_Reserved_31_20_WIDTH 12
-#define GMMx284C_Reserved_31_20_MASK 0xfff00000
+#define GMMx261C_DbstEn0_OFFSET 0
+#define GMMx261C_DbstEn0_WIDTH 4
+#define GMMx261C_DbstEn0_MASK 0xf
+#define GMMx261C_Reserved_31_4_OFFSET 4
+#define GMMx261C_Reserved_31_4_WIDTH 28
+#define GMMx261C_Reserved_31_4_MASK 0xfffffff0
-/// GMMx284C
+/// GMMx261C
typedef union {
struct { ///<
- UINT32 Dimm0AddrMap:4 ; ///<
- UINT32 Dimm1AddrMap:4 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 BankSwizzleMode:1 ; ///<
- UINT32 Reserved_18_17:2 ; ///<
- UINT32 BankSwap:1 ; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 DbstEn0:4 ; ///<
+ UINT32 Reserved_31_4:28; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx284C_STRUCT;
+} GMMx261C_STRUCT;
-// **** GMMx2858 Register Definition ****
+// **** GMMx2638 Register Definition ****
// Address
-#define GMMx2858_ADDRESS 0x2858
+#define GMMx2638_ADDRESS 0x2638
// Type
-#define GMMx2858_TYPE TYPE_GMM
+#define GMMx2638_TYPE TYPE_GMM
// Field Data
-#define GMMx2858_Reserved_8_0_OFFSET 0
-#define GMMx2858_Reserved_8_0_WIDTH 9
-#define GMMx2858_Reserved_8_0_MASK 0x1ff
-#define GMMx2858_DctSelBankSwap_OFFSET 9
-#define GMMx2858_DctSelBankSwap_WIDTH 1
-#define GMMx2858_DctSelBankSwap_MASK 0x200
-#define GMMx2858_Reserved_31_10_OFFSET 10
-#define GMMx2858_Reserved_31_10_WIDTH 22
-#define GMMx2858_Reserved_31_10_MASK 0xfffffc00
+#define GMMx2638_Reserved_17_0_OFFSET 0
+#define GMMx2638_Reserved_17_0_WIDTH 18
+#define GMMx2638_Reserved_17_0_MASK 0x3ffff
+#define GMMx2638_Enable_OFFSET 18
+#define GMMx2638_Enable_WIDTH 1
+#define GMMx2638_Enable_MASK 0x40000
+#define GMMx2638_Reserved_31_19_OFFSET 19
+#define GMMx2638_Reserved_31_19_WIDTH 13
+#define GMMx2638_Reserved_31_19_MASK 0xfff80000
-/// GMMx2858
+/// GMMx2638
typedef union {
struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 DctSelBankSwap:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
+ UINT32 Reserved_17_0:18; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2858_STRUCT;
+} GMMx2638_STRUCT;
-// **** GMMx285C Register Definition ****
+// **** GMMx263C Register Definition ****
// Address
-#define GMMx285C_ADDRESS 0x285c
+#define GMMx263C_ADDRESS 0x263c
// Type
-#define GMMx285C_TYPE TYPE_GMM
+#define GMMx263C_TYPE TYPE_GMM
// Field Data
-#define GMMx285C_DramHoleValid_OFFSET 0
-#define GMMx285C_DramHoleValid_WIDTH 1
-#define GMMx285C_DramHoleValid_MASK 0x1
-#define GMMx285C_Reserved_6_1_OFFSET 1
-#define GMMx285C_Reserved_6_1_WIDTH 6
-#define GMMx285C_Reserved_6_1_MASK 0x7e
-#define GMMx285C_DramHoleOffset_31_23__OFFSET 7
-#define GMMx285C_DramHoleOffset_31_23__WIDTH 9
-#define GMMx285C_DramHoleOffset_31_23__MASK 0xff80
-#define GMMx285C_Reserved_23_16_OFFSET 16
-#define GMMx285C_Reserved_23_16_WIDTH 8
-#define GMMx285C_Reserved_23_16_MASK 0xff0000
-#define GMMx285C_DramHoleBase_31_24__OFFSET 24
-#define GMMx285C_DramHoleBase_31_24__WIDTH 8
-#define GMMx285C_DramHoleBase_31_24__MASK 0xff000000
+#define GMMx263C_Reserved_17_0_OFFSET 0
+#define GMMx263C_Reserved_17_0_WIDTH 18
+#define GMMx263C_Reserved_17_0_MASK 0x3ffff
+#define GMMx263C_Enable_OFFSET 18
+#define GMMx263C_Enable_WIDTH 1
+#define GMMx263C_Enable_MASK 0x40000
+#define GMMx263C_Reserved_31_19_OFFSET 19
+#define GMMx263C_Reserved_31_19_WIDTH 13
+#define GMMx263C_Reserved_31_19_MASK 0xfff80000
-/// GMMx285C
+/// GMMx263C
typedef union {
struct { ///<
- UINT32 DramHoleValid:1 ; ///<
- UINT32 Reserved_6_1:6 ; ///<
- UINT32 DramHoleOffset_31_23_:9 ; ///<
- UINT32 Reserved_23_16:8 ; ///<
- UINT32 DramHoleBase_31_24_:8 ; ///<
+ UINT32 Reserved_17_0:18; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx285C_STRUCT;
+} GMMx263C_STRUCT;
-// **** GMMx2864 Register Definition ****
+// **** GMMx2640 Register Definition ****
// Address
-#define GMMx2864_ADDRESS 0x2864
+#define GMMx2640_ADDRESS 0x2640
// Type
-#define GMMx2864_TYPE TYPE_GMM
+#define GMMx2640_TYPE TYPE_GMM
// Field Data
-#define GMMx2864_A8Map_OFFSET 0
-#define GMMx2864_A8Map_WIDTH 4
-#define GMMx2864_A8Map_MASK 0xf
-#define GMMx2864_A9Map_OFFSET 4
-#define GMMx2864_A9Map_WIDTH 4
-#define GMMx2864_A9Map_MASK 0xf0
-#define GMMx2864_A10Map_OFFSET 8
-#define GMMx2864_A10Map_WIDTH 4
-#define GMMx2864_A10Map_MASK 0xf00
-#define GMMx2864_A11Map_OFFSET 12
-#define GMMx2864_A11Map_WIDTH 4
-#define GMMx2864_A11Map_MASK 0xf000
-#define GMMx2864_A12Map_OFFSET 16
-#define GMMx2864_A12Map_WIDTH 4
-#define GMMx2864_A12Map_MASK 0xf0000
-#define GMMx2864_A13Map_OFFSET 20
-#define GMMx2864_A13Map_WIDTH 4
-#define GMMx2864_A13Map_MASK 0xf00000
-#define GMMx2864_A14Map_OFFSET 24
-#define GMMx2864_A14Map_WIDTH 4
-#define GMMx2864_A14Map_MASK 0xf000000
-#define GMMx2864_A15Map_OFFSET 28
-#define GMMx2864_A15Map_WIDTH 4
-#define GMMx2864_A15Map_MASK 0xf0000000
+#define GMMx2640_Reserved_17_0_OFFSET 0
+#define GMMx2640_Reserved_17_0_WIDTH 18
+#define GMMx2640_Reserved_17_0_MASK 0x3ffff
+#define GMMx2640_Enable_OFFSET 18
+#define GMMx2640_Enable_WIDTH 1
+#define GMMx2640_Enable_MASK 0x40000
+#define GMMx2640_Reserved_31_19_OFFSET 19
+#define GMMx2640_Reserved_31_19_WIDTH 13
+#define GMMx2640_Reserved_31_19_MASK 0xfff80000
-/// GMMx2864
+/// GMMx2640
typedef union {
struct { ///<
- UINT32 A8Map:4 ; ///<
- UINT32 A9Map:4 ; ///<
- UINT32 A10Map:4 ; ///<
- UINT32 A11Map:4 ; ///<
- UINT32 A12Map:4 ; ///<
- UINT32 A13Map:4 ; ///<
- UINT32 A14Map:4 ; ///<
- UINT32 A15Map:4 ; ///<
+ UINT32 Reserved_17_0:18; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2864_STRUCT;
+} GMMx2640_STRUCT;
-// **** GMMx286C Register Definition ****
+// **** GMMx277C Register Definition ****
// Address
-#define GMMx286C_ADDRESS 0x286c
+#define GMMx277C_ADDRESS 0x277c
// Type
-#define GMMx286C_TYPE TYPE_GMM
+#define GMMx277C_TYPE TYPE_GMM
// Field Data
-#define GMMx286C_Base_OFFSET 0
-#define GMMx286C_Base_WIDTH 20
-#define GMMx286C_Base_MASK 0xfffff
-#define GMMx286C_Reserved_31_20_OFFSET 20
-#define GMMx286C_Reserved_31_20_WIDTH 12
-#define GMMx286C_Reserved_31_20_MASK 0xfff00000
+#define GMMx277C_ActRd_OFFSET 0
+#define GMMx277C_ActRd_WIDTH 8
+#define GMMx277C_ActRd_MASK 0xff
+#define GMMx277C_ActWr_OFFSET 8
+#define GMMx277C_ActWr_WIDTH 8
+#define GMMx277C_ActWr_MASK 0xff00
+#define GMMx277C_RasMActRd_OFFSET 16
+#define GMMx277C_RasMActRd_WIDTH 8
+#define GMMx277C_RasMActRd_MASK 0xff0000
+#define GMMx277C_RasMActWr_OFFSET 24
+#define GMMx277C_RasMActWr_WIDTH 8
+#define GMMx277C_RasMActWr_MASK 0xff000000
-/// GMMx286C
+/// GMMx277C
typedef union {
struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 ActRd:8 ; ///<
+ UINT32 ActWr:8 ; ///<
+ UINT32 RasMActRd:8 ; ///<
+ UINT32 RasMActWr:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx286C_STRUCT;
+} GMMx277C_STRUCT;
-// **** GMMx2870 Register Definition ****
+// **** GMMx2780 Register Definition ****
// Address
-#define GMMx2870_ADDRESS 0x2870
+#define GMMx2780_ADDRESS 0x2780
// Type
-#define GMMx2870_TYPE TYPE_GMM
+#define GMMx2780_TYPE TYPE_GMM
// Field Data
-#define GMMx2870_Base_OFFSET 0
-#define GMMx2870_Base_WIDTH 20
-#define GMMx2870_Base_MASK 0xfffff
-#define GMMx2870_Reserved_31_20_OFFSET 20
-#define GMMx2870_Reserved_31_20_WIDTH 12
-#define GMMx2870_Reserved_31_20_MASK 0xfff00000
+#define GMMx2780_Ras2Ras_OFFSET 0
+#define GMMx2780_Ras2Ras_WIDTH 8
+#define GMMx2780_Ras2Ras_MASK 0xff
+#define GMMx2780_Rp_OFFSET 8
+#define GMMx2780_Rp_WIDTH 8
+#define GMMx2780_Rp_MASK 0xff00
+#define GMMx2780_WrPlusRp_OFFSET 16
+#define GMMx2780_WrPlusRp_WIDTH 8
+#define GMMx2780_WrPlusRp_MASK 0xff0000
+#define GMMx2780_BusTurn_OFFSET 24
+#define GMMx2780_BusTurn_WIDTH 8
+#define GMMx2780_BusTurn_MASK 0xff000000
-/// GMMx2870
+/// GMMx2780
typedef union {
struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 Ras2Ras:8 ; ///<
+ UINT32 Rp:8 ; ///<
+ UINT32 WrPlusRp:8 ; ///<
+ UINT32 BusTurn:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2870_STRUCT;
+} GMMx2780_STRUCT;
-// **** GMMx2874 Register Definition ****
+// **** GMMx2784 Register Definition ****
// Address
-#define GMMx2874_ADDRESS 0x2874
+#define GMMx2784_ADDRESS 0x2784
// Type
-#define GMMx2874_TYPE TYPE_GMM
+#define GMMx2784_TYPE TYPE_GMM
// Field Data
-#define GMMx2874_Base_OFFSET 0
-#define GMMx2874_Base_WIDTH 20
-#define GMMx2874_Base_MASK 0xfffff
-#define GMMx2874_Reserved_31_20_OFFSET 20
-#define GMMx2874_Reserved_31_20_WIDTH 12
-#define GMMx2874_Reserved_31_20_MASK 0xfff00000
+#define GMMx2784_WtMode_OFFSET 0
+#define GMMx2784_WtMode_WIDTH 2
+#define GMMx2784_WtMode_MASK 0x3
+#define GMMx2784_HarshPri_OFFSET 2
+#define GMMx2784_HarshPri_WIDTH 1
+#define GMMx2784_HarshPri_MASK 0x4
+#define GMMx2784_Reserved_31_3_OFFSET 3
+#define GMMx2784_Reserved_31_3_WIDTH 29
+#define GMMx2784_Reserved_31_3_MASK 0xfffffff8
-/// GMMx2874
+/// GMMx2784
typedef union {
struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 WtMode:2 ; ///<
+ UINT32 HarshPri:1 ; ///<
+ UINT32 Reserved_31_3:29; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2874_STRUCT;
+} GMMx2784_STRUCT;
-// **** GMMx2878 Register Definition ****
+// **** GMMx2788 Register Definition ****
// Address
-#define GMMx2878_ADDRESS 0x2878
+#define GMMx2788_ADDRESS 0x2788
// Type
-#define GMMx2878_TYPE TYPE_GMM
+#define GMMx2788_TYPE TYPE_GMM
// Field Data
-#define GMMx2878_Base_OFFSET 0
-#define GMMx2878_Base_WIDTH 20
-#define GMMx2878_Base_MASK 0xfffff
-#define GMMx2878_Reserved_31_20_OFFSET 20
-#define GMMx2878_Reserved_31_20_WIDTH 12
-#define GMMx2878_Reserved_31_20_MASK 0xfff00000
+#define GMMx2788_WtMode_OFFSET 0
+#define GMMx2788_WtMode_WIDTH 2
+#define GMMx2788_WtMode_MASK 0x3
+#define GMMx2788_HarshPri_OFFSET 2
+#define GMMx2788_HarshPri_WIDTH 1
+#define GMMx2788_HarshPri_MASK 0x4
+#define GMMx2788_Reserved_31_3_OFFSET 3
+#define GMMx2788_Reserved_31_3_WIDTH 29
+#define GMMx2788_Reserved_31_3_MASK 0xfffffff8
-/// GMMx2878
+/// GMMx2788
typedef union {
struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 WtMode:2 ; ///<
+ UINT32 HarshPri:1 ; ///<
+ UINT32 Reserved_31_3:29; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2878_STRUCT;
+} GMMx2788_STRUCT;
-// **** GMMx287C Register Definition ****
+// **** GMMx279C Register Definition ****
// Address
-#define GMMx287C_ADDRESS 0x287c
+#define GMMx279C_ADDRESS 0x279c
// Type
-#define GMMx287C_TYPE TYPE_GMM
+#define GMMx279C_TYPE TYPE_GMM
// Field Data
-#define GMMx287C_Top_OFFSET 0
-#define GMMx287C_Top_WIDTH 20
-#define GMMx287C_Top_MASK 0xfffff
-#define GMMx287C_Reserved_31_20_OFFSET 20
-#define GMMx287C_Reserved_31_20_WIDTH 12
-#define GMMx287C_Reserved_31_20_MASK 0xfff00000
+#define GMMx279C_Group0_OFFSET 0
+#define GMMx279C_Group0_WIDTH 8
+#define GMMx279C_Group0_MASK 0xff
+#define GMMx279C_Group1_OFFSET 8
+#define GMMx279C_Group1_WIDTH 8
+#define GMMx279C_Group1_MASK 0xff00
+#define GMMx279C_Group2_OFFSET 16
+#define GMMx279C_Group2_WIDTH 8
+#define GMMx279C_Group2_MASK 0xff0000
+#define GMMx279C_Group3_OFFSET 24
+#define GMMx279C_Group3_WIDTH 8
+#define GMMx279C_Group3_MASK 0xff000000
-/// GMMx287C
+/// GMMx279C
typedef union {
struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 Group0:8 ; ///<
+ UINT32 Group1:8 ; ///<
+ UINT32 Group2:8 ; ///<
+ UINT32 Group3:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx287C_STRUCT;
+} GMMx279C_STRUCT;
-// **** GMMx2880 Register Definition ****
+// **** GMMx27A0 Register Definition ****
// Address
-#define GMMx2880_ADDRESS 0x2880
+#define GMMx27A0_ADDRESS 0x27a0
// Type
-#define GMMx2880_TYPE TYPE_GMM
+#define GMMx27A0_TYPE TYPE_GMM
// Field Data
-#define GMMx2880_Top_OFFSET 0
-#define GMMx2880_Top_WIDTH 20
-#define GMMx2880_Top_MASK 0xfffff
-#define GMMx2880_Reserved_31_20_OFFSET 20
-#define GMMx2880_Reserved_31_20_WIDTH 12
-#define GMMx2880_Reserved_31_20_MASK 0xfff00000
+#define GMMx27A0_Group0_OFFSET 0
+#define GMMx27A0_Group0_WIDTH 8
+#define GMMx27A0_Group0_MASK 0xff
+#define GMMx27A0_Group1_OFFSET 8
+#define GMMx27A0_Group1_WIDTH 8
+#define GMMx27A0_Group1_MASK 0xff00
+#define GMMx27A0_Group2_OFFSET 16
+#define GMMx27A0_Group2_WIDTH 8
+#define GMMx27A0_Group2_MASK 0xff0000
+#define GMMx27A0_Group3_OFFSET 24
+#define GMMx27A0_Group3_WIDTH 8
+#define GMMx27A0_Group3_MASK 0xff000000
-/// GMMx2880
+/// GMMx27A0
typedef union {
struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 Group0:8 ; ///<
+ UINT32 Group1:8 ; ///<
+ UINT32 Group2:8 ; ///<
+ UINT32 Group3:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2880_STRUCT;
+} GMMx27A0_STRUCT;
-// **** GMMx2884 Register Definition ****
+// **** GMMx27CC Register Definition ****
// Address
-#define GMMx2884_ADDRESS 0x2884
+#define GMMx27CC_ADDRESS 0x27cc
// Type
-#define GMMx2884_TYPE TYPE_GMM
+#define GMMx27CC_TYPE TYPE_GMM
// Field Data
-#define GMMx2884_Top_OFFSET 0
-#define GMMx2884_Top_WIDTH 20
-#define GMMx2884_Top_MASK 0xfffff
-#define GMMx2884_Reserved_31_20_OFFSET 20
-#define GMMx2884_Reserved_31_20_WIDTH 12
-#define GMMx2884_Reserved_31_20_MASK 0xfff00000
+#define GMMx27CC_StreakLimit_OFFSET 0
+#define GMMx27CC_StreakLimit_WIDTH 8
+#define GMMx27CC_StreakLimit_MASK 0xff
+#define GMMx27CC_StreakLimitUber_OFFSET 8
+#define GMMx27CC_StreakLimitUber_WIDTH 8
+#define GMMx27CC_StreakLimitUber_MASK 0xff00
+#define GMMx27CC_StreakBreak_OFFSET 16
+#define GMMx27CC_StreakBreak_WIDTH 1
+#define GMMx27CC_StreakBreak_MASK 0x10000
+#define GMMx27CC_StreakUber_OFFSET 17
+#define GMMx27CC_StreakUber_WIDTH 1
+#define GMMx27CC_StreakUber_MASK 0x20000
+#define GMMx27CC_Reserved_31_18_OFFSET 18
+#define GMMx27CC_Reserved_31_18_WIDTH 14
+#define GMMx27CC_Reserved_31_18_MASK 0xfffc0000
-/// GMMx2884
+/// GMMx27CC
typedef union {
struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 StreakLimit:8 ; ///<
+ UINT32 StreakLimitUber:8 ; ///<
+ UINT32 StreakBreak:1 ; ///<
+ UINT32 StreakUber:1 ; ///<
+ UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2884_STRUCT;
+} GMMx27CC_STRUCT;
-// **** GMMx2888 Register Definition ****
+// **** GMMx27D0 Register Definition ****
// Address
-#define GMMx2888_ADDRESS 0x2888
+#define GMMx27D0_ADDRESS 0x27d0
// Type
-#define GMMx2888_TYPE TYPE_GMM
+#define GMMx27D0_TYPE TYPE_GMM
// Field Data
-#define GMMx2888_Top_OFFSET 0
-#define GMMx2888_Top_WIDTH 20
-#define GMMx2888_Top_MASK 0xfffff
-#define GMMx2888_Reserved_31_20_OFFSET 20
-#define GMMx2888_Reserved_31_20_WIDTH 12
-#define GMMx2888_Reserved_31_20_MASK 0xfff00000
+#define GMMx27D0_StreakLimit_OFFSET 0
+#define GMMx27D0_StreakLimit_WIDTH 8
+#define GMMx27D0_StreakLimit_MASK 0xff
+#define GMMx27D0_StreakLimitUber_OFFSET 8
+#define GMMx27D0_StreakLimitUber_WIDTH 8
+#define GMMx27D0_StreakLimitUber_MASK 0xff00
+#define GMMx27D0_StreakBreak_OFFSET 16
+#define GMMx27D0_StreakBreak_WIDTH 1
+#define GMMx27D0_StreakBreak_MASK 0x10000
+#define GMMx27D0_StreakUber_OFFSET 17
+#define GMMx27D0_StreakUber_WIDTH 1
+#define GMMx27D0_StreakUber_MASK 0x20000
+#define GMMx27D0_Reserved_31_18_OFFSET 18
+#define GMMx27D0_Reserved_31_18_WIDTH 14
+#define GMMx27D0_Reserved_31_18_MASK 0xfffc0000
-/// GMMx2888
+/// GMMx27D0
typedef union {
struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 StreakLimit:8 ; ///<
+ UINT32 StreakLimitUber:8 ; ///<
+ UINT32 StreakBreak:1 ; ///<
+ UINT32 StreakUber:1 ; ///<
+ UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2888_STRUCT;
+} GMMx27D0_STRUCT;
-// **** GMMx288C Register Definition ****
+// **** GMMx27DC Register Definition ****
// Address
-#define GMMx288C_ADDRESS 0x288c
+#define GMMx27DC_ADDRESS 0x27dc
// Type
-#define GMMx288C_TYPE TYPE_GMM
+#define GMMx27DC_TYPE TYPE_GMM
// Field Data
-#define GMMx288C_Base_OFFSET 0
-#define GMMx288C_Base_WIDTH 20
-#define GMMx288C_Base_MASK 0xfffff
-#define GMMx288C_Reserved_31_20_OFFSET 20
-#define GMMx288C_Reserved_31_20_WIDTH 12
-#define GMMx288C_Reserved_31_20_MASK 0xfff00000
+#define GMMx27DC_Lcl_OFFSET 0
+#define GMMx27DC_Lcl_WIDTH 8
+#define GMMx27DC_Lcl_MASK 0xff
+#define GMMx27DC_Hub_OFFSET 8
+#define GMMx27DC_Hub_WIDTH 8
+#define GMMx27DC_Hub_MASK 0xff00
+#define GMMx27DC_Disp_OFFSET 16
+#define GMMx27DC_Disp_WIDTH 8
+#define GMMx27DC_Disp_MASK 0xff0000
+#define GMMx27DC_Reserved_31_24_OFFSET 24
+#define GMMx27DC_Reserved_31_24_WIDTH 8
+#define GMMx27DC_Reserved_31_24_MASK 0xff000000
-/// GMMx288C
+/// GMMx27DC
typedef union {
struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 Lcl:8 ; ///<
+ UINT32 Hub:8 ; ///<
+ UINT32 Disp:8 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx288C_STRUCT;
+} GMMx27DC_STRUCT;
-// **** GMMx2890 Register Definition ****
+// **** GMMx27E0 Register Definition ****
// Address
-#define GMMx2890_ADDRESS 0x2890
+#define GMMx27E0_ADDRESS 0x27e0
// Type
-#define GMMx2890_TYPE TYPE_GMM
+#define GMMx27E0_TYPE TYPE_GMM
// Field Data
-#define GMMx2890_Top_OFFSET 0
-#define GMMx2890_Top_WIDTH 20
-#define GMMx2890_Top_MASK 0xfffff
-#define GMMx2890_Reserved_31_20_OFFSET 20
-#define GMMx2890_Reserved_31_20_WIDTH 12
-#define GMMx2890_Reserved_31_20_MASK 0xfff00000
+#define GMMx27E0_Lcl_OFFSET 0
+#define GMMx27E0_Lcl_WIDTH 8
+#define GMMx27E0_Lcl_MASK 0xff
+#define GMMx27E0_Hub_OFFSET 8
+#define GMMx27E0_Hub_WIDTH 8
+#define GMMx27E0_Hub_MASK 0xff00
+#define GMMx27E0_Reserved_31_16_OFFSET 16
+#define GMMx27E0_Reserved_31_16_WIDTH 16
+#define GMMx27E0_Reserved_31_16_MASK 0xffff0000
-/// GMMx2890
+/// GMMx27E0
typedef union {
struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 Lcl:8 ; ///<
+ UINT32 Hub:8 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2890_STRUCT;
+} GMMx27E0_STRUCT;
-// **** GMMx2894 Register Definition ****
+// **** GMMx2814 Register Definition ****
// Address
-#define GMMx2894_ADDRESS 0x2894
+#define GMMx2814_ADDRESS 0x2814
// Type
-#define GMMx2894_TYPE TYPE_GMM
+#define GMMx2814_TYPE TYPE_GMM
// Field Data
-#define GMMx2894_Def_OFFSET 0
-#define GMMx2894_Def_WIDTH 28
-#define GMMx2894_Def_MASK 0xfffffff
-#define GMMx2894_Reserved_31_28_OFFSET 28
-#define GMMx2894_Reserved_31_28_WIDTH 4
-#define GMMx2894_Reserved_31_28_MASK 0xf0000000
+#define GMMx2814_WriteClks_OFFSET 0
+#define GMMx2814_WriteClks_WIDTH 9
+#define GMMx2814_WriteClks_MASK 0x1ff
+#define GMMx2814_UvdHarshPriority_OFFSET 9
+#define GMMx2814_UvdHarshPriority_WIDTH 1
+#define GMMx2814_UvdHarshPriority_MASK 0x200
+#define GMMx2814_Reserved_31_10_OFFSET 10
+#define GMMx2814_Reserved_31_10_WIDTH 22
+#define GMMx2814_Reserved_31_10_MASK 0xfffffc00
-/// GMMx2894
+/// GMMx2814
typedef union {
struct { ///<
- UINT32 Def:28; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 WriteClks:9 ; ///<
+ UINT32 UvdHarshPriority:1 ; ///<
+ UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2894_STRUCT;
+} GMMx2814_STRUCT;
-// **** GMMx2898 Register Definition ****
+// **** GMMx281C Register Definition ****
// Address
-#define GMMx2898_ADDRESS 0x2898
+#define GMMx281C_ADDRESS 0x281c
// Type
-#define GMMx2898_TYPE TYPE_GMM
+#define GMMx281C_TYPE TYPE_GMM
// Field Data
-#define GMMx2898_Offset_OFFSET 0
-#define GMMx2898_Offset_WIDTH 20
-#define GMMx2898_Offset_MASK 0xfffff
-#define GMMx2898_Base_OFFSET 20
-#define GMMx2898_Base_WIDTH 4
-#define GMMx2898_Base_MASK 0xf00000
-#define GMMx2898_Top_OFFSET 24
-#define GMMx2898_Top_WIDTH 4
-#define GMMx2898_Top_MASK 0xf000000
-#define GMMx2898_Reserved_31_28_OFFSET 28
-#define GMMx2898_Reserved_31_28_WIDTH 4
-#define GMMx2898_Reserved_31_28_MASK 0xf0000000
+#define GMMx281C_CSEnable_OFFSET 0
+#define GMMx281C_CSEnable_WIDTH 1
+#define GMMx281C_CSEnable_MASK 0x1
+#define GMMx281C_Reserved_4_1_OFFSET 1
+#define GMMx281C_Reserved_4_1_WIDTH 4
+#define GMMx281C_Reserved_4_1_MASK 0x1e
+#define GMMx281C_BaseAddr_21_13__OFFSET 5
+#define GMMx281C_BaseAddr_21_13__WIDTH 9
+#define GMMx281C_BaseAddr_21_13__MASK 0x3fe0
+#define GMMx281C_Reserved_18_14_OFFSET 14
+#define GMMx281C_Reserved_18_14_WIDTH 5
+#define GMMx281C_Reserved_18_14_MASK 0x7c000
+#define GMMx281C_BaseAddr_35_27__OFFSET 19
+#define GMMx281C_BaseAddr_35_27__WIDTH 9
+#define GMMx281C_BaseAddr_35_27__MASK 0xff80000
+#define GMMx281C_Reserved_31_28_OFFSET 28
+#define GMMx281C_Reserved_31_28_WIDTH 4
+#define GMMx281C_Reserved_31_28_MASK 0xf0000000
-/// GMMx2898
+/// GMMx281C
typedef union {
struct { ///<
- UINT32 Offset:20; ///<
- UINT32 Base:4 ; ///<
- UINT32 Top:4 ; ///<
+ UINT32 CSEnable:1 ; ///<
+ UINT32 Reserved_4_1:4 ; ///<
+ UINT32 BaseAddr_21_13_:9 ; ///<
+ UINT32 Reserved_18_14:5 ; ///<
+ UINT32 BaseAddr_35_27_:9 ; ///<
UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2898_STRUCT;
+} GMMx281C_STRUCT;
-// **** GMMx28D8 Register Definition ****
+// **** GMMx2824 Register Definition ****
// Address
-#define GMMx28D8_ADDRESS 0x28d8
+#define GMMx2824_ADDRESS 0x2824
// Type
-#define GMMx28D8_TYPE TYPE_GMM
+#define GMMx2824_TYPE TYPE_GMM
// Field Data
-#define GMMx28D8_ActRd_OFFSET 0
-#define GMMx28D8_ActRd_WIDTH 8
-#define GMMx28D8_ActRd_MASK 0xff
-#define GMMx28D8_ActWr_OFFSET 8
-#define GMMx28D8_ActWr_WIDTH 8
-#define GMMx28D8_ActWr_MASK 0xff00
-#define GMMx28D8_RasMActRd_OFFSET 16
-#define GMMx28D8_RasMActRd_WIDTH 8
-#define GMMx28D8_RasMActRd_MASK 0xff0000
-#define GMMx28D8_RasMActWr_OFFSET 24
-#define GMMx28D8_RasMActWr_WIDTH 8
-#define GMMx28D8_RasMActWr_MASK 0xff000000
+#define GMMx2824_CSEnable_OFFSET 0
+#define GMMx2824_CSEnable_WIDTH 1
+#define GMMx2824_CSEnable_MASK 0x1
+#define GMMx2824_Reserved_4_1_OFFSET 1
+#define GMMx2824_Reserved_4_1_WIDTH 4
+#define GMMx2824_Reserved_4_1_MASK 0x1e
+#define GMMx2824_BaseAddr_21_13__OFFSET 5
+#define GMMx2824_BaseAddr_21_13__WIDTH 9
+#define GMMx2824_BaseAddr_21_13__MASK 0x3fe0
+#define GMMx2824_Reserved_18_14_OFFSET 14
+#define GMMx2824_Reserved_18_14_WIDTH 5
+#define GMMx2824_Reserved_18_14_MASK 0x7c000
+#define GMMx2824_BaseAddr_35_27__OFFSET 19
+#define GMMx2824_BaseAddr_35_27__WIDTH 9
+#define GMMx2824_BaseAddr_35_27__MASK 0xff80000
+#define GMMx2824_Reserved_31_28_OFFSET 28
+#define GMMx2824_Reserved_31_28_WIDTH 4
+#define GMMx2824_Reserved_31_28_MASK 0xf0000000
-/// GMMx28D8
+/// GMMx2824
typedef union {
struct { ///<
- UINT32 ActRd:8 ; ///<
- UINT32 ActWr:8 ; ///<
- UINT32 RasMActRd:8 ; ///<
- UINT32 RasMActWr:8 ; ///<
+ UINT32 CSEnable:1 ; ///<
+ UINT32 Reserved_4_1:4 ; ///<
+ UINT32 BaseAddr_21_13_:9 ; ///<
+ UINT32 Reserved_18_14:5 ; ///<
+ UINT32 BaseAddr_35_27_:9 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx28D8_STRUCT;
+} GMMx2824_STRUCT;
-// **** GMMx28DC Register Definition ****
+// **** GMMx282C Register Definition ****
// Address
-#define GMMx28DC_ADDRESS 0x28dc
+#define GMMx282C_ADDRESS 0x282c
// Type
-#define GMMx28DC_TYPE TYPE_GMM
+#define GMMx282C_TYPE TYPE_GMM
// Field Data
-#define GMMx28DC_Ras2Ras_OFFSET 0
-#define GMMx28DC_Ras2Ras_WIDTH 8
-#define GMMx28DC_Ras2Ras_MASK 0xff
-#define GMMx28DC_Rp_OFFSET 8
-#define GMMx28DC_Rp_WIDTH 8
-#define GMMx28DC_Rp_MASK 0xff00
-#define GMMx28DC_WrPlusRp_OFFSET 16
-#define GMMx28DC_WrPlusRp_WIDTH 8
-#define GMMx28DC_WrPlusRp_MASK 0xff0000
-#define GMMx28DC_BusTurn_OFFSET 24
-#define GMMx28DC_BusTurn_WIDTH 8
-#define GMMx28DC_BusTurn_MASK 0xff000000
+#define GMMx282C_CSEnable_OFFSET 0
+#define GMMx282C_CSEnable_WIDTH 1
+#define GMMx282C_CSEnable_MASK 0x1
+#define GMMx282C_Reserved_4_1_OFFSET 1
+#define GMMx282C_Reserved_4_1_WIDTH 4
+#define GMMx282C_Reserved_4_1_MASK 0x1e
+#define GMMx282C_BaseAddr_21_13__OFFSET 5
+#define GMMx282C_BaseAddr_21_13__WIDTH 9
+#define GMMx282C_BaseAddr_21_13__MASK 0x3fe0
+#define GMMx282C_Reserved_18_14_OFFSET 14
+#define GMMx282C_Reserved_18_14_WIDTH 5
+#define GMMx282C_Reserved_18_14_MASK 0x7c000
+#define GMMx282C_BaseAddr_35_27__OFFSET 19
+#define GMMx282C_BaseAddr_35_27__WIDTH 9
+#define GMMx282C_BaseAddr_35_27__MASK 0xff80000
+#define GMMx282C_Reserved_31_28_OFFSET 28
+#define GMMx282C_Reserved_31_28_WIDTH 4
+#define GMMx282C_Reserved_31_28_MASK 0xf0000000
-/// GMMx28DC
+/// GMMx282C
typedef union {
struct { ///<
- UINT32 Ras2Ras:8 ; ///<
- UINT32 Rp:8 ; ///<
- UINT32 WrPlusRp:8 ; ///<
- UINT32 BusTurn:8 ; ///<
+ UINT32 CSEnable:1 ; ///<
+ UINT32 Reserved_4_1:4 ; ///<
+ UINT32 BaseAddr_21_13_:9 ; ///<
+ UINT32 Reserved_18_14:5 ; ///<
+ UINT32 BaseAddr_35_27_:9 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx28DC_STRUCT;
+} GMMx282C_STRUCT;
-// **** GMMx2B8C Register Definition ****
+// **** GMMx2834 Register Definition ****
// Address
-#define GMMx2B8C_ADDRESS 0x2b8c
+#define GMMx2834_ADDRESS 0x2834
// Type
-#define GMMx2B8C_TYPE TYPE_GMM
+#define GMMx2834_TYPE TYPE_GMM
// Field Data
-#define GMMx2B8C_RengRamIndex_OFFSET 0
-#define GMMx2B8C_RengRamIndex_WIDTH 10
-#define GMMx2B8C_RengRamIndex_MASK 0x3ff
-#define GMMx2B8C_Reserved_31_10_OFFSET 10
-#define GMMx2B8C_Reserved_31_10_WIDTH 22
-#define GMMx2B8C_Reserved_31_10_MASK 0xfffffc00
+#define GMMx2834_CSEnable_OFFSET 0
+#define GMMx2834_CSEnable_WIDTH 1
+#define GMMx2834_CSEnable_MASK 0x1
+#define GMMx2834_Reserved_4_1_OFFSET 1
+#define GMMx2834_Reserved_4_1_WIDTH 4
+#define GMMx2834_Reserved_4_1_MASK 0x1e
+#define GMMx2834_BaseAddr_21_13__OFFSET 5
+#define GMMx2834_BaseAddr_21_13__WIDTH 9
+#define GMMx2834_BaseAddr_21_13__MASK 0x3fe0
+#define GMMx2834_Reserved_18_14_OFFSET 14
+#define GMMx2834_Reserved_18_14_WIDTH 5
+#define GMMx2834_Reserved_18_14_MASK 0x7c000
+#define GMMx2834_BaseAddr_35_27__OFFSET 19
+#define GMMx2834_BaseAddr_35_27__WIDTH 9
+#define GMMx2834_BaseAddr_35_27__MASK 0xff80000
+#define GMMx2834_Reserved_31_28_OFFSET 28
+#define GMMx2834_Reserved_31_28_WIDTH 4
+#define GMMx2834_Reserved_31_28_MASK 0xf0000000
-/// GMMx2B8C
+/// GMMx2834
typedef union {
struct { ///<
- UINT32 RengRamIndex:10; ///<
- UINT32 Reserved_31_10:22; ///<
+ UINT32 CSEnable:1 ; ///<
+ UINT32 Reserved_4_1:4 ; ///<
+ UINT32 BaseAddr_21_13_:9 ; ///<
+ UINT32 Reserved_18_14:5 ; ///<
+ UINT32 BaseAddr_35_27_:9 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2B8C_STRUCT;
+} GMMx2834_STRUCT;
-// **** GMMx2B90 Register Definition ****
+// **** GMMx283C Register Definition ****
// Address
-#define GMMx2B90_ADDRESS 0x2b90
+#define GMMx283C_ADDRESS 0x283c
// Type
-#define GMMx2B90_TYPE TYPE_GMM
+#define GMMx283C_TYPE TYPE_GMM
// Field Data
-#define GMMx2B90_RengRamData_OFFSET 0
-#define GMMx2B90_RengRamData_WIDTH 32
-#define GMMx2B90_RengRamData_MASK 0xffffffff
+#define GMMx283C_Reserved_4_0_OFFSET 0
+#define GMMx283C_Reserved_4_0_WIDTH 5
+#define GMMx283C_Reserved_4_0_MASK 0x1f
+#define GMMx283C_AddrMask_21_13__OFFSET 5
+#define GMMx283C_AddrMask_21_13__WIDTH 9
+#define GMMx283C_AddrMask_21_13__MASK 0x3fe0
+#define GMMx283C_Reserved_18_14_OFFSET 14
+#define GMMx283C_Reserved_18_14_WIDTH 5
+#define GMMx283C_Reserved_18_14_MASK 0x7c000
+#define GMMx283C_AddrMask_35_27__OFFSET 19
+#define GMMx283C_AddrMask_35_27__WIDTH 9
+#define GMMx283C_AddrMask_35_27__MASK 0xff80000
+#define GMMx283C_Reserved_28_28_OFFSET 28
+#define GMMx283C_Reserved_28_28_WIDTH 1
+#define GMMx283C_Reserved_28_28_MASK 0x10000000
+#define GMMx283C_Reserved_31_29_OFFSET 29
+#define GMMx283C_Reserved_31_29_WIDTH 3
+#define GMMx283C_Reserved_31_29_MASK 0xe0000000
-/// GMMx2B90
+/// GMMx283C
typedef union {
struct { ///<
- UINT32 RengRamData:32; ///<
+ UINT32 Reserved_4_0:5 ; ///<
+ UINT32 AddrMask_21_13_:9 ; ///<
+ UINT32 Reserved_18_14:5 ; ///<
+ UINT32 AddrMask_35_27_:9 ; ///<
+ UINT32 Reserved_28_28:1 ; ///<
+ UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2B90_STRUCT;
+} GMMx283C_STRUCT;
-// **** GMMx2C04 Register Definition ****
+// **** GMMx2840 Register Definition ****
// Address
-#define GMMx2C04_ADDRESS 0x2c04
+#define GMMx2840_ADDRESS 0x2840
// Type
-#define GMMx2C04_TYPE TYPE_GMM
+#define GMMx2840_TYPE TYPE_GMM
// Field Data
-#define GMMx2C04_NonsurfBase_OFFSET 0
-#define GMMx2C04_NonsurfBase_WIDTH 28
-#define GMMx2C04_NonsurfBase_MASK 0xfffffff
-#define GMMx2C04_Reserved_31_28_OFFSET 28
-#define GMMx2C04_Reserved_31_28_WIDTH 4
-#define GMMx2C04_Reserved_31_28_MASK 0xf0000000
+#define GMMx2840_Reserved_4_0_OFFSET 0
+#define GMMx2840_Reserved_4_0_WIDTH 5
+#define GMMx2840_Reserved_4_0_MASK 0x1f
+#define GMMx2840_AddrMask_21_13__OFFSET 5
+#define GMMx2840_AddrMask_21_13__WIDTH 9
+#define GMMx2840_AddrMask_21_13__MASK 0x3fe0
+#define GMMx2840_Reserved_18_14_OFFSET 14
+#define GMMx2840_Reserved_18_14_WIDTH 5
+#define GMMx2840_Reserved_18_14_MASK 0x7c000
+#define GMMx2840_AddrMask_35_27__OFFSET 19
+#define GMMx2840_AddrMask_35_27__WIDTH 9
+#define GMMx2840_AddrMask_35_27__MASK 0xff80000
+#define GMMx2840_Reserved_28_28_OFFSET 28
+#define GMMx2840_Reserved_28_28_WIDTH 1
+#define GMMx2840_Reserved_28_28_MASK 0x10000000
+#define GMMx2840_Reserved_31_29_OFFSET 29
+#define GMMx2840_Reserved_31_29_WIDTH 3
+#define GMMx2840_Reserved_31_29_MASK 0xe0000000
-/// GMMx2C04
+/// GMMx2840
typedef union {
struct { ///<
- UINT32 NonsurfBase:28; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 Reserved_4_0:5 ; ///<
+ UINT32 AddrMask_21_13_:9 ; ///<
+ UINT32 Reserved_18_14:5 ; ///<
+ UINT32 AddrMask_35_27_:9 ; ///<
+ UINT32 Reserved_28_28:1 ; ///<
+ UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx2C04_STRUCT;
+} GMMx2840_STRUCT;
-// **** GMMx5428 Register Definition ****
+// **** GMMx284C Register Definition ****
// Address
-#define GMMx5428_ADDRESS 0x5428
+#define GMMx284C_ADDRESS 0x284c
// Type
-#define GMMx5428_TYPE TYPE_GMM
+#define GMMx284C_TYPE TYPE_GMM
// Field Data
-#define GMMx5428_ConfigMemsize_OFFSET 0
-#define GMMx5428_ConfigMemsize_WIDTH 32
-#define GMMx5428_ConfigMemsize_MASK 0xffffffff
+#define GMMx284C_Dimm0AddrMap_OFFSET 0
+#define GMMx284C_Dimm0AddrMap_WIDTH 4
+#define GMMx284C_Dimm0AddrMap_MASK 0xf
+#define GMMx284C_Dimm1AddrMap_OFFSET 4
+#define GMMx284C_Dimm1AddrMap_WIDTH 4
+#define GMMx284C_Dimm1AddrMap_MASK 0xf0
+#define GMMx284C_Reserved_15_8_OFFSET 8
+#define GMMx284C_Reserved_15_8_WIDTH 8
+#define GMMx284C_Reserved_15_8_MASK 0xff00
+#define GMMx284C_BankSwizzleMode_OFFSET 16
+#define GMMx284C_BankSwizzleMode_WIDTH 1
+#define GMMx284C_BankSwizzleMode_MASK 0x10000
+#define GMMx284C_Reserved_18_17_OFFSET 17
+#define GMMx284C_Reserved_18_17_WIDTH 2
+#define GMMx284C_Reserved_18_17_MASK 0x60000
+#define GMMx284C_BankSwap_OFFSET 19
+#define GMMx284C_BankSwap_WIDTH 1
+#define GMMx284C_BankSwap_MASK 0x80000
+#define GMMx284C_Reserved_31_20_OFFSET 20
+#define GMMx284C_Reserved_31_20_WIDTH 12
+#define GMMx284C_Reserved_31_20_MASK 0xfff00000
-/// GMMx5428
+/// GMMx284C
typedef union {
struct { ///<
- UINT32 ConfigMemsize:32; ///<
+ UINT32 Dimm0AddrMap:4 ; ///<
+ UINT32 Dimm1AddrMap:4 ; ///<
+ UINT32 Reserved_15_8:8 ; ///<
+ UINT32 BankSwizzleMode:1 ; ///<
+ UINT32 Reserved_18_17:2 ; ///<
+ UINT32 BankSwap:1 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx5428_STRUCT;
+} GMMx284C_STRUCT;
-// **** GMMx5490 Register Definition ****
+// **** GMMx2858 Register Definition ****
// Address
-#define GMMx5490_ADDRESS 0x5490
+#define GMMx2858_ADDRESS 0x2858
// Type
-#define GMMx5490_TYPE TYPE_GMM
+#define GMMx2858_TYPE TYPE_GMM
// Field Data
-#define GMMx5490_FbReadEn_OFFSET 0
-#define GMMx5490_FbReadEn_WIDTH 1
-#define GMMx5490_FbReadEn_MASK 0x1
-#define GMMx5490_FbWriteEn_OFFSET 1
-#define GMMx5490_FbWriteEn_WIDTH 1
-#define GMMx5490_FbWriteEn_MASK 0x2
-#define GMMx5490_Reserved_31_2_OFFSET 2
-#define GMMx5490_Reserved_31_2_WIDTH 30
-#define GMMx5490_Reserved_31_2_MASK 0xfffffffc
+#define GMMx2858_Reserved_8_0_OFFSET 0
+#define GMMx2858_Reserved_8_0_WIDTH 9
+#define GMMx2858_Reserved_8_0_MASK 0x1ff
+#define GMMx2858_DctSelBankSwap_OFFSET 9
+#define GMMx2858_DctSelBankSwap_WIDTH 1
+#define GMMx2858_DctSelBankSwap_MASK 0x200
+#define GMMx2858_Reserved_31_10_OFFSET 10
+#define GMMx2858_Reserved_31_10_WIDTH 22
+#define GMMx2858_Reserved_31_10_MASK 0xfffffc00
-/// GMMx5490
+/// GMMx2858
typedef union {
struct { ///<
- UINT32 FbReadEn:1 ; ///<
- UINT32 FbWriteEn:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
+ UINT32 Reserved_8_0:9 ; ///<
+ UINT32 DctSelBankSwap:1 ; ///<
+ UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
-} GMMx5490_STRUCT;
+} GMMx2858_STRUCT;
-// **** SMUx03 Register Definition ****
+// **** GMMx285C Register Definition ****
// Address
-#define SMUx03_ADDRESS 0x3
+#define GMMx285C_ADDRESS 0x285c
// Type
-#define SMUx03_TYPE TYPE_SMU
+#define GMMx285C_TYPE TYPE_GMM
// Field Data
-#define SMUx03_IntReq_OFFSET 0
-#define SMUx03_IntReq_WIDTH 1
-#define SMUx03_IntReq_MASK 0x1
-#define SMUx03_IntAck_OFFSET 1
-#define SMUx03_IntAck_WIDTH 1
-#define SMUx03_IntAck_MASK 0x2
-#define SMUx03_IntDone_OFFSET 2
-#define SMUx03_IntDone_WIDTH 1
-#define SMUx03_IntDone_MASK 0x4
-#define SMUx03_ServiceIndex_OFFSET 3
-#define SMUx03_ServiceIndex_WIDTH 8
-#define SMUx03_ServiceIndex_MASK 0x7f8
-#define SMUx03_Reserved_31_11_OFFSET 11
-#define SMUx03_Reserved_31_11_WIDTH 21
-#define SMUx03_Reserved_31_11_MASK 0xfffff800
+#define GMMx285C_DramHoleValid_OFFSET 0
+#define GMMx285C_DramHoleValid_WIDTH 1
+#define GMMx285C_DramHoleValid_MASK 0x1
+#define GMMx285C_Reserved_6_1_OFFSET 1
+#define GMMx285C_Reserved_6_1_WIDTH 6
+#define GMMx285C_Reserved_6_1_MASK 0x7e
+#define GMMx285C_DramHoleOffset_31_23__OFFSET 7
+#define GMMx285C_DramHoleOffset_31_23__WIDTH 9
+#define GMMx285C_DramHoleOffset_31_23__MASK 0xff80
+#define GMMx285C_Reserved_23_16_OFFSET 16
+#define GMMx285C_Reserved_23_16_WIDTH 8
+#define GMMx285C_Reserved_23_16_MASK 0xff0000
+#define GMMx285C_DramHoleBase_31_24__OFFSET 24
+#define GMMx285C_DramHoleBase_31_24__WIDTH 8
+#define GMMx285C_DramHoleBase_31_24__MASK 0xff000000
-/// SMUx03
+/// GMMx285C
typedef union {
struct { ///<
- UINT32 IntReq:1 ; ///<
- UINT32 IntAck:1 ; ///<
- UINT32 IntDone:1 ; ///<
- UINT32 ServiceIndex:8 ; ///<
- UINT32 Reserved_31_11:21; ///<
+ UINT32 DramHoleValid:1 ; ///<
+ UINT32 Reserved_6_1:6 ; ///<
+ UINT32 DramHoleOffset_31_23_:9 ; ///<
+ UINT32 Reserved_23_16:8 ; ///<
+ UINT32 DramHoleBase_31_24_:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx03_STRUCT;
+} GMMx285C_STRUCT;
-// **** SMUx05 Register Definition ****
+// **** GMMx2864 Register Definition ****
// Address
-#define SMUx05_ADDRESS 0x5
+#define GMMx2864_ADDRESS 0x2864
// Type
-#define SMUx05_TYPE TYPE_SMU
+#define GMMx2864_TYPE TYPE_GMM
// Field Data
-#define SMUx05_McuRam_OFFSET 0
-#define SMUx05_McuRam_WIDTH 32
-#define SMUx05_McuRam_MASK 0xffffffff
+#define GMMx2864_A8Map_OFFSET 0
+#define GMMx2864_A8Map_WIDTH 4
+#define GMMx2864_A8Map_MASK 0xf
+#define GMMx2864_A9Map_OFFSET 4
+#define GMMx2864_A9Map_WIDTH 4
+#define GMMx2864_A9Map_MASK 0xf0
+#define GMMx2864_A10Map_OFFSET 8
+#define GMMx2864_A10Map_WIDTH 4
+#define GMMx2864_A10Map_MASK 0xf00
+#define GMMx2864_A11Map_OFFSET 12
+#define GMMx2864_A11Map_WIDTH 4
+#define GMMx2864_A11Map_MASK 0xf000
+#define GMMx2864_A12Map_OFFSET 16
+#define GMMx2864_A12Map_WIDTH 4
+#define GMMx2864_A12Map_MASK 0xf0000
+#define GMMx2864_A13Map_OFFSET 20
+#define GMMx2864_A13Map_WIDTH 4
+#define GMMx2864_A13Map_MASK 0xf00000
+#define GMMx2864_A14Map_OFFSET 24
+#define GMMx2864_A14Map_WIDTH 4
+#define GMMx2864_A14Map_MASK 0xf000000
+#define GMMx2864_A15Map_OFFSET 28
+#define GMMx2864_A15Map_WIDTH 4
+#define GMMx2864_A15Map_MASK 0xf0000000
-/// SMUx05
+/// GMMx2864
typedef union {
struct { ///<
- UINT32 McuRam:32; ///<
+ UINT32 A8Map:4 ; ///<
+ UINT32 A9Map:4 ; ///<
+ UINT32 A10Map:4 ; ///<
+ UINT32 A11Map:4 ; ///<
+ UINT32 A12Map:4 ; ///<
+ UINT32 A13Map:4 ; ///<
+ UINT32 A14Map:4 ; ///<
+ UINT32 A15Map:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx05_STRUCT;
+} GMMx2864_STRUCT;
-// **** SMUx0B Register Definition ****
+// **** GMMx286C Register Definition ****
// Address
-#define SMUx0B_ADDRESS 0xb
+#define GMMx286C_ADDRESS 0x286c
// Type
-#define SMUx0B_TYPE TYPE_SMU
+#define GMMx286C_TYPE TYPE_GMM
// Field Data
-#define SMUx0B_MemAddr_OFFSET 0
-#define SMUx0B_MemAddr_WIDTH 16
-#define SMUx0B_MemAddr_MASK 0xffff
+#define GMMx286C_Base_OFFSET 0
+#define GMMx286C_Base_WIDTH 20
+#define GMMx286C_Base_MASK 0xfffff
+#define GMMx286C_Reserved_31_20_OFFSET 20
+#define GMMx286C_Reserved_31_20_WIDTH 12
+#define GMMx286C_Reserved_31_20_MASK 0xfff00000
-/// SMUx0B
+/// GMMx286C
typedef union {
struct { ///<
- UINT32 MemAddr:16; ///<
+ UINT32 Base:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx0B_STRUCT;
+} GMMx286C_STRUCT;
-// **** MSRC001_001A Register Definition ****
+// **** GMMx2870 Register Definition ****
// Address
-#define MSRC001_001A_ADDRESS 0xc001001a
+#define GMMx2870_ADDRESS 0x2870
// Type
-#define MSRC001_001A_TYPE TYPE_MSR
+#define GMMx2870_TYPE TYPE_GMM
// Field Data
-#define MSRC001_001A_RAZ_22_0_OFFSET 0
-#define MSRC001_001A_RAZ_22_0_WIDTH 23
-#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff
-#define MSRC001_001A_TOM_35_23__OFFSET 23
-#define MSRC001_001A_TOM_35_23__WIDTH 13
-#define MSRC001_001A_TOM_35_23__MASK 0xfff800000
-#define MSRC001_001A_RAZ_63_36_OFFSET 36
-#define MSRC001_001A_RAZ_63_36_WIDTH 28
-#define MSRC001_001A_RAZ_63_36_MASK 0xfffffff000000000
+#define GMMx2870_Base_OFFSET 0
+#define GMMx2870_Base_WIDTH 20
+#define GMMx2870_Base_MASK 0xfffff
+#define GMMx2870_Reserved_31_20_OFFSET 20
+#define GMMx2870_Reserved_31_20_WIDTH 12
+#define GMMx2870_Reserved_31_20_MASK 0xfff00000
-/// MSRC001_001A
+/// GMMx2870
typedef union {
struct { ///<
- UINT64 RAZ_22_0:23; ///<
- UINT64 TOM_35_23_:13; ///<
- UINT64 RAZ_63_36:28; ///<
+ UINT32 Base:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
- UINT64 Value; ///<
-} MSRC001_001A_STRUCT;
-
-
-// **** FCRxFF30_0AE6(GMMx2B98) Register Definition ****
-// Address
-#define FCRxFF30_0AE6_ADDRESS 0xff300AE6
-
-// Field Data
-#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0
-#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10
-#define FCRxFF30_0AE6_RengExecuteNowMode_OFFSET 10
-#define FCRxFF30_0AE6_RengExecuteNowMode_WIDTH 1
-#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11
-#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1
-#define FCRxFF30_0AE6_RengSrbmCreditsMcd_OFFSET 12
-#define FCRxFF30_0AE6_RengSrbmCreditsMcd_WIDTH 4
-#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16
-#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1
-#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_OFFSET 17
-#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_WIDTH 2
-#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_OFFSET 19
-#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_WIDTH 2
-#define FCRxFF30_0AE6_StctrlIgnorePreSr_OFFSET 21
-#define FCRxFF30_0AE6_StctrlIgnorePreSr_WIDTH 1
-#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_OFFSET 22
-#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_WIDTH 1
-#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_OFFSET 23
-#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_WIDTH 1
-#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24
-#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1
-#define FCRxFF30_0AE6_StctrlDisableAllowSr_OFFSET 25
-#define FCRxFF30_0AE6_StctrlDisableAllowSr_WIDTH 1
-#define FCRxFF30_0AE6_StctrlDisableGmcOffline_OFFSET 26
-#define FCRxFF30_0AE6_StctrlDisableGmcOffline_WIDTH 1
-#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27
-#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1
-#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_OFFSET 28
-#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_WIDTH 1
-#define FCRxFF30_0AE6_AllowDeepSleepMode_OFFSET 29
-#define FCRxFF30_0AE6_AllowDeepSleepMode_WIDTH 2
-#define FCRxFF30_0AE6_Reserved_31_31_OFFSET 31
-#define FCRxFF30_0AE6_Reserved_31_31_WIDTH 1
-
-/// FCRxFF30_0AE6
-typedef union {
- struct { ///<
- UINT32 RengExecuteNonsecureStartPtr:10; ///<
- UINT32 RengExecuteNowMode:1 ; ///<
- UINT32 RengExecuteOnRegUpdate:1 ; ///<
- UINT32 RengSrbmCreditsMcd:4 ; ///<
- UINT32 StctrlStutterEn:1 ; ///<
- UINT32 StctrlGmcIdleThreshold:2 ; ///<
- UINT32 StctrlSrbmIdleThreshold:2 ; ///<
- UINT32 StctrlIgnorePreSr:1 ; ///<
- UINT32 StctrlIgnoreAllowStop:1 ; ///<
- UINT32 StctrlIgnoreDramOffline:1 ; ///<
- UINT32 StctrlIgnoreProtectionFault:1 ; ///<
- UINT32 StctrlDisableAllowSr:1 ; ///<
- UINT32 StctrlDisableGmcOffline:1 ; ///<
- UINT32 CriticalRegsLock:1 ; ///<
- UINT32 SmuExecuteOnRegUpdate:1 ; ///<
- UINT32 AllowDeepSleepMode:2 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field;
- UINT32 Value;
-} FCRxFF30_0AE6_STRUCT;
+ UINT32 Value; ///<
+} GMMx2870_STRUCT;
-// **** FCRxFF30_0134(GMMx4D0) Register Definition ****
+// **** GMMx2874 Register Definition ****
// Address
-#define FCRxFF30_0134_ADDRESS 0xff300134
+#define GMMx2874_ADDRESS 0x2874
+// Type
+#define GMMx2874_TYPE TYPE_GMM
// Field Data
-#define FCRxFF30_0134_DispclkDccgGateDisable_OFFSET 0
-#define FCRxFF30_0134_DispclkDccgGateDisable_WIDTH 1
-#define FCRxFF30_0134_DispclkDccgGateDisable_MASK 0x1
-#define FCRxFF30_0134_DispclkRDccgGateDisable_OFFSET 1
-#define FCRxFF30_0134_DispclkRDccgGateDisable_WIDTH 1
-#define FCRxFF30_0134_DispclkRDccgGateDisable_MASK 0x2
-#define FCRxFF30_0134_SclkGateDisable_OFFSET 2
-#define FCRxFF30_0134_SclkGateDisable_WIDTH 1
-#define FCRxFF30_0134_SclkGateDisable_MASK 0x4
-#define FCRxFF30_0134_Reserved_7_3_OFFSET 3
-#define FCRxFF30_0134_Reserved_7_3_WIDTH 5
-#define FCRxFF30_0134_Reserved_7_3_MASK 0xf8
-#define FCRxFF30_0134_SymclkaGateDisable_OFFSET 8
-#define FCRxFF30_0134_SymclkaGateDisable_WIDTH 1
-#define FCRxFF30_0134_SymclkaGateDisable_MASK 0x100
-#define FCRxFF30_0134_SymclkbGateDisable_OFFSET 9
-#define FCRxFF30_0134_SymclkbGateDisable_WIDTH 1
-#define FCRxFF30_0134_SymclkbGateDisable_MASK 0x200
-#define FCRxFF30_0134_Reserved_31_10_OFFSET 10
-#define FCRxFF30_0134_Reserved_31_10_WIDTH 22
-#define FCRxFF30_0134_Reserved_31_10_MASK 0xfffffc00
+#define GMMx2874_Base_OFFSET 0
+#define GMMx2874_Base_WIDTH 20
+#define GMMx2874_Base_MASK 0xfffff
+#define GMMx2874_Reserved_31_20_OFFSET 20
+#define GMMx2874_Reserved_31_20_WIDTH 12
+#define GMMx2874_Reserved_31_20_MASK 0xfff00000
-/// FCRxFF30_0134
+/// GMMx2874
typedef union {
struct { ///<
- UINT32 DispclkDccgGateDisable:1 ; ///<
- UINT32 DispclkRDccgGateDisable:1 ; ///<
- UINT32 SclkGateDisable:1 ; ///<
- UINT32 Reserved_7_3:5 ; ///<
- UINT32 SymclkaGateDisable:1 ; ///<
- UINT32 SymclkbGateDisable:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
+ UINT32 Base:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_0134_STRUCT;
+} GMMx2874_STRUCT;
-// **** FCRxFF30_1B7C(GMMx6DF0) Register Definition ****
+// **** GMMx2878 Register Definition ****
// Address
-#define FCRxFF30_1B7C_ADDRESS 0xff301B7C
+#define GMMx2878_ADDRESS 0x2878
+// Type
+#define GMMx2878_TYPE TYPE_GMM
// Field Data
-#define FCRxFF30_1B7C_Reserved_3_0_OFFSET 0
-#define FCRxFF30_1B7C_Reserved_3_0_WIDTH 4
-#define FCRxFF30_1B7C_Reserved_3_0_MASK 0xf
-#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_OFFSET 4
-#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_WIDTH 1
-#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_MASK 0x10
-#define FCRxFF30_1B7C_Reserved_7_5_OFFSET 5
-#define FCRxFF30_1B7C_Reserved_7_5_WIDTH 3
-#define FCRxFF30_1B7C_Reserved_7_5_MASK 0xe0
-#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_OFFSET 8
-#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_WIDTH 1
-#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_MASK 0x100
-#define FCRxFF30_1B7C_Reserved_11_9_OFFSET 9
-#define FCRxFF30_1B7C_Reserved_11_9_WIDTH 3
-#define FCRxFF30_1B7C_Reserved_11_9_MASK 0xe00
-#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_OFFSET 12
-#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_WIDTH 1
-#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_MASK 0x1000
-#define FCRxFF30_1B7C_Reserved_31_13_OFFSET 13
-#define FCRxFF30_1B7C_Reserved_31_13_WIDTH 19
-#define FCRxFF30_1B7C_Reserved_31_13_MASK 0xffffe000
+#define GMMx2878_Base_OFFSET 0
+#define GMMx2878_Base_WIDTH 20
+#define GMMx2878_Base_MASK 0xfffff
+#define GMMx2878_Reserved_31_20_OFFSET 20
+#define GMMx2878_Reserved_31_20_WIDTH 12
+#define GMMx2878_Reserved_31_20_MASK 0xfff00000
-/// FCRxFF30_1B7C
+/// GMMx2878
typedef union {
struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///<
- UINT32 Reserved_7_5:3 ; ///<
- UINT32 CrtcDispclkGDcpGateDisable:1 ; ///<
- UINT32 Reserved_11_9:3 ; ///<
- UINT32 CrtcDispclkGSclGateDisable:1 ; ///<
- UINT32 Reserved_31_13:19; ///<
+ UINT32 Base:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_1B7C_STRUCT;
+} GMMx2878_STRUCT;
-// **** FCRxFF30_1E7C(GMMx79F0) Register Definition ****
+// **** GMMx287C Register Definition ****
// Address
-#define FCRxFF30_1E7C_ADDRESS 0xff301E7C
+#define GMMx287C_ADDRESS 0x287c
+// Type
+#define GMMx287C_TYPE TYPE_GMM
// Field Data
-#define FCRxFF30_1E7C_Reserved_3_0_OFFSET 0
-#define FCRxFF30_1E7C_Reserved_3_0_WIDTH 4
-#define FCRxFF30_1E7C_Reserved_3_0_MASK 0xf
-#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_OFFSET 4
-#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_WIDTH 1
-#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_MASK 0x10
-#define FCRxFF30_1E7C_Reserved_7_5_OFFSET 5
-#define FCRxFF30_1E7C_Reserved_7_5_WIDTH 3
-#define FCRxFF30_1E7C_Reserved_7_5_MASK 0xe0
-#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_OFFSET 8
-#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_WIDTH 1
-#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_MASK 0x100
-#define FCRxFF30_1E7C_Reserved_11_9_OFFSET 9
-#define FCRxFF30_1E7C_Reserved_11_9_WIDTH 3
-#define FCRxFF30_1E7C_Reserved_11_9_MASK 0xe00
-#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_OFFSET 12
-#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_WIDTH 1
-#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_MASK 0x1000
-#define FCRxFF30_1E7C_Reserved_31_13_OFFSET 13
-#define FCRxFF30_1E7C_Reserved_31_13_WIDTH 19
-#define FCRxFF30_1E7C_Reserved_31_13_MASK 0xffffe000
+#define GMMx287C_Top_OFFSET 0
+#define GMMx287C_Top_WIDTH 20
+#define GMMx287C_Top_MASK 0xfffff
+#define GMMx287C_Reserved_31_20_OFFSET 20
+#define GMMx287C_Reserved_31_20_WIDTH 12
+#define GMMx287C_Reserved_31_20_MASK 0xfff00000
-/// FCRxFF30_1E7C
+/// GMMx287C
typedef union {
struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///<
- UINT32 Reserved_7_5:3 ; ///<
- UINT32 CrtcDispclkGDcpGateDisable:1 ; ///<
- UINT32 Reserved_11_9:3 ; ///<
- UINT32 CrtcDispclkGSclGateDisable:1 ; ///<
- UINT32 Reserved_31_13:19; ///<
+ UINT32 Top:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_1E7C_STRUCT;
+} GMMx287C_STRUCT;
-// **** FCRxFE00_600E Register Definition ****
+// **** GMMx2880 Register Definition ****
// Address
-#define FCRxFE00_600E_ADDRESS 0xfe00600e
+#define GMMx2880_ADDRESS 0x2880
+// Type
+#define GMMx2880_TYPE TYPE_GMM
// Field Data
-#define FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET 0
-#define FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH 6
-#define FCRxFE00_600E_WrCkDid_OFFSET 10
-#define FCRxFE00_600E_WrCkDid_WIDTH 5
+#define GMMx2880_Top_OFFSET 0
+#define GMMx2880_Top_WIDTH 20
+#define GMMx2880_Top_MASK 0xfffff
+#define GMMx2880_Reserved_31_20_OFFSET 20
+#define GMMx2880_Reserved_31_20_WIDTH 12
+#define GMMx2880_Reserved_31_20_MASK 0xfff00000
-/// FCRxFE00_600E
+/// GMMx2880
typedef union {
- struct {
- UINT32 MainPllOpFreqIdStartup:6 ; ///<
- UINT32 Reserved:5 ; ///<
- UINT32 WrCkDid:5 ; ///<
- } Field;
- UINT32 Value;
-} FCRxFE00_600E_STRUCT;
+ struct { ///<
+ UINT32 Top:20; ///<
+ UINT32 Reserved_31_20:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx2880_STRUCT;
-// **** SMUx0B_x8498 Register Definition ****
+// **** GMMx2884 Register Definition ****
// Address
-#define SMUx0B_x8498_ADDRESS 0x8498
+#define GMMx2884_ADDRESS 0x2884
+// Type
+#define GMMx2884_TYPE TYPE_GMM
// Field Data
-#define SMUx0B_x8498_ConditionalBF_1_0_OFFSET 0
-#define SMUx0B_x8498_ConditionalBF_1_0_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_1_0_MASK 0x3
-#define SMUx0B_x8498_ConditionalBF_3_2_OFFSET 2
-#define SMUx0B_x8498_ConditionalBF_3_2_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_3_2_MASK 0xc
-#define SMUx0B_x8498_Reserved_7_4_OFFSET 4
-#define SMUx0B_x8498_Reserved_7_4_WIDTH 4
-#define SMUx0B_x8498_Reserved_7_4_MASK 0xf0
-#define SMUx0B_x8498_ConditionalBF_9_8_OFFSET 8
-#define SMUx0B_x8498_ConditionalBF_9_8_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_9_8_MASK 0x300
-#define SMUx0B_x8498_ConditionalBF_11_10_OFFSET 10
-#define SMUx0B_x8498_ConditionalBF_11_10_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_11_10_MASK 0xc00
-#define SMUx0B_x8498_Reserved_15_12_OFFSET 12
-#define SMUx0B_x8498_Reserved_15_12_WIDTH 4
-#define SMUx0B_x8498_Reserved_15_12_MASK 0xf000
-#define SMUx0B_x8498_BaseVid_5_OFFSET 16
-#define SMUx0B_x8498_BaseVid_5_WIDTH 2
-#define SMUx0B_x8498_BaseVid_5_MASK 0x30000
-#define SMUx0B_x8498_TolExcdVid_5_OFFSET 18
-#define SMUx0B_x8498_TolExcdVid_5_WIDTH 2
-#define SMUx0B_x8498_TolExcdVid_5_MASK 0xc0000
-#define SMUx0B_x8498_Reserved_23_20_OFFSET 20
-#define SMUx0B_x8498_Reserved_23_20_WIDTH 4
-#define SMUx0B_x8498_Reserved_23_20_MASK 0xf00000
-#define SMUx0B_x8498_BaseVid_4_OFFSET 24
-#define SMUx0B_x8498_BaseVid_4_WIDTH 2
-#define SMUx0B_x8498_BaseVid_4_MASK 0x3000000
-#define SMUx0B_x8498_TolExcdVid_4_OFFSET 26
-#define SMUx0B_x8498_TolExcdVid_4_WIDTH 2
-#define SMUx0B_x8498_TolExcdVid_4_MASK 0xc000000
-#define SMUx0B_x8498_Reserved_31_28_OFFSET 28
-#define SMUx0B_x8498_Reserved_31_28_WIDTH 4
-#define SMUx0B_x8498_Reserved_31_28_MASK 0xf0000000
+#define GMMx2884_Top_OFFSET 0
+#define GMMx2884_Top_WIDTH 20
+#define GMMx2884_Top_MASK 0xfffff
+#define GMMx2884_Reserved_31_20_OFFSET 20
+#define GMMx2884_Reserved_31_20_WIDTH 12
+#define GMMx2884_Reserved_31_20_MASK 0xfff00000
-/// SMUx0B_x8498
+/// GMMx2884
typedef union {
struct { ///<
- UINT32 ConditionalBF_1_0:2 ; ///<
- UINT32 ConditionalBF_3_2:2 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 ConditionalBF_9_8:2 ; ///<
- UINT32 ConditionalBF_11_10:2 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 BaseVid_5:2 ; ///<
- UINT32 TolExcdVid_5:2 ; ///<
- UINT32 Reserved_23_20:4 ; ///<
- UINT32 BaseVid_4:2 ; ///<
- UINT32 TolExcdVid_4:2 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
+ UINT32 Top:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx0B_x8498_STRUCT;
+} GMMx2884_STRUCT;
-// **** D0F0xE4_WRAP_8013 Register Definition ****
+// **** GMMx2888 Register Definition ****
// Address
-#define D0F0xE4_WRAP_8013_ADDRESS 0x8013
+#define GMMx2888_ADDRESS 0x2888
+// Type
+#define GMMx2888_TYPE TYPE_GMM
// Field Data
-#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0
-#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1
-#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1
-#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1
-#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2
-#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2
-#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4
-#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3
-#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8
-#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4
-#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1
-#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10
-#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5
-#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20
-#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6
-#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40
-#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7
-#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80
-#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8
-#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1
-#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100
-#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9
-#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1
-#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200
-#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10
-#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400
-#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11
-#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800
-#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12
-#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000
-#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13
-#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3
-#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000
-#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16
-#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000
-#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17
-#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3
-#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000
-#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20
-#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000
-#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21
-#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11
-#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000
+#define GMMx2888_Top_OFFSET 0
+#define GMMx2888_Top_WIDTH 20
+#define GMMx2888_Top_MASK 0xfffff
+#define GMMx2888_Reserved_31_20_OFFSET 20
+#define GMMx2888_Reserved_31_20_WIDTH 12
+#define GMMx2888_Reserved_31_20_MASK 0xfff00000
-/// D0F0xE4_WRAP_8013
+/// GMMx2888
typedef union {
struct { ///<
- UINT32 MasterPciePllA:1 ; ///<
- UINT32 MasterPciePllB:1 ; ///<
- UINT32 MasterPciePllC:1 ; ///<
- UINT32 MasterPciePllD:1 ; ///<
- UINT32 ClkDividerResetOverrideA:1 ; ///<
- UINT32 Reserved_5_5:1 ; ///<
- UINT32 Reserved_6_6:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 TxclkSelCoreOverride:1 ; ///<
- UINT32 TxclkSelPifAOverride:1 ; ///<
- UINT32 Reserved_10_10:1 ; ///<
- UINT32 Reserved_11_11:1 ; ///<
- UINT32 Reserved_12_12:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 Reserved_16_16:1 ; ///<
- UINT32 Reserved_19_17:3 ; ///<
- UINT32 Reserved_20_20:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
+ UINT32 Top:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_8013_STRUCT;
+} GMMx2888_STRUCT;
-// **** D0F0xE4_WRAP_8014 Register Definition ****
+// **** GMMx288C Register Definition ****
// Address
-#define D0F0xE4_WRAP_8014_ADDRESS 0x8014
+#define GMMx288C_ADDRESS 0x288c
+// Type
+#define GMMx288C_TYPE TYPE_GMM
// Field Data
-#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0
-#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1
-#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1
-#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2
-#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2
-#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4
-#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3
-#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8
-#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4
-#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10
-#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5
-#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20
-#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6
-#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40
-#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7
-#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80
-#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8
-#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100
-#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9
-#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200
-#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10
-#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400
-#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11
-#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800
-#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12
-#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000
-#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13
-#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000
-#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14
-#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000
-#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15
-#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000
-#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16
-#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000
-#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17
-#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000
-#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18
-#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000
-#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19
-#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000
-#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20
-#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1
-#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000
-#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21
-#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11
-#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000
+#define GMMx288C_Base_OFFSET 0
+#define GMMx288C_Base_WIDTH 20
+#define GMMx288C_Base_MASK 0xfffff
+#define GMMx288C_Reserved_31_20_OFFSET 20
+#define GMMx288C_Reserved_31_20_WIDTH 12
+#define GMMx288C_Reserved_31_20_MASK 0xfff00000
-/// D0F0xE4_WRAP_8014
+/// GMMx288C
typedef union {
- struct {
- UINT32 TxclkPermGateEnable:1 ; ///<
- UINT32 TxclkPrbsGateEnable:1 ; ///<
- UINT32 DdiGatePifA1xEnable:1 ; ///<
- UINT32 DdiGatePifB1xEnable:1 ; ///<
- UINT32 DdiGatePifC1xEnable:1 ; ///<
- UINT32 DdiGatePifD1xEnable:1 ; ///<
- UINT32 DdiGateDigAEnable:1 ; ///<
- UINT32 DdiGateDigBEnable:1 ; ///<
- UINT32 DdiGatePifA2p5xEnable:1 ; ///<
- UINT32 DdiGatePifB2p5xEnable:1 ; ///<
- UINT32 DdiGatePifC2p5xEnable:1 ; ///<
- UINT32 DdiGatePifD2p5xEnable:1 ; ///<
- UINT32 PcieGatePifA1xEnable:1 ; ///<
- UINT32 PcieGatePifB1xEnable:1 ; ///<
- UINT32 PcieGatePifC1xEnable:1 ; ///<
- UINT32 PcieGatePifD1xEnable:1 ; ///<
- UINT32 PcieGatePifA2p5xEnable:1 ; ///<
- UINT32 PcieGatePifB2p5xEnable:1 ; ///<
- UINT32 PcieGatePifC2p5xEnable:1 ; ///<
- UINT32 PcieGatePifD2p5xEnable:1 ; ///<
- UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
+ struct { ///<
+ UINT32 Base:20; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_8014_STRUCT;
+} GMMx288C_STRUCT;
-// **** SMUx0B_x85B0 Register Definition ****
+// **** GMMx2890 Register Definition ****
// Address
-#define SMUx0B_x85B0_ADDRESS 0x85B0
+#define GMMx2890_ADDRESS 0x2890
+// Type
+#define GMMx2890_TYPE TYPE_GMM
+// Field Data
+#define GMMx2890_Top_OFFSET 0
+#define GMMx2890_Top_WIDTH 20
+#define GMMx2890_Top_MASK 0xfffff
+#define GMMx2890_Reserved_31_20_OFFSET 20
+#define GMMx2890_Reserved_31_20_WIDTH 12
+#define GMMx2890_Reserved_31_20_MASK 0xfff00000
-// **** SMUx0B_x85D0 Register Definition ****
+/// GMMx2890
+typedef union {
+ struct { ///<
+ UINT32 Top:20; ///<
+ UINT32 Reserved_31_20:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx2890_STRUCT;
+
+// **** GMMx2894 Register Definition ****
// Address
-#define SMUx0B_x85D0_ADDRESS 0x85D0
+#define GMMx2894_ADDRESS 0x2894
-// **** D0F0x64_x51 Register Definition ****
+// Type
+#define GMMx2894_TYPE TYPE_GMM
+// Field Data
+#define GMMx2894_Def_OFFSET 0
+#define GMMx2894_Def_WIDTH 28
+#define GMMx2894_Def_MASK 0xfffffff
+#define GMMx2894_Reserved_31_28_OFFSET 28
+#define GMMx2894_Reserved_31_28_WIDTH 4
+#define GMMx2894_Reserved_31_28_MASK 0xf0000000
+
+/// GMMx2894
+typedef union {
+ struct { ///<
+ UINT32 Def:28; ///<
+ UINT32 Reserved_31_28:4 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx2894_STRUCT;
+
+// **** GMMx2898 Register Definition ****
// Address
-#define D0F0x64_x51_ADDRESS 0x51
+#define GMMx2898_ADDRESS 0x2898
// Type
-#define D0F0x64_x51_TYPE TYPE_D0F0x64
+#define GMMx2898_TYPE TYPE_GMM
// Field Data
-#define D0F0x64_x51_Reserved_2_0_OFFSET 0
-#define D0F0x64_x51_Reserved_2_0_WIDTH 3
-#define D0F0x64_x51_Reserved_2_0_MASK 0x7
-#define D0F0x64_x51_P2pDis_OFFSET 3
-#define D0F0x64_x51_P2pDis_WIDTH 1
-#define D0F0x64_x51_P2pDis_MASK 0x8
-#define D0F0x64_x51_Reserved_15_4_OFFSET 4
-#define D0F0x64_x51_Reserved_15_4_WIDTH 12
-#define D0F0x64_x51_Reserved_15_4_MASK 0xfff0
-#define D0F0x64_x51_ExtDevPlug_OFFSET 16
-#define D0F0x64_x51_ExtDevPlug_WIDTH 1
-#define D0F0x64_x51_ExtDevPlug_MASK 0x10000
-#define D0F0x64_x51_ExtDevCrsEn_OFFSET 17
-#define D0F0x64_x51_ExtDevCrsEn_WIDTH 1
-#define D0F0x64_x51_ExtDevCrsEn_MASK 0x20000
-#define D0F0x64_x51_CrsEn_OFFSET 18
-#define D0F0x64_x51_CrsEn_WIDTH 1
-#define D0F0x64_x51_CrsEn_MASK 0x40000
-#define D0F0x64_x51_IntSelMode_OFFSET 19
-#define D0F0x64_x51_IntSelMode_WIDTH 1
-#define D0F0x64_x51_IntSelMode_MASK 0x80000
-#define D0F0x64_x51_SetPowEn_OFFSET 20
-#define D0F0x64_x51_SetPowEn_WIDTH 1
-#define D0F0x64_x51_SetPowEn_MASK 0x100000
-#define D0F0x64_x51_Reserved_31_21_OFFSET 21
-#define D0F0x64_x51_Reserved_31_21_WIDTH 11
-#define D0F0x64_x51_Reserved_31_21_MASK 0xffe00000
+#define GMMx2898_Offset_OFFSET 0
+#define GMMx2898_Offset_WIDTH 20
+#define GMMx2898_Offset_MASK 0xfffff
+#define GMMx2898_Base_OFFSET 20
+#define GMMx2898_Base_WIDTH 4
+#define GMMx2898_Base_MASK 0xf00000
+#define GMMx2898_Top_OFFSET 24
+#define GMMx2898_Top_WIDTH 4
+#define GMMx2898_Top_MASK 0xf000000
+#define GMMx2898_Reserved_31_28_OFFSET 28
+#define GMMx2898_Reserved_31_28_WIDTH 4
+#define GMMx2898_Reserved_31_28_MASK 0xf0000000
-/// D0F0x64_x51
+/// GMMx2898
typedef union {
struct { ///<
- UINT32 Reserved_2_0:3 ; ///<
- UINT32 P2pDis:1 ; ///<
- UINT32 Reserved_15_4:12; ///<
- UINT32 ExtDevPlug:1 ; ///<
- UINT32 ExtDevCrsEn:1 ; ///<
- UINT32 CrsEn:1 ; ///<
- UINT32 IntSelMode:1 ; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
+ UINT32 Offset:20; ///<
+ UINT32 Base:4 ; ///<
+ UINT32 Top:4 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x64_x51_STRUCT;
+} GMMx2898_STRUCT;
-// **** SMUx33 Register Definition ****
+// **** GMMx28C8 Register Definition ****
// Address
-#define SMUx33_ADDRESS 0x33
+#define GMMx28C8_ADDRESS 0x28c8
// Type
-#define SMUx33_TYPE TYPE_SMU
+#define GMMx28C8_TYPE TYPE_GMM
// Field Data
-#define SMUx33_LclkActMonPrd_OFFSET 0
-#define SMUx33_LclkActMonPrd_WIDTH 16
-#define SMUx33_LclkActMonPrd_MASK 0xffff
-#define SMUx33_LclkActMonUnt_OFFSET 16
-#define SMUx33_LclkActMonUnt_WIDTH 4
-#define SMUx33_LclkActMonUnt_MASK 0xf0000
-#define SMUx33_Reserved_22_20_OFFSET 20
-#define SMUx33_Reserved_22_20_WIDTH 3
-#define SMUx33_Reserved_22_20_MASK 0x700000
-#define SMUx33_BusyCntSel_OFFSET 23
-#define SMUx33_BusyCntSel_WIDTH 2
-#define SMUx33_BusyCntSel_MASK 0x1800000
-#define SMUx33_Reserved_31_25_OFFSET 25
-#define SMUx33_Reserved_31_25_WIDTH 7
-#define SMUx33_Reserved_31_25_MASK 0xfe000000
+#define GMMx28C8_Delay_OFFSET 0
+#define GMMx28C8_Delay_WIDTH 4
+#define GMMx28C8_Delay_MASK 0xf
+#define GMMx28C8_Reserved_31_4_OFFSET 4
+#define GMMx28C8_Reserved_31_4_WIDTH 28
+#define GMMx28C8_Reserved_31_4_MASK 0xfffffff0
-/// SMUx33
+/// GMMx28C8
typedef union {
struct { ///<
- UINT32 LclkActMonPrd:16; ///<
- UINT32 LclkActMonUnt:4 ; ///<
- UINT32 Reserved_22_20:3 ; ///<
- UINT32 BusyCntSel:2 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
+ UINT32 Delay:4 ; ///<
+ UINT32 Reserved_31_4:28; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx33_STRUCT;
+} GMMx28C8_STRUCT;
-// **** SMUx0B_x8434 Register Definition ****
+// **** GMMx28D8 Register Definition ****
// Address
-#define SMUx0B_x8434_ADDRESS 0x8434
+#define GMMx28D8_ADDRESS 0x28d8
// Type
-#define SMUx0B_x8434_TYPE TYPE_SMUx0B
+#define GMMx28D8_TYPE TYPE_GMM
// Field Data
-#define SMUx0B_x8434_LclkDpmEn_OFFSET 0
-#define SMUx0B_x8434_LclkDpmEn_WIDTH 1
-#define SMUx0B_x8434_LclkDpmEn_MASK 0x1
-#define SMUx0B_x8434_LclkDpmType_OFFSET 1
-#define SMUx0B_x8434_LclkDpmType_WIDTH 1
-#define SMUx0B_x8434_LclkDpmType_MASK 0x2
-#define SMUx0B_x8434_Reserved_3_2_OFFSET 2
-#define SMUx0B_x8434_Reserved_3_2_WIDTH 2
-#define SMUx0B_x8434_Reserved_3_2_MASK 0xc
-#define SMUx0B_x8434_LclkTimerPrescalar_OFFSET 4
-#define SMUx0B_x8434_LclkTimerPrescalar_WIDTH 4
-#define SMUx0B_x8434_LclkTimerPrescalar_MASK 0xf0
-#define SMUx0B_x8434_Reserved_15_8_OFFSET 8
-#define SMUx0B_x8434_Reserved_15_8_WIDTH 8
-#define SMUx0B_x8434_Reserved_15_8_MASK 0xff00
-#define SMUx0B_x8434_LclkTimerPeriod_OFFSET 16
-#define SMUx0B_x8434_LclkTimerPeriod_WIDTH 16
-#define SMUx0B_x8434_LclkTimerPeriod_MASK 0xffff0000
+#define GMMx28D8_ActRd_OFFSET 0
+#define GMMx28D8_ActRd_WIDTH 8
+#define GMMx28D8_ActRd_MASK 0xff
+#define GMMx28D8_ActWr_OFFSET 8
+#define GMMx28D8_ActWr_WIDTH 8
+#define GMMx28D8_ActWr_MASK 0xff00
+#define GMMx28D8_RasMActRd_OFFSET 16
+#define GMMx28D8_RasMActRd_WIDTH 8
+#define GMMx28D8_RasMActRd_MASK 0xff0000
+#define GMMx28D8_RasMActWr_OFFSET 24
+#define GMMx28D8_RasMActWr_WIDTH 8
+#define GMMx28D8_RasMActWr_MASK 0xff000000
-/// SMUx0B_x8434
+/// GMMx28D8
typedef union {
struct { ///<
- UINT32 LclkDpmEn:1 ; ///<
- UINT32 LclkDpmType:1 ; ///<
- UINT32 Reserved_3_2:2 ; ///<
- UINT32 LclkTimerPrescalar:4 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 LclkTimerPeriod:16; ///<
+ UINT32 ActRd:8 ; ///<
+ UINT32 ActWr:8 ; ///<
+ UINT32 RasMActRd:8 ; ///<
+ UINT32 RasMActWr:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx28D8_STRUCT;
+
+// **** GMMx28DC Register Definition ****
+// Address
+#define GMMx28DC_ADDRESS 0x28dc
+
+// Type
+#define GMMx28DC_TYPE TYPE_GMM
+// Field Data
+#define GMMx28DC_Ras2Ras_OFFSET 0
+#define GMMx28DC_Ras2Ras_WIDTH 8
+#define GMMx28DC_Ras2Ras_MASK 0xff
+#define GMMx28DC_Rp_OFFSET 8
+#define GMMx28DC_Rp_WIDTH 8
+#define GMMx28DC_Rp_MASK 0xff00
+#define GMMx28DC_WrPlusRp_OFFSET 16
+#define GMMx28DC_WrPlusRp_WIDTH 8
+#define GMMx28DC_WrPlusRp_MASK 0xff0000
+#define GMMx28DC_BusTurn_OFFSET 24
+#define GMMx28DC_BusTurn_WIDTH 8
+#define GMMx28DC_BusTurn_MASK 0xff000000
+
+/// GMMx28DC
+typedef union {
+ struct { ///<
+ UINT32 Ras2Ras:8 ; ///<
+ UINT32 Rp:8 ; ///<
+ UINT32 WrPlusRp:8 ; ///<
+ UINT32 BusTurn:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx28DC_STRUCT;
+
+// **** GMMx2B8C Register Definition ****
+// Address
+#define GMMx2B8C_ADDRESS 0x2b8c
+
+// Type
+#define GMMx2B8C_TYPE TYPE_GMM
+// Field Data
+#define GMMx2B8C_RengRamIndex_OFFSET 0
+#define GMMx2B8C_RengRamIndex_WIDTH 10
+#define GMMx2B8C_RengRamIndex_MASK 0x3ff
+#define GMMx2B8C_Reserved_31_10_OFFSET 10
+#define GMMx2B8C_Reserved_31_10_WIDTH 22
+#define GMMx2B8C_Reserved_31_10_MASK 0xfffffc00
+
+/// GMMx2B8C
+typedef union {
+ struct { ///<
+ UINT32 RengRamIndex:10; ///<
+ UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx0B_x8434_STRUCT;
+} GMMx2B8C_STRUCT;
-// **** FCRxFF30_01E4 Register Definition ****
+// **** GMMx2B90 Register Definition ****
// Address
-#define FCRxFF30_01E4_ADDRESS 0xff3001e4
+#define GMMx2B90_ADDRESS 0x2b90
// Type
-#define FCRxFF30_01E4_TYPE TYPE_FCR
+#define GMMx2B90_TYPE TYPE_GMM
// Field Data
-#define FCRxFF30_01E4_Reserved_19_0_OFFSET 0
-#define FCRxFF30_01E4_Reserved_19_0_WIDTH 20
-#define FCRxFF30_01E4_Reserved_19_0_MASK 0xfffff
-#define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20
-#define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1
-#define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000
-#define FCRxFF30_01E4_Reserved_31_21_OFFSET 21
-#define FCRxFF30_01E4_Reserved_31_21_WIDTH 11
-#define FCRxFF30_01E4_Reserved_31_21_MASK 0xffe00000
+#define GMMx2B90_RengRamData_OFFSET 0
+#define GMMx2B90_RengRamData_WIDTH 32
+#define GMMx2B90_RengRamData_MASK 0xffffffff
-/// FCRxFF30_01E4
+/// GMMx2B90
typedef union {
struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 VoltageChangeEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
+ UINT32 RengRamData:32; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_01E4_STRUCT;
-
-// **** SMUx0B_x8470 Register Definition ****
-// Address
-#define SMUx0B_x8470_ADDRESS 0x8470
-
-
-// **** SMUx0B_x8440 Register Definition ****
-// Address
-#define SMUx0B_x8440_ADDRESS 0x8440
-
-
-// **** SMUx0B_x848C Register Definition ****
-// Address
-#define SMUx0B_x848C_ADDRESS 0x848c
-
+} GMMx2B90_STRUCT;
-// **** SMUx35 Register Definition ****
+// **** GMMx2B94 Register Definition ****
// Address
-#define SMUx35_ADDRESS 0x35
+#define GMMx2B94_ADDRESS 0x2b94
// Type
-#define SMUx35_TYPE TYPE_SMU
+#define GMMx2B94_TYPE TYPE_GMM
// Field Data
-#define SMUx35_DownTrendCoef_OFFSET 0
-#define SMUx35_DownTrendCoef_WIDTH 10
-#define SMUx35_DownTrendCoef_MASK 0x3ff
-#define SMUx35_UpTrendCoef_OFFSET 10
-#define SMUx35_UpTrendCoef_WIDTH 10
-#define SMUx35_UpTrendCoef_MASK 0xffc00
-#define SMUx35_Reserved_31_20_OFFSET 20
-#define SMUx35_Reserved_31_20_WIDTH 12
-#define SMUx35_Reserved_31_20_MASK 0xfff00000
+#define GMMx2B94_RengExecuteOnPwrUp_OFFSET 0
+#define GMMx2B94_RengExecuteOnPwrUp_WIDTH 1
+#define GMMx2B94_RengExecuteOnPwrUp_MASK 0x1
+#define GMMx2B94_Reserved_31_1_OFFSET 1
+#define GMMx2B94_Reserved_31_1_WIDTH 31
+#define GMMx2B94_Reserved_31_1_MASK 0xfffffffe
-/// SMUx35
+/// GMMx2B94
typedef union {
struct { ///<
- UINT32 DownTrendCoef:10; ///<
- UINT32 UpTrendCoef:10; ///<
- UINT32 Reserved_31_20:12; ///<
+ UINT32 RengExecuteOnPwrUp:1 ; ///<
+ UINT32 Reserved_31_1:31; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx35_STRUCT;
+} GMMx2B94_STRUCT;
-// **** SMUx37 Register Definition ****
+// **** GMMx2B98 Register Definition ****
// Address
-#define SMUx37_ADDRESS 0x37
-
-
-// **** SMUx51 Register Definition ****
+#define GMMx2B98_ADDRESS 0x2b98
+// Type
+#define GMMx2B98_TYPE TYPE_GMM
+// **** GMMx2C04 Register Definition ****
// Address
-#define SMUx51_ADDRESS 0x51
-
+#define GMMx2C04_ADDRESS 0x2c04
-// **** SMUx0B_x8490 Register Definition ****
-// Address
-#define SMUx0B_x8490_ADDRESS 0x8490
+// Type
+#define GMMx2C04_TYPE TYPE_GMM
+// Field Data
+#define GMMx2C04_NonsurfBase_OFFSET 0
+#define GMMx2C04_NonsurfBase_WIDTH 28
+#define GMMx2C04_NonsurfBase_MASK 0xfffffff
+#define GMMx2C04_Reserved_31_28_OFFSET 28
+#define GMMx2C04_Reserved_31_28_WIDTH 4
+#define GMMx2C04_Reserved_31_28_MASK 0xf0000000
+/// GMMx2C04
+typedef union {
+ struct { ///<
+ UINT32 NonsurfBase:28; ///<
+ UINT32 Reserved_31_28:4 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMx2C04_STRUCT;
-// **** DxF0xE4_xB5 Register Definition ****
+// **** GMMx5428 Register Definition ****
// Address
-#define DxF0xE4_xB5_ADDRESS 0xb5
+#define GMMx5428_ADDRESS 0x5428
// Type
-#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4
+#define GMMx5428_TYPE TYPE_GMM
// Field Data
-#define DxF0xE4_xB5_Reserved_9_0_OFFSET 0
-#define DxF0xE4_xB5_Reserved_9_0_WIDTH 10
-#define DxF0xE4_xB5_Reserved_9_0_MASK 0x3ff
-#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10
-#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1
-#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400
-#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11
-#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1
-#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800
-#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12
-#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2
-#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000
-#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14
-#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2
-#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000
-#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16
-#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16
-#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000
+#define GMMx5428_ConfigMemsize_OFFSET 0
+#define GMMx5428_ConfigMemsize_WIDTH 32
+#define GMMx5428_ConfigMemsize_MASK 0xffffffff
-/// DxF0xE4_xB5
+/// GMMx5428
typedef union {
struct { ///<
- UINT32 Reserved_9_0:10; ///<
- UINT32 LcEnhancedHotPlugEn:1 ; ///<
- UINT32 Reserved_11_11:1 ; ///<
- UINT32 LcEhpRxPhyCmd:2 ; ///<
- UINT32 LcEhpTxPhyCmd:2 ; ///<
- UINT32 Reserved_31_16:16 ; ///<
- } Field; ///<
+ UINT32 ConfigMemsize:32; ///<
+ } Field; ///<
UINT32 Value; ///<
-} DxF0xE4_xB5_STRUCT;
+} GMMx5428_STRUCT;
-// **** D0F0xE4_WRAP_80F0 Register Definition ****
+// **** GMMx5490 Register Definition ****
// Address
-#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0
+#define GMMx5490_ADDRESS 0x5490
// Type
-#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4
+#define GMMx5490_TYPE TYPE_GMM
// Field Data
-#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0
-#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32
-#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff
+#define GMMx5490_FbReadEn_OFFSET 0
+#define GMMx5490_FbReadEn_WIDTH 1
+#define GMMx5490_FbReadEn_MASK 0x1
+#define GMMx5490_FbWriteEn_OFFSET 1
+#define GMMx5490_FbWriteEn_WIDTH 1
+#define GMMx5490_FbWriteEn_MASK 0x2
+#define GMMx5490_Reserved_31_2_OFFSET 2
+#define GMMx5490_Reserved_31_2_WIDTH 30
+#define GMMx5490_Reserved_31_2_MASK 0xfffffffc
-/// D0F0xE4_WRAP_80F0
+/// GMMx5490
typedef union {
struct { ///<
- UINT32 MicroSeconds:32; ///<
+ UINT32 FbReadEn:1 ; ///<
+ UINT32 FbWriteEn:1 ; ///<
+ UINT32 Reserved_31_2:30; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_80F0_STRUCT;
-
-// **** DxF0xE4_xA5 Register Definition ****
-// Address
-#define DxF0xE4_xA5_ADDRESS 0xa5
-
+} GMMx5490_STRUCT;
-// **** D0F0xE4_WRAP_8012 Register Definition ****
+// **** SMUx0B Register Definition ****
// Address
-#define D0F0xE4_WRAP_8012_ADDRESS 0x8012
+#define SMUx0B_ADDRESS 0xb
// Type
-#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4
+#define SMUx0B_TYPE TYPE_SMU
// Field Data
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f
-#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6
-#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1
-#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80
-#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8
-#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00
-#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14
-#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2
-#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000
-#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22
-#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1
-#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000
-#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30
-#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2
-#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000
+#define SMUx0B_MemAddr_OFFSET 0
+#define SMUx0B_MemAddr_WIDTH 16
+#define SMUx0B_MemAddr_MASK 0xffff
-/// D0F0xE4_WRAP_8012
+/// SMUx0B
typedef union {
struct { ///<
- UINT32 Pif1xIdleGateLatency:6 ; ///<
- UINT32 Reserved_6_6:1 ; ///<
- UINT32 Pif1xIdleGateEnable:1 ; ///<
- UINT32 Pif1xIdleResumeLatency:6 ; ///<
- UINT32 Reserved_15_14:2 ; ///<
- UINT32 Pif2p5xIdleGateLatency:6 ; ///<
- UINT32 Reserved_22_22:1 ; ///<
- UINT32 Pif2p5xIdleGateEnable:1 ; ///<
- UINT32 Pif2p5xIdleResumeLatency:6 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8012_STRUCT;
+ UINT32 MemAddr:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_STRUCT;
-// **** D0F0xE4_WRAP_8011 Register Definition ****
+// **** MSRC001_001A Register Definition ****
// Address
-#define D0F0xE4_WRAP_8011_ADDRESS 0x8011
+#define MSRC001_001A_ADDRESS 0xc001001a
// Type
-#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4
+#define MSRC001_001A_TYPE TYPE_MSR
// Field Data
-#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0
-#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f
-#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6
-#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40
-#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7
-#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80
-#define D0F0xE4_WRAP_8011_Reserved_8_8_OFFSET 8
-#define D0F0xE4_WRAP_8011_Reserved_8_8_WIDTH 1
-#define D0F0xE4_WRAP_8011_Reserved_8_8_MASK 0x100
-#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9
-#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200
-#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10
-#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00
-#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16
-#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000
-#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17
-#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000
-#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23
-#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1
-#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000
-#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24
-#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000
-#define D0F0xE4_WRAP_8011_Reserved_31_25_OFFSET 25
-#define D0F0xE4_WRAP_8011_Reserved_31_25_WIDTH 7
-#define D0F0xE4_WRAP_8011_Reserved_31_25_MASK 0xfe000000
+#define MSRC001_001A_RAZ_22_0_OFFSET 0
+#define MSRC001_001A_RAZ_22_0_WIDTH 23
+#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff
+#define MSRC001_001A_TOM_35_23__OFFSET 23
+#define MSRC001_001A_TOM_35_23__WIDTH 13
+#define MSRC001_001A_TOM_35_23__MASK 0xfff800000
+#define MSRC001_001A_RAZ_63_36_OFFSET 36
+#define MSRC001_001A_RAZ_63_36_WIDTH 28
+#define MSRC001_001A_RAZ_63_36_MASK 0xfffffff000000000
-/// D0F0xE4_WRAP_8011
+/// MSRC001_001A
typedef union {
struct { ///<
- UINT32 TxclkDynGateLatency:6 ; ///<
- UINT32 TxclkPermGateEven:1 ; ///<
- UINT32 TxclkDynGateEnable:1 ; ///<
- UINT32 Reserved_8_8:1 ; ///<
- UINT32 TxclkRegsGateEnable:1 ; ///<
- UINT32 TxclkRegsGateLatency:6 ; ///<
- UINT32 RcvrDetClkEnable:1 ; ///<
- UINT32 TxclkPermGateLatency:6 ; ///<
- UINT32 Reserved_23_23:1 ; ///<
- UINT32 TxclkLcntGateEnable:1 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8011_STRUCT;
+ UINT64 RAZ_22_0:23; ///<
+ UINT64 TOM_35_23_:13; ///<
+ UINT64 RAZ_63_36:28; ///<
+ } Field; ///<
+ UINT64 Value; ///<
+} MSRC001_001A_STRUCT;
-// **** D0F0xE4_WRAP_8016 Register Definition ****
+
+
+// **** FCRxFF30_0134(GMMx4D0) Register Definition ****
// Address
-#define D0F0xE4_WRAP_8016_ADDRESS 0x8016
+#define FCRxFF30_0134_ADDRESS 0xff300134
-// Type
-#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4
// Field Data
-#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0
-#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6
-#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f
-#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6
-#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16
-#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0
-#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22
-#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1
-#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000
-#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23
-#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000
-#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24
-#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8
-#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000
+#define FCRxFF30_0134_DispclkDccgGateDisable_OFFSET 0
+#define FCRxFF30_0134_DispclkDccgGateDisable_WIDTH 1
+#define FCRxFF30_0134_DispclkDccgGateDisable_MASK 0x1
+#define FCRxFF30_0134_DispclkRDccgGateDisable_OFFSET 1
+#define FCRxFF30_0134_DispclkRDccgGateDisable_WIDTH 1
+#define FCRxFF30_0134_DispclkRDccgGateDisable_MASK 0x2
+#define FCRxFF30_0134_SclkGateDisable_OFFSET 2
+#define FCRxFF30_0134_SclkGateDisable_WIDTH 1
+#define FCRxFF30_0134_SclkGateDisable_MASK 0x4
+#define FCRxFF30_0134_Reserved_7_3_OFFSET 3
+#define FCRxFF30_0134_Reserved_7_3_WIDTH 5
+#define FCRxFF30_0134_Reserved_7_3_MASK 0xf8
+#define FCRxFF30_0134_SymclkaGateDisable_OFFSET 8
+#define FCRxFF30_0134_SymclkaGateDisable_WIDTH 1
+#define FCRxFF30_0134_SymclkaGateDisable_MASK 0x100
+#define FCRxFF30_0134_SymclkbGateDisable_OFFSET 9
+#define FCRxFF30_0134_SymclkbGateDisable_WIDTH 1
+#define FCRxFF30_0134_SymclkbGateDisable_MASK 0x200
+#define FCRxFF30_0134_Reserved_31_10_OFFSET 10
+#define FCRxFF30_0134_Reserved_31_10_WIDTH 22
+#define FCRxFF30_0134_Reserved_31_10_MASK 0xfffffc00
-/// D0F0xE4_WRAP_8016
+/// FCRxFF30_0134
typedef union {
struct { ///<
- UINT32 CalibAckLatency:6 ; ///<
- UINT32 Reserved_21_6:16; ///<
- UINT32 LclkGateFree:1 ; ///<
- UINT32 LclkDynGateEnable:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
+ UINT32 DispclkDccgGateDisable:1 ; ///<
+ UINT32 DispclkRDccgGateDisable:1 ; ///<
+ UINT32 SclkGateDisable:1 ; ///<
+ UINT32 Reserved_7_3:5 ; ///<
+ UINT32 SymclkaGateDisable:1 ; ///<
+ UINT32 SymclkbGateDisable:1 ; ///<
+ UINT32 Reserved_31_10:22; ///<
+ } Field; ///<
UINT32 Value; ///<
-} D0F0xE4_WRAP_8016_STRUCT;
+} FCRxFF30_0134_STRUCT;
-// **** D18F6x110 Register Definition ****
+// **** FCRxFF30_01F4 Register Definition ****
// Address
-#define D18F6x110_ADDRESS 0x110
+#define FCRxFF30_01F4_ADDRESS 0xff3001f4
// Type
-#define D18F6x110_TYPE TYPE_D18F6
+#define FCRxFF30_01F4_TYPE TYPE_FCR
// Field Data
-#define D18F6x110_NclkFifoOff_OFFSET 0
-#define D18F6x110_NclkFifoOff_WIDTH 3
-#define D18F6x110_NclkFifoOff_MASK 0x7
-#define D18F6x110_Reserved_3_3_OFFSET 3
-#define D18F6x110_Reserved_3_3_WIDTH 1
-#define D18F6x110_Reserved_3_3_MASK 0x8
-#define D18F6x110_LclkFifoOff_OFFSET 4
-#define D18F6x110_LclkFifoOff_WIDTH 3
-#define D18F6x110_LclkFifoOff_MASK 0x70
-#define D18F6x110_Reserved_7_7_OFFSET 7
-#define D18F6x110_Reserved_7_7_WIDTH 1
-#define D18F6x110_Reserved_7_7_MASK 0x80
-#define D18F6x110_PllMult_OFFSET 8
-#define D18F6x110_PllMult_WIDTH 6
-#define D18F6x110_PllMult_MASK 0x3f00
-#define D18F6x110_Reserved_14_14_OFFSET 14
-#define D18F6x110_Reserved_14_14_WIDTH 1
-#define D18F6x110_Reserved_14_14_MASK 0x4000
-#define D18F6x110_Enable_OFFSET 15
-#define D18F6x110_Enable_WIDTH 1
-#define D18F6x110_Enable_MASK 0x8000
-#define D18F6x110_LclkFreq_OFFSET 16
-#define D18F6x110_LclkFreq_WIDTH 7
-#define D18F6x110_LclkFreq_MASK 0x7f0000
-#define D18F6x110_LclkFreqType_OFFSET 23
-#define D18F6x110_LclkFreqType_WIDTH 1
-#define D18F6x110_LclkFreqType_MASK 0x800000
-#define D18F6x110_NclkFreq_OFFSET 24
-#define D18F6x110_NclkFreq_WIDTH 7
-#define D18F6x110_NclkFreq_MASK 0x7f000000
-#define D18F6x110_NclkFreqType_OFFSET 31
-#define D18F6x110_NclkFreqType_WIDTH 1
-#define D18F6x110_NclkFreqType_MASK 0x80000000
+#define FCRxFF30_01F4_CgRlcCgttSclkOverride_OFFSET 0
+#define FCRxFF30_01F4_CgRlcCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgRlcCgttSclkOverride_MASK 0x1
+#define FCRxFF30_01F4_CgCpCgttSclkOverride_OFFSET 1
+#define FCRxFF30_01F4_CgCpCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgCpCgttSclkOverride_MASK 0x2
+#define FCRxFF30_01F4_CgVgtCgttSclkOverride_OFFSET 2
+#define FCRxFF30_01F4_CgVgtCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgVgtCgttSclkOverride_MASK 0x4
+#define FCRxFF30_01F4_CgPaCgttSclkOverride_OFFSET 3
+#define FCRxFF30_01F4_CgPaCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgPaCgttSclkOverride_MASK 0x8
+#define FCRxFF30_01F4_CgScCgttSclkOverride_OFFSET 4
+#define FCRxFF30_01F4_CgScCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgScCgttSclkOverride_MASK 0x10
+#define FCRxFF30_01F4_CgSpimCgttSclkOverride_OFFSET 5
+#define FCRxFF30_01F4_CgSpimCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgSpimCgttSclkOverride_MASK 0x20
+#define FCRxFF30_01F4_CgSxmCgttSclkOverride_OFFSET 6
+#define FCRxFF30_01F4_CgSxmCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgSxmCgttSclkOverride_MASK 0x40
+#define FCRxFF30_01F4_CgSxsCgttSclkOverride_OFFSET 7
+#define FCRxFF30_01F4_CgSxsCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgSxsCgttSclkOverride_MASK 0x80
+#define FCRxFF30_01F4_CgCb0CgttSclkOverride_OFFSET 8
+#define FCRxFF30_01F4_CgCb0CgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgCb0CgttSclkOverride_MASK 0x100
+#define FCRxFF30_01F4_CgCb1CgttSclkOverride_OFFSET 9
+#define FCRxFF30_01F4_CgCb1CgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgCb1CgttSclkOverride_MASK 0x200
+#define FCRxFF30_01F4_ReservedCgtt10Override_OFFSET 10
+#define FCRxFF30_01F4_ReservedCgtt10Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt10Override_MASK 0x400
+#define FCRxFF30_01F4_ReservedCgtt11Override_OFFSET 11
+#define FCRxFF30_01F4_ReservedCgtt11Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt11Override_MASK 0x800
+#define FCRxFF30_01F4_CgDb0CgttSclkOverride_OFFSET 12
+#define FCRxFF30_01F4_CgDb0CgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgDb0CgttSclkOverride_MASK 0x1000
+#define FCRxFF30_01F4_CgDb1CgttSclkOverride_OFFSET 13
+#define FCRxFF30_01F4_CgDb1CgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgDb1CgttSclkOverride_MASK 0x2000
+#define FCRxFF30_01F4_ReservedCgtt14Override_OFFSET 14
+#define FCRxFF30_01F4_ReservedCgtt14Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt14Override_MASK 0x4000
+#define FCRxFF30_01F4_ReservedCgtt15Override_OFFSET 15
+#define FCRxFF30_01F4_ReservedCgtt15Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt15Override_MASK 0x8000
+#define FCRxFF30_01F4_CgVcCgttSclkOverride_OFFSET 16
+#define FCRxFF30_01F4_CgVcCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgVcCgttSclkOverride_MASK 0x10000
+#define FCRxFF30_01F4_CgAvpCgttSclkOverride_OFFSET 17
+#define FCRxFF30_01F4_CgAvpCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgAvpCgttSclkOverride_MASK 0x20000
+#define FCRxFF30_01F4_CgAvpCgttEclkOverride_OFFSET 18
+#define FCRxFF30_01F4_CgAvpCgttEclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgAvpCgttEclkOverride_MASK 0x40000
+#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_OFFSET 19
+#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgUvdmCgttSclkOverride_MASK 0x80000
+#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_OFFSET 20
+#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgUvdmCgttVclkOverride_MASK 0x100000
+#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_OFFSET 21
+#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgUvdmCgttDclkOverride_MASK 0x200000
+#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22
+#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000
+#define FCRxFF30_01F4_CgRomCgttSclkOverride_OFFSET 23
+#define FCRxFF30_01F4_CgRomCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgRomCgttSclkOverride_MASK 0x800000
+#define FCRxFF30_01F4_CgDrmCgttSclkOverride_OFFSET 24
+#define FCRxFF30_01F4_CgDrmCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgDrmCgttSclkOverride_MASK 0x1000000
+#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25
+#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000
+#define FCRxFF30_01F4_ReservedCgtt26Override_OFFSET 26
+#define FCRxFF30_01F4_ReservedCgtt26Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt26Override_MASK 0x4000000
+#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27
+#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000
+#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28
+#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000
+#define FCRxFF30_01F4_ReservedCgtt29Override_OFFSET 29
+#define FCRxFF30_01F4_ReservedCgtt29Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt29Override_MASK 0x20000000
+#define FCRxFF30_01F4_ReservedCgtt30Override_OFFSET 30
+#define FCRxFF30_01F4_ReservedCgtt30Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt30Override_MASK 0x40000000
+#define FCRxFF30_01F4_ReservedCgtt31Override_OFFSET 31
+#define FCRxFF30_01F4_ReservedCgtt31Override_WIDTH 1
+#define FCRxFF30_01F4_ReservedCgtt31Override_MASK 0x80000000
-/// D18F6x110
+/// FCRxFF30_01F4
typedef union {
struct { ///<
- UINT32 NclkFifoOff:3 ; ///<
- UINT32 Reserved_3_3:1 ; ///<
- UINT32 LclkFifoOff:3 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 PllMult:6 ; ///<
- UINT32 Reserved_14_14:1 ; ///<
- UINT32 Enable:1 ; ///<
- UINT32 LclkFreq:7 ; ///<
- UINT32 LclkFreqType:1 ; ///<
- UINT32 NclkFreq:7 ; ///<
- UINT32 NclkFreqType:1 ; ///<
+ UINT32 CgRlcCgttSclkOverride:1 ; ///<
+ UINT32 CgCpCgttSclkOverride:1 ; ///<
+ UINT32 CgVgtCgttSclkOverride:1 ; ///<
+ UINT32 CgPaCgttSclkOverride:1 ; ///<
+ UINT32 CgScCgttSclkOverride:1 ; ///<
+ UINT32 CgSpimCgttSclkOverride:1 ; ///<
+ UINT32 CgSxmCgttSclkOverride:1 ; ///<
+ UINT32 CgSxsCgttSclkOverride:1 ; ///<
+ UINT32 CgCb0CgttSclkOverride:1 ; ///<
+ UINT32 CgCb1CgttSclkOverride:1 ; ///<
+ UINT32 ReservedCgtt10Override:1 ; ///<
+ UINT32 ReservedCgtt11Override:1 ; ///<
+ UINT32 CgDb0CgttSclkOverride:1 ; ///<
+ UINT32 CgDb1CgttSclkOverride:1 ; ///<
+ UINT32 ReservedCgtt14Override:1 ; ///<
+ UINT32 ReservedCgtt15Override:1 ; ///<
+ UINT32 CgVcCgttSclkOverride:1 ; ///<
+ UINT32 CgAvpCgttSclkOverride:1 ; ///<
+ UINT32 CgAvpCgttEclkOverride:1 ; ///<
+ UINT32 CgUvdmCgttSclkOverride:1 ; ///<
+ UINT32 CgUvdmCgttVclkOverride:1 ; ///<
+ UINT32 CgUvdmCgttDclkOverride:1 ; ///<
+ UINT32 CgBifCgttSclkOverride:1 ; ///<
+ UINT32 CgRomCgttSclkOverride:1 ; ///<
+ UINT32 CgDrmCgttSclkOverride:1 ; ///<
+ UINT32 CgDcCgttSclkOverride:1 ; ///<
+ UINT32 ReservedCgtt26Override:1 ; ///<
+ UINT32 CgMcbCgttSclkOverride:1 ; ///<
+ UINT32 CgMcdwCgttSclkOverride:1 ; ///<
+ UINT32 ReservedCgtt29Override:1 ; ///<
+ UINT32 ReservedCgtt30Override:1 ; ///<
+ UINT32 ReservedCgtt31Override:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F6x110_STRUCT;
+} FCRxFF30_01F4_STRUCT;
-// **** D18F3xA0 Register Definition ****
+// **** FCRxFF30_01F5 Register Definition ****
// Address
-#define D18F3xA0_ADDRESS 0xa0
+#define FCRxFF30_01F5_ADDRESS 0xff3001f5
// Type
-#define D18F3xA0_TYPE TYPE_D18F3
+#define FCRxFF30_01F5_TYPE TYPE_FCR
// Field Data
-#define D18F3xA0_PsiVid_OFFSET 0
-#define D18F3xA0_PsiVid_WIDTH 7
-#define D18F3xA0_PsiVid_MASK 0x7f
-#define D18F3xA0_PsiVidEn_OFFSET 7
-#define D18F3xA0_PsiVidEn_WIDTH 1
-#define D18F3xA0_PsiVidEn_MASK 0x80
-#define D18F3xA0_Reserved_8_8_OFFSET 8
-#define D18F3xA0_Reserved_8_8_WIDTH 1
-#define D18F3xA0_Reserved_8_8_MASK 0x100
-#define D18F3xA0_SviHighFreqSel_OFFSET 9
-#define D18F3xA0_SviHighFreqSel_WIDTH 1
-#define D18F3xA0_SviHighFreqSel_MASK 0x200
-#define D18F3xA0_Reserved_15_10_OFFSET 10
-#define D18F3xA0_Reserved_15_10_WIDTH 6
-#define D18F3xA0_Reserved_15_10_MASK 0xfc00
-#define D18F3xA0_ConfigId_OFFSET 16
-#define D18F3xA0_ConfigId_WIDTH 12
-#define D18F3xA0_ConfigId_MASK 0xfff0000
-#define D18F3xA0_Reserved_30_28_OFFSET 28
-#define D18F3xA0_Reserved_30_28_WIDTH 3
-#define D18F3xA0_Reserved_30_28_MASK 0x70000000
-#define D18F3xA0_CofVidProg_OFFSET 31
-#define D18F3xA0_CofVidProg_WIDTH 1
-#define D18F3xA0_CofVidProg_MASK 0x80000000
+#define FCRxFF30_01F5_ReservedCgtt32Override_OFFSET 0
+#define FCRxFF30_01F5_ReservedCgtt32Override_WIDTH 1
+#define FCRxFF30_01F5_ReservedCgtt32Override_MASK 0x1
+#define FCRxFF30_01F5_ReservedCgtt33Override_OFFSET 1
+#define FCRxFF30_01F5_ReservedCgtt33Override_WIDTH 1
+#define FCRxFF30_01F5_ReservedCgtt33Override_MASK 0x2
+#define FCRxFF30_01F5_ReservedCgtt34Override_OFFSET 2
+#define FCRxFF30_01F5_ReservedCgtt34Override_WIDTH 1
+#define FCRxFF30_01F5_ReservedCgtt34Override_MASK 0x4
+#define FCRxFF30_01F5_ReservedCgtt35Override_OFFSET 3
+#define FCRxFF30_01F5_ReservedCgtt35Override_WIDTH 1
+#define FCRxFF30_01F5_ReservedCgtt35Override_MASK 0x8
+#define FCRxFF30_01F5_CgTaCgttSclkOverride_OFFSET 4
+#define FCRxFF30_01F5_CgTaCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgTaCgttSclkOverride_MASK 0x10
+#define FCRxFF30_01F5_CgTdCgttSclkOverride_OFFSET 5
+#define FCRxFF30_01F5_CgTdCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgTdCgttSclkOverride_MASK 0x20
+#define FCRxFF30_01F5_CgTcaCgttSclkOverride_OFFSET 6
+#define FCRxFF30_01F5_CgTcaCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgTcaCgttSclkOverride_MASK 0x40
+#define FCRxFF30_01F5_CgTcpCgttSclkOverride_OFFSET 7
+#define FCRxFF30_01F5_CgTcpCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgTcpCgttSclkOverride_MASK 0x80
+#define FCRxFF30_01F5_CgTccCgttSclkOverride_OFFSET 8
+#define FCRxFF30_01F5_CgTccCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgTccCgttSclkOverride_MASK 0x100
+#define FCRxFF30_01F5_CgSqCgttSclkOverride_OFFSET 9
+#define FCRxFF30_01F5_CgSqCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgSqCgttSclkOverride_MASK 0x200
+#define FCRxFF30_01F5_CgHdpCgttSclkOverride_OFFSET 10
+#define FCRxFF30_01F5_CgHdpCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgHdpCgttSclkOverride_MASK 0x400
+#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11
+#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800
+#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12
+#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000
+#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13
+#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000
+#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14
+#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000
+#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15
+#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000
+#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_OFFSET 16
+#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgGrbmCgttSclkOverride_MASK 0x10000
+#define FCRxFF30_01F5_ReservedCgtt49Override_OFFSET 17
+#define FCRxFF30_01F5_ReservedCgtt49Override_WIDTH 1
+#define FCRxFF30_01F5_ReservedCgtt49Override_MASK 0x20000
+#define FCRxFF30_01F5_CgSmuCgttSclkOverride_OFFSET 18
+#define FCRxFF30_01F5_CgSmuCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgSmuCgttSclkOverride_MASK 0x40000
+#define FCRxFF30_01F5_ReservedCgtt51Override_OFFSET 19
+#define FCRxFF30_01F5_ReservedCgtt51Override_WIDTH 1
+#define FCRxFF30_01F5_ReservedCgtt51Override_MASK 0x80000
+#define FCRxFF30_01F5_CgIhCgttSclkOverride_OFFSET 20
+#define FCRxFF30_01F5_CgIhCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgIhCgttSclkOverride_MASK 0x100000
+#define FCRxFF30_01F5_CgDbgCgttSclkOverride_OFFSET 21
+#define FCRxFF30_01F5_CgDbgCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgDbgCgttSclkOverride_MASK 0x200000
+#define FCRxFF30_01F5_CgSemCgttSclkOverride_OFFSET 22
+#define FCRxFF30_01F5_CgSemCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgSemCgttSclkOverride_MASK 0x400000
+#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_OFFSET 23
+#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgSrbmCgttSclkOverride_MASK 0x800000
+#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_OFFSET 24
+#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgDrmdmaCgttSclkOverride_MASK 0x1000000
+#define FCRxFF30_01F5_CgUvduCgttSclkOverride_OFFSET 25
+#define FCRxFF30_01F5_CgUvduCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgUvduCgttSclkOverride_MASK 0x2000000
+#define FCRxFF30_01F5_CgUvduCgttVclkOverride_OFFSET 26
+#define FCRxFF30_01F5_CgUvduCgttVclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgUvduCgttVclkOverride_MASK 0x4000000
+#define FCRxFF30_01F5_CgUvduCgttDclkOverride_OFFSET 27
+#define FCRxFF30_01F5_CgUvduCgttDclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgUvduCgttDclkOverride_MASK 0x8000000
+#define FCRxFF30_01F5_CgDcCgttDispclkOverride_OFFSET 28
+#define FCRxFF30_01F5_CgDcCgttDispclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgDcCgttDispclkOverride_MASK 0x10000000
+#define FCRxFF30_01F5_CgXbrCgttSclkOverride_OFFSET 29
+#define FCRxFF30_01F5_CgXbrCgttSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgXbrCgttSclkOverride_MASK 0x20000000
+#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_OFFSET 30
+#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_WIDTH 1
+#define FCRxFF30_01F5_CgSpimCgtsSclkOverride_MASK 0x40000000
+#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_OFFSET 31
+#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_WIDTH 1
+#define FCRxFF30_01F5_CgSpimCgtsSclkLsOverride_MASK 0x80000000
-/// D18F3xA0
+/// FCRxFF30_01F5
typedef union {
struct { ///<
- UINT32 PsiVid:7 ; ///<
- UINT32 PsiVidEn:1 ; ///<
- UINT32 Reserved_8_8:1 ; ///<
- UINT32 SviHighFreqSel:1 ; ///<
- UINT32 Reserved_15_10:6 ; ///<
- UINT32 ConfigId:12; ///<
- UINT32 Reserved_30_28:3 ; ///<
- UINT32 CofVidProg:1 ; ///<
+ UINT32 ReservedCgtt32Override:1 ; ///<
+ UINT32 ReservedCgtt33Override:1 ; ///<
+ UINT32 ReservedCgtt34Override:1 ; ///<
+ UINT32 ReservedCgtt35Override:1 ; ///<
+ UINT32 CgTaCgttSclkOverride:1 ; ///<
+ UINT32 CgTdCgttSclkOverride:1 ; ///<
+ UINT32 CgTcaCgttSclkOverride:1 ; ///<
+ UINT32 CgTcpCgttSclkOverride:1 ; ///<
+ UINT32 CgTccCgttSclkOverride:1 ; ///<
+ UINT32 CgSqCgttSclkOverride:1 ; ///<
+ UINT32 CgHdpCgttSclkOverride:1 ; ///<
+ UINT32 CgVmcCgttSclkOverride:1 ; ///<
+ UINT32 CgOrbCgttSclkOverride:1 ; ///<
+ UINT32 CgOrbCgttLclkOverride:1 ; ///<
+ UINT32 CgIocCgttSclkOverride:1 ; ///<
+ UINT32 CgIocCgttLclkOverride:1 ; ///<
+ UINT32 CgGrbmCgttSclkOverride:1 ; ///<
+ UINT32 ReservedCgtt49Override:1 ; ///<
+ UINT32 CgSmuCgttSclkOverride:1 ; ///<
+ UINT32 ReservedCgtt51Override:1 ; ///<
+ UINT32 CgIhCgttSclkOverride:1 ; ///<
+ UINT32 CgDbgCgttSclkOverride:1 ; ///<
+ UINT32 CgSemCgttSclkOverride:1 ; ///<
+ UINT32 CgSrbmCgttSclkOverride:1 ; ///<
+ UINT32 CgDrmdmaCgttSclkOverride:1 ; ///<
+ UINT32 CgUvduCgttSclkOverride:1 ; ///<
+ UINT32 CgUvduCgttVclkOverride:1 ; ///<
+ UINT32 CgUvduCgttDclkOverride:1 ; ///<
+ UINT32 CgDcCgttDispclkOverride:1 ; ///<
+ UINT32 CgXbrCgttSclkOverride:1 ; ///<
+ UINT32 CgSpimCgtsSclkOverride:1 ; ///<
+ UINT32 CgSpimCgtsSclkLsOverride:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3xA0_STRUCT;
+} FCRxFF30_01F5_STRUCT;
-// **** FCRxFF30_0398 Register Definition ****
+// **** FCRxFF30_1B7C(GMMx6DF0) Register Definition ****
// Address
-#define FCRxFF30_0398_ADDRESS 0xff300398
+#define FCRxFF30_1B7C_ADDRESS 0xff301B7C
-// Type
-#define FCRxFF30_0398_TYPE TYPE_FCR
// Field Data
-#define FCRxFF30_0398_Reserved_4_0_OFFSET 0
-#define FCRxFF30_0398_Reserved_4_0_WIDTH 5
-#define FCRxFF30_0398_Reserved_4_0_MASK 0x1f
-#define FCRxFF30_0398_SoftResetDc_OFFSET 5
-#define FCRxFF30_0398_SoftResetDc_WIDTH 1
-#define FCRxFF30_0398_SoftResetDc_MASK 0x20
-#define FCRxFF30_0398_Reserved_6_6_OFFSET 6
-#define FCRxFF30_0398_Reserved_6_6_WIDTH 1
-#define FCRxFF30_0398_Reserved_6_6_MASK 0x40
-#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8
-#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1
-#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100
-#define FCRxFF30_0398_SoftResetMc_OFFSET 11
-#define FCRxFF30_0398_SoftResetMc_WIDTH 1
-#define FCRxFF30_0398_SoftResetMc_MASK 0x800
-#define FCRxFF30_0398_Reserved_12_12_OFFSET 12
-#define FCRxFF30_0398_Reserved_12_12_WIDTH 1
-#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000
-#define FCRxFF30_0398_SoftResetRlc_OFFSET 13
-#define FCRxFF30_0398_SoftResetRlc_WIDTH 1
-#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000
-#define FCRxFF30_0398_Reserved_16_16_OFFSET 16
-#define FCRxFF30_0398_Reserved_16_16_WIDTH 1
-#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000
-#define FCRxFF30_0398_SoftResetUvd_OFFSET 18
-#define FCRxFF30_0398_SoftResetUvd_WIDTH 1
-#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000
-#define FCRxFF30_0398_Reserved_31_19_OFFSET 19
-#define FCRxFF30_0398_Reserved_31_19_WIDTH 13
-#define FCRxFF30_0398_Reserved_31_19_MASK 0xfff80000
+#define FCRxFF30_1B7C_Reserved_3_0_OFFSET 0
+#define FCRxFF30_1B7C_Reserved_3_0_WIDTH 4
+#define FCRxFF30_1B7C_Reserved_3_0_MASK 0xf
+#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_OFFSET 4
+#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_WIDTH 1
+#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_MASK 0x10
+#define FCRxFF30_1B7C_Reserved_7_5_OFFSET 5
+#define FCRxFF30_1B7C_Reserved_7_5_WIDTH 3
+#define FCRxFF30_1B7C_Reserved_7_5_MASK 0xe0
+#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_OFFSET 8
+#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_WIDTH 1
+#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_MASK 0x100
+#define FCRxFF30_1B7C_Reserved_11_9_OFFSET 9
+#define FCRxFF30_1B7C_Reserved_11_9_WIDTH 3
+#define FCRxFF30_1B7C_Reserved_11_9_MASK 0xe00
+#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_OFFSET 12
+#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_WIDTH 1
+#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_MASK 0x1000
+#define FCRxFF30_1B7C_Reserved_31_13_OFFSET 13
+#define FCRxFF30_1B7C_Reserved_31_13_WIDTH 19
+#define FCRxFF30_1B7C_Reserved_31_13_MASK 0xffffe000
-/// FCRxFF30_0398
+/// FCRxFF30_1B7C
typedef union {
struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 SoftResetDc:1 ; ///<
- UINT32 Reserved_6_6:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 SoftResetGrbm:1 ; ///<
- UINT32 Reserved_9_9:1 ; ///<
- UINT32 Reserved_10_10:1 ; ///<
- UINT32 SoftResetMc:1 ; ///<
- UINT32 Reserved_12_12:1 ; ///<
- UINT32 SoftResetRlc:1 ; ///<
- UINT32 Reserved_14_14:1 ; ///<
- UINT32 Reserved_15_15:1 ; ///<
- UINT32 Reserved_16_16:1 ; ///<
- UINT32 Reserved_17_17:1 ; ///<
- UINT32 SoftResetUvd:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///<
+ UINT32 Reserved_7_5:3 ; ///<
+ UINT32 CrtcDispclkGDcpGateDisable:1 ; ///<
+ UINT32 Reserved_11_9:3 ; ///<
+ UINT32 CrtcDispclkGSclGateDisable:1 ; ///<
+ UINT32 Reserved_31_13:19; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_0398_STRUCT;
+} FCRxFF30_1B7C_STRUCT;
-// **** SMUx0B_x8504 Register Definition ****
+// **** FCRxFF30_1E7C(GMMx79F0) Register Definition ****
// Address
-#define SMUx0B_x8504_ADDRESS 0x8504
+#define FCRxFF30_1E7C_ADDRESS 0xff301E7C
-// Type
-#define SMUx0B_x8504_TYPE TYPE_SMUx0B
// Field Data
-#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0
-#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8
-#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff
-#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8
-#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8
-#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00
-#define SMUx0B_x8504_Reserved_31_16_OFFSET 16
-#define SMUx0B_x8504_Reserved_31_16_WIDTH 16
-#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000
+#define FCRxFF30_1E7C_Reserved_3_0_OFFSET 0
+#define FCRxFF30_1E7C_Reserved_3_0_WIDTH 4
+#define FCRxFF30_1E7C_Reserved_3_0_MASK 0xf
+#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_OFFSET 4
+#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_WIDTH 1
+#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_MASK 0x10
+#define FCRxFF30_1E7C_Reserved_7_5_OFFSET 5
+#define FCRxFF30_1E7C_Reserved_7_5_WIDTH 3
+#define FCRxFF30_1E7C_Reserved_7_5_MASK 0xe0
+#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_OFFSET 8
+#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_WIDTH 1
+#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_MASK 0x100
+#define FCRxFF30_1E7C_Reserved_11_9_OFFSET 9
+#define FCRxFF30_1E7C_Reserved_11_9_WIDTH 3
+#define FCRxFF30_1E7C_Reserved_11_9_MASK 0xe00
+#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_OFFSET 12
+#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_WIDTH 1
+#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_MASK 0x1000
+#define FCRxFF30_1E7C_Reserved_31_13_OFFSET 13
+#define FCRxFF30_1E7C_Reserved_31_13_WIDTH 19
+#define FCRxFF30_1E7C_Reserved_31_13_MASK 0xffffe000
-/// SMUx0B_x8504
+/// FCRxFF30_1E7C
typedef union {
struct { ///<
- UINT32 SaveRestoreWidth:8 ; ///<
- UINT32 PsoRestoreTimer:8 ; ///<
- UINT32 Reserved_31_16:16; ///<
+ UINT32 Reserved_3_0:4 ; ///<
+ UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///<
+ UINT32 Reserved_7_5:3 ; ///<
+ UINT32 CrtcDispclkGDcpGateDisable:1 ; ///<
+ UINT32 Reserved_11_9:3 ; ///<
+ UINT32 CrtcDispclkGSclGateDisable:1 ; ///<
+ UINT32 Reserved_31_13:19; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx0B_x8504_STRUCT;
+} FCRxFF30_1E7C_STRUCT;
-// **** SMUx0B_x8408 Register Definition ****
+// **** FCRxFE00_600E Register Definition ****
// Address
-#define SMUx0B_x8408_ADDRESS 0x8408
+#define FCRxFE00_600E_ADDRESS 0xfe00600e
+// Field Data
+#define FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET 0
+#define FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH 6
+#define FCRxFE00_600E_WrCkDid_OFFSET 10
+#define FCRxFE00_600E_WrCkDid_WIDTH 5
-// **** SMUx0B_x8410 Register Definition ****
+/// FCRxFE00_600E
+typedef union {
+ struct {
+ UINT32 MainPllOpFreqIdStartup:6 ; ///<
+ UINT32 Reserved:5 ; ///<
+ UINT32 WrCkDid:5 ; ///<
+ } Field;
+ UINT32 Value;
+} FCRxFE00_600E_STRUCT;
+
+// **** SMUx0B_x8498 Register Definition ****
// Address
-#define SMUx0B_x8410_ADDRESS 0x8410
+#define SMUx0B_x8498_ADDRESS 0x8498
-// Type
-#define SMUx0B_x8410_TYPE TYPE_SMUx0B
// Field Data
-#define SMUx0B_x8410_PwrGatingEn_OFFSET 0
-#define SMUx0B_x8410_PwrGatingEn_WIDTH 1
-#define SMUx0B_x8410_PwrGatingEn_MASK 0x1
-#define SMUx0B_x8410_Reserved_2_1_OFFSET 1
-#define SMUx0B_x8410_Reserved_2_1_WIDTH 2
-#define SMUx0B_x8410_Reserved_2_1_MASK 0x6
-#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3
-#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5
-#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8
-#define SMUx0B_x8410_SavePsoDelay_OFFSET 8
-#define SMUx0B_x8410_SavePsoDelay_WIDTH 4
-#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00
-#define SMUx0B_x8410_Reserved_27_12_OFFSET 12
-#define SMUx0B_x8410_Reserved_27_12_WIDTH 16
-#define SMUx0B_x8410_Reserved_27_12_MASK 0xffff000
-#define SMUx0B_x8410_PwrGaterSel_OFFSET 28
-#define SMUx0B_x8410_PwrGaterSel_WIDTH 4
-#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000
+#define SMUx0B_x8498_ConditionalBF_1_0_OFFSET 0
+#define SMUx0B_x8498_ConditionalBF_1_0_WIDTH 2
+#define SMUx0B_x8498_ConditionalBF_1_0_MASK 0x3
+#define SMUx0B_x8498_ConditionalBF_3_2_OFFSET 2
+#define SMUx0B_x8498_ConditionalBF_3_2_WIDTH 2
+#define SMUx0B_x8498_ConditionalBF_3_2_MASK 0xc
+#define SMUx0B_x8498_Reserved_7_4_OFFSET 4
+#define SMUx0B_x8498_Reserved_7_4_WIDTH 4
+#define SMUx0B_x8498_Reserved_7_4_MASK 0xf0
+#define SMUx0B_x8498_ConditionalBF_9_8_OFFSET 8
+#define SMUx0B_x8498_ConditionalBF_9_8_WIDTH 2
+#define SMUx0B_x8498_ConditionalBF_9_8_MASK 0x300
+#define SMUx0B_x8498_ConditionalBF_11_10_OFFSET 10
+#define SMUx0B_x8498_ConditionalBF_11_10_WIDTH 2
+#define SMUx0B_x8498_ConditionalBF_11_10_MASK 0xc00
+#define SMUx0B_x8498_Reserved_15_12_OFFSET 12
+#define SMUx0B_x8498_Reserved_15_12_WIDTH 4
+#define SMUx0B_x8498_Reserved_15_12_MASK 0xf000
+#define SMUx0B_x8498_BaseVid_5_OFFSET 16
+#define SMUx0B_x8498_BaseVid_5_WIDTH 2
+#define SMUx0B_x8498_BaseVid_5_MASK 0x30000
+#define SMUx0B_x8498_TolExcdVid_5_OFFSET 18
+#define SMUx0B_x8498_TolExcdVid_5_WIDTH 2
+#define SMUx0B_x8498_TolExcdVid_5_MASK 0xc0000
+#define SMUx0B_x8498_Reserved_23_20_OFFSET 20
+#define SMUx0B_x8498_Reserved_23_20_WIDTH 4
+#define SMUx0B_x8498_Reserved_23_20_MASK 0xf00000
+#define SMUx0B_x8498_BaseVid_4_OFFSET 24
+#define SMUx0B_x8498_BaseVid_4_WIDTH 2
+#define SMUx0B_x8498_BaseVid_4_MASK 0x3000000
+#define SMUx0B_x8498_TolExcdVid_4_OFFSET 26
+#define SMUx0B_x8498_TolExcdVid_4_WIDTH 2
+#define SMUx0B_x8498_TolExcdVid_4_MASK 0xc000000
+#define SMUx0B_x8498_Reserved_31_28_OFFSET 28
+#define SMUx0B_x8498_Reserved_31_28_WIDTH 4
+#define SMUx0B_x8498_Reserved_31_28_MASK 0xf0000000
-/// SMUx0B_x8410
+/// SMUx0B_x8498
typedef union {
struct { ///<
- UINT32 PwrGatingEn:1 ; ///<
- UINT32 Reserved_2_1:2 ; ///<
- UINT32 PsoControlValidNum:5 ; ///<
- UINT32 SavePsoDelay:4 ; ///<
- UINT32 Reserved_27_12:16; ///<
- UINT32 PwrGaterSel:4 ; ///<
+ UINT32 ConditionalBF_1_0:2 ; ///<
+ UINT32 ConditionalBF_3_2:2 ; ///<
+ UINT32 Reserved_7_4:4 ; ///<
+ UINT32 ConditionalBF_9_8:2 ; ///<
+ UINT32 ConditionalBF_11_10:2 ; ///<
+ UINT32 Reserved_15_12:4 ; ///<
+ UINT32 BaseVid_5:2 ; ///<
+ UINT32 TolExcdVid_5:2 ; ///<
+ UINT32 Reserved_23_20:4 ; ///<
+ UINT32 BaseVid_4:2 ; ///<
+ UINT32 TolExcdVid_4:2 ; ///<
+ UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx0B_x8410_STRUCT;
+} SMUx0B_x8498_STRUCT;
-// **** SMUx0B_x84A0 Register Definition ****
+
+// **** SMUx0B_x85B0 Register Definition ****
// Address
-#define SMUx0B_x84A0_ADDRESS 0x84a0
+#define SMUx0B_x85B0_ADDRESS 0x85B0
-// **** D0F0xE4_CORE_0020 Register Definition ****
+// **** SMUx0B_x85D0 Register Definition ****
// Address
-#define D0F0xE4_CORE_0020_ADDRESS 0x20
+#define SMUx0B_x85D0_ADDRESS 0x85D0
+
+// **** D0F0x64_x51 Register Definition ****
+// Address
+#define D0F0x64_x51_ADDRESS 0x51
// Type
-#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4
+#define D0F0x64_x51_TYPE TYPE_D0F0x64
// Field Data
-#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0
-#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9
-#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff
-#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8
-#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1
-#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100
-#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9
-#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1
-#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200
-#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10
-#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22
-#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00
+#define D0F0x64_x51_Reserved_2_0_OFFSET 0
+#define D0F0x64_x51_Reserved_2_0_WIDTH 3
+#define D0F0x64_x51_Reserved_2_0_MASK 0x7
+#define D0F0x64_x51_P2pDis_OFFSET 3
+#define D0F0x64_x51_P2pDis_WIDTH 1
+#define D0F0x64_x51_P2pDis_MASK 0x8
+#define D0F0x64_x51_Reserved_15_4_OFFSET 4
+#define D0F0x64_x51_Reserved_15_4_WIDTH 12
+#define D0F0x64_x51_Reserved_15_4_MASK 0xfff0
+#define D0F0x64_x51_ExtDevPlug_OFFSET 16
+#define D0F0x64_x51_ExtDevPlug_WIDTH 1
+#define D0F0x64_x51_ExtDevPlug_MASK 0x10000
+#define D0F0x64_x51_ExtDevCrsEn_OFFSET 17
+#define D0F0x64_x51_ExtDevCrsEn_WIDTH 1
+#define D0F0x64_x51_ExtDevCrsEn_MASK 0x20000
+#define D0F0x64_x51_CrsEn_OFFSET 18
+#define D0F0x64_x51_CrsEn_WIDTH 1
+#define D0F0x64_x51_CrsEn_MASK 0x40000
+#define D0F0x64_x51_IntSelMode_OFFSET 19
+#define D0F0x64_x51_IntSelMode_WIDTH 1
+#define D0F0x64_x51_IntSelMode_MASK 0x80000
+#define D0F0x64_x51_SetPowEn_OFFSET 20
+#define D0F0x64_x51_SetPowEn_WIDTH 1
+#define D0F0x64_x51_SetPowEn_MASK 0x100000
+#define D0F0x64_x51_Reserved_31_21_OFFSET 21
+#define D0F0x64_x51_Reserved_31_21_WIDTH 11
+#define D0F0x64_x51_Reserved_31_21_MASK 0xffe00000
-/// D0F0xE4_CORE_0020
+/// D0F0x64_x51
typedef union {
struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 CiRcOrderingDis:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
+ UINT32 Reserved_2_0:3 ; ///<
+ UINT32 P2pDis:1 ; ///<
+ UINT32 Reserved_15_4:12; ///<
+ UINT32 ExtDevPlug:1 ; ///<
+ UINT32 ExtDevCrsEn:1 ; ///<
+ UINT32 CrsEn:1 ; ///<
+ UINT32 IntSelMode:1 ; ///<
+ UINT32 SetPowEn:1 ; ///<
+ UINT32 Reserved_31_21:11; ///<
+ } Field; ///<
UINT32 Value; ///<
-} D0F0xE4_CORE_0020_STRUCT;
+} D0F0x64_x51_STRUCT;
+
+// **** D0F0xE4_PHY_6440 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6440_ADDRESS 0x6440
+
+// Type
+#define D0F0xE4_PHY_6440_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6440_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6440_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6440_RxInCalForce_MASK 0x80
-// **** D0F0xE4_CORE_00B0 Register Definition ****
+// **** D0F0xE4_PHY_6480 Register Definition ****
// Address
-#define D0F0xE4_CORE_00B0_ADDRESS 0xb0
+#define D0F0xE4_PHY_6480_ADDRESS 0x6480
// Type
-#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4
+#define D0F0xE4_PHY_6480_TYPE TYPE_D0F0xE4
// Field Data
-#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0
-#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2
-#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3
-#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2
-#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1
-#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4
-#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3
-#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29
-#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8
+#define D0F0xE4_PHY_6480_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6480_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6480_RxInCalForce_MASK 0x80
-/// D0F0xE4_CORE_00B0
-typedef union {
- struct { ///<
- UINT32 Reserved_1_0:2 ; ///<
- UINT32 StrapF0MsiEn:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_00B0_STRUCT;
+// **** D0F0xE4_PHY_6500 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6500_ADDRESS 0x6500
-// **** D0F0x64_x1C Register Definition ****
+// Type
+#define D0F0xE4_PHY_6500_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6500_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6500_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6500_RxInCalForce_MASK 0x80
+
+// **** D0F0xE4_PHY_6600 Register Definition ****
// Address
-#define D0F0x64_x1C_ADDRESS 0x1c
+#define D0F0xE4_PHY_6600_ADDRESS 0x6600
// Type
-#define D0F0x64_x1C_TYPE TYPE_D0F0x64
+#define D0F0xE4_PHY_6600_TYPE TYPE_D0F0xE4
// Field Data
-#define D0F0x64_x1C_WriteDis_OFFSET 0
-#define D0F0x64_x1C_WriteDis_WIDTH 1
-#define D0F0x64_x1C_WriteDis_MASK 0x1
-#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1
-#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1
-#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2
-#define D0F0x64_x1C_Reserved_2_2_OFFSET 2
-#define D0F0x64_x1C_Reserved_2_2_WIDTH 1
-#define D0F0x64_x1C_Reserved_2_2_MASK 0x4
-#define D0F0x64_x1C_MemApSize_OFFSET 3
-#define D0F0x64_x1C_MemApSize_WIDTH 3
-#define D0F0x64_x1C_MemApSize_MASK 0x38
-#define D0F0x64_x1C_RegApSize_OFFSET 6
-#define D0F0x64_x1C_RegApSize_WIDTH 1
-#define D0F0x64_x1C_RegApSize_MASK 0x40
-#define D0F0x64_x1C_Reserved_7_7_OFFSET 7
-#define D0F0x64_x1C_Reserved_7_7_WIDTH 1
-#define D0F0x64_x1C_Reserved_7_7_MASK 0x80
-#define D0F0x64_x1C_AudioEn_OFFSET 8
-#define D0F0x64_x1C_AudioEn_WIDTH 1
-#define D0F0x64_x1C_AudioEn_MASK 0x100
-#define D0F0x64_x1C_Reserved_9_9_OFFSET 9
-#define D0F0x64_x1C_Reserved_9_9_WIDTH 1
-#define D0F0x64_x1C_Reserved_9_9_MASK 0x200
-#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10
-#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1
-#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400
-#define D0F0x64_x1C_Reserved_16_11_OFFSET 11
-#define D0F0x64_x1C_Reserved_16_11_WIDTH 6
-#define D0F0x64_x1C_Reserved_16_11_MASK 0x1f800
-#define D0F0x64_x1C_F0En_OFFSET 17
-#define D0F0x64_x1C_F0En_WIDTH 1
-#define D0F0x64_x1C_F0En_MASK 0x20000
-#define D0F0x64_x1C_Reserved_22_18_OFFSET 18
-#define D0F0x64_x1C_Reserved_22_18_WIDTH 5
-#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000
-#define D0F0x64_x1C_RcieEn_OFFSET 23
-#define D0F0x64_x1C_RcieEn_WIDTH 1
-#define D0F0x64_x1C_RcieEn_MASK 0x800000
-#define D0F0x64_x1C_Reserved_31_24_OFFSET 24
-#define D0F0x64_x1C_Reserved_31_24_WIDTH 8
-#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000
+#define D0F0xE4_PHY_6600_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6600_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6600_RxInCalForce_MASK 0x80
-/// D0F0x64_x1C
-typedef union {
- struct { ///<
- UINT32 WriteDis:1 ; ///<
- UINT32 F0NonlegacyDeviceTypeEn:1 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 MemApSize:3 ; ///<
- UINT32 RegApSize:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 AudioEn:1 ; ///<
- UINT32 Reserved_9_9:1 ; ///<
- UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///<
- UINT32 Reserved_16_11:6 ; ///<
- UINT32 F0En:1 ; ///<
- UINT32 Reserved_22_18:5 ; ///<
- UINT32 RcieEn:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x1C_STRUCT;
-// **** D18F2x0F4_x40 Register Definition ****
+// **** D0F0xE4_PHY_6840 Register Definition ****
// Address
-#define D18F2x0F4_x40_ADDRESS 0x40
+#define D0F0xE4_PHY_6840_ADDRESS 0x6840
// Type
-#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4
+#define D0F0xE4_PHY_6840_TYPE TYPE_D0F0xE4
// Field Data
-#define D18F2x0F4_x40_Trcd_OFFSET 0
-#define D18F2x0F4_x40_Trcd_WIDTH 4
-#define D18F2x0F4_x40_Trcd_MASK 0xf
-#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4
-#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4
-#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0
-#define D18F2x0F4_x40_Trp_OFFSET 8
-#define D18F2x0F4_x40_Trp_WIDTH 4
-#define D18F2x0F4_x40_Trp_MASK 0xf00
-#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12
-#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4
-#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000
-#define D18F2x0F4_x40_Tras_OFFSET 16
-#define D18F2x0F4_x40_Tras_WIDTH 5
-#define D18F2x0F4_x40_Tras_MASK 0x1f0000
-#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21
-#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3
-#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000
-#define D18F2x0F4_x40_Trc_OFFSET 24
-#define D18F2x0F4_x40_Trc_WIDTH 6
-#define D18F2x0F4_x40_Trc_MASK 0x3f000000
-#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30
-#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2
-#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000
+#define D0F0xE4_PHY_6840_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6840_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6840_RxInCalForce_MASK 0x80
-/// D18F2x0F4_x40
-typedef union {
- struct { ///<
- UINT32 Trcd:4 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 Trp:4 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 Tras:5 ; ///<
- UINT32 Reserved_23_21:3 ; ///<
- UINT32 Trc:6 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x0F4_x40_STRUCT;
-// **** D18F2x0F4_x41 Register Definition ****
+// **** D0F0xE4_PHY_6880 Register Definition ****
// Address
-#define D18F2x0F4_x41_ADDRESS 0x41
+#define D0F0xE4_PHY_6880_ADDRESS 0x6880
// Type
-#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4
+#define D0F0xE4_PHY_6880_TYPE TYPE_D0F0xE4
// Field Data
-#define D18F2x0F4_x41_Trtp_OFFSET 0
-#define D18F2x0F4_x41_Trtp_WIDTH 3
-#define D18F2x0F4_x41_Trtp_MASK 0x7
-#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3
-#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5
-#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8
-#define D18F2x0F4_x41_Trrd_OFFSET 8
-#define D18F2x0F4_x41_Trrd_WIDTH 3
-#define D18F2x0F4_x41_Trrd_MASK 0x700
-#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11
-#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5
-#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800
-#define D18F2x0F4_x41_Twtr_OFFSET 16
-#define D18F2x0F4_x41_Twtr_WIDTH 3
-#define D18F2x0F4_x41_Twtr_MASK 0x70000
-#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19
-#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13
-#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000
+#define D0F0xE4_PHY_6880_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6880_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6880_RxInCalForce_MASK 0x80
-/// D18F2x0F4_x41
-typedef union {
- struct { ///<
- UINT32 Trtp:3 ; ///<
- UINT32 Reserved_7_3:5 ; ///<
- UINT32 Trrd:3 ; ///<
- UINT32 Reserved_15_11:5 ; ///<
- UINT32 Twtr:3 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x0F4_x41_STRUCT;
+// **** D0F0xE4_PHY_6900 Register Definition ****
+// Address
+#define D0F0xE4_PHY_6900_ADDRESS 0x6900
+
+// Type
+#define D0F0xE4_PHY_6900_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6900_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6900_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6900_RxInCalForce_MASK 0x80
-// **** D18F2x0F0 Register Definition ****
+// **** D0F0xE4_PHY_6A00 Register Definition ****
// Address
-#define D18F2x0F0_ADDRESS 0xf0
+#define D0F0xE4_PHY_6A00_ADDRESS 0x6a00
+// Type
+#define D0F0xE4_PHY_6A00_TYPE TYPE_D0F0xE4
+// Field Data
+#define D0F0xE4_PHY_6A00_RxInCalForce_OFFSET 7
+#define D0F0xE4_PHY_6A00_RxInCalForce_WIDTH 1
+#define D0F0xE4_PHY_6A00_RxInCalForce_MASK 0x80
-// **** D18F2x1F0 Register Definition ****
+// **** D0F0x64_x20 Register Definition ****
// Address
-#define D18F2x1F0_ADDRESS 0x1f0
+#define D0F0x64_x20_ADDRESS 0x20
+// Type
+#define D0F0x64_x20_TYPE TYPE_D0F0x64
+// Field Data
+#define D0F0x64_x20_IocPcieDevRemapDis_OFFSET 1
+#define D0F0x64_x20_IocPcieDevRemapDis_WIDTH 1
+#define D0F0x64_x20_IocPcieDevRemapDis_MASK 0x2
-// **** D18F2x184 Register Definition ****
+// **** SMUx33 Register Definition ****
// Address
-#define D18F2x184_ADDRESS 0x184
+#define SMUx33_ADDRESS 0x33
+// Type
+#define SMUx33_TYPE TYPE_SMU
+// Field Data
+#define SMUx33_LclkActMonPrd_OFFSET 0
+#define SMUx33_LclkActMonPrd_WIDTH 16
+#define SMUx33_LclkActMonPrd_MASK 0xffff
+#define SMUx33_LclkActMonUnt_OFFSET 16
+#define SMUx33_LclkActMonUnt_WIDTH 4
+#define SMUx33_LclkActMonUnt_MASK 0xf0000
+#define SMUx33_TrendMode_OFFSET 20
+#define SMUx33_TrendMode_WIDTH 1
+#define SMUx33_TrendMode_MASK 0x100000
+#define SMUx33_ForceTrend_OFFSET 21
+#define SMUx33_ForceTrend_WIDTH 1
+#define SMUx33_ForceTrend_MASK 0x200000
+#define SMUx33_ActMonRst_OFFSET 22
+#define SMUx33_ActMonRst_WIDTH 1
+#define SMUx33_ActMonRst_MASK 0x400000
+#define SMUx33_BusyCntSel_OFFSET 23
+#define SMUx33_BusyCntSel_WIDTH 2
+#define SMUx33_BusyCntSel_MASK 0x1800000
+#define SMUx33_AccessCntl_OFFSET 25
+#define SMUx33_AccessCntl_WIDTH 1
+#define SMUx33_AccessCntl_MASK 0x2000000
+#define SMUx33_Reserved_31_26_OFFSET 26
+#define SMUx33_Reserved_31_26_WIDTH 6
+#define SMUx33_Reserved_31_26_MASK 0xfc000000
-// **** D18F2x094 Register Definition ****
-// Address
-#define D18F2x094_ADDRESS 0x94
-
-// Type
-#define D18F2x094_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x094_MemClkFreq_OFFSET 0
-#define D18F2x094_MemClkFreq_WIDTH 5
-#define D18F2x094_MemClkFreq_MASK 0x1f
-#define D18F2x094_Reserved_6_5_OFFSET 5
-#define D18F2x094_Reserved_6_5_WIDTH 2
-#define D18F2x094_Reserved_6_5_MASK 0x60
-#define D18F2x094_MemClkFreqVal_OFFSET 7
-#define D18F2x094_MemClkFreqVal_WIDTH 1
-#define D18F2x094_MemClkFreqVal_MASK 0x80
-#define D18F2x094_Reserved_9_8_OFFSET 8
-#define D18F2x094_Reserved_9_8_WIDTH 2
-#define D18F2x094_Reserved_9_8_MASK 0x300
-#define D18F2x094_ZqcsInterval_OFFSET 10
-#define D18F2x094_ZqcsInterval_WIDTH 2
-#define D18F2x094_ZqcsInterval_MASK 0xc00
-#define D18F2x094_Reserved_13_12_OFFSET 12
-#define D18F2x094_Reserved_13_12_WIDTH 2
-#define D18F2x094_Reserved_13_12_MASK 0x3000
-#define D18F2x094_DisDramInterface_OFFSET 14
-#define D18F2x094_DisDramInterface_WIDTH 1
-#define D18F2x094_DisDramInterface_MASK 0x4000
-#define D18F2x094_PowerDownEn_OFFSET 15
-#define D18F2x094_PowerDownEn_WIDTH 1
-#define D18F2x094_PowerDownEn_MASK 0x8000
-#define D18F2x094_PowerDownMode_OFFSET 16
-#define D18F2x094_PowerDownMode_WIDTH 1
-#define D18F2x094_PowerDownMode_MASK 0x10000
-#define D18F2x094_Reserved_19_17_OFFSET 17
-#define D18F2x094_Reserved_19_17_WIDTH 3
-#define D18F2x094_Reserved_19_17_MASK 0xe0000
-#define D18F2x094_SlowAccessMode_OFFSET 20
-#define D18F2x094_SlowAccessMode_WIDTH 1
-#define D18F2x094_SlowAccessMode_MASK 0x100000
-#define D18F2x094_Reserved_21_21_OFFSET 21
-#define D18F2x094_Reserved_21_21_WIDTH 1
-#define D18F2x094_Reserved_21_21_MASK 0x200000
-#define D18F2x094_BankSwizzleMode_OFFSET 22
-#define D18F2x094_BankSwizzleMode_WIDTH 1
-#define D18F2x094_BankSwizzleMode_MASK 0x400000
-#define D18F2x094_ProcOdtDis_OFFSET 23
-#define D18F2x094_ProcOdtDis_WIDTH 1
-#define D18F2x094_ProcOdtDis_MASK 0x800000
-#define D18F2x094_DcqBypassMax_OFFSET 24
-#define D18F2x094_DcqBypassMax_WIDTH 4
-#define D18F2x094_DcqBypassMax_MASK 0xf000000
-#define D18F2x094_FourActWindow_OFFSET 28
-#define D18F2x094_FourActWindow_WIDTH 4
-#define D18F2x094_FourActWindow_MASK 0xf0000000
-
-/// D18F2x094
+/// SMUx33
typedef union {
struct { ///<
- UINT32 MemClkFreq:5 ; ///<
- UINT32 Reserved_6_5:2 ; ///<
- UINT32 MemClkFreqVal:1 ; ///<
- UINT32 Reserved_9_8:2 ; ///<
- UINT32 ZqcsInterval:2 ; ///<
- UINT32 Reserved_13_12:2 ; ///<
- UINT32 DisDramInterface:1 ; ///<
- UINT32 PowerDownEn:1 ; ///<
- UINT32 PowerDownMode:1 ; ///<
- UINT32 Reserved_19_17:3 ; ///<
- UINT32 SlowAccessMode:1 ; ///<
- UINT32 Reserved_21_21:1 ; ///<
- UINT32 BankSwizzleMode:1 ; ///<
- UINT32 ProcOdtDis:1 ; ///<
- UINT32 DcqBypassMax:4 ; ///<
- UINT32 FourActWindow:4 ; ///<
+ UINT32 LclkActMonPrd:16; ///<
+ UINT32 LclkActMonUnt:4 ; ///<
+ UINT32 TrendMode:1 ; ///<
+ UINT32 ForceTrend:1 ; ///<
+ UINT32 ActMonRst:1 ; ///<
+ UINT32 BusyCntSel:2 ; ///<
+ UINT32 AccessCntl:1 ; ///<
+ UINT32 Reserved_31_26:6 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x094_STRUCT;
+} SMUx33_STRUCT;
-// **** D18F2x194 Register Definition ****
+// **** SMUx0B_x8434 Register Definition ****
// Address
-#define D18F2x194_ADDRESS 0x194
+#define SMUx0B_x8434_ADDRESS 0x8434
+
+// Type
+#define SMUx0B_x8434_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x8434_LclkDpmEn_OFFSET 0
+#define SMUx0B_x8434_LclkDpmEn_WIDTH 1
+#define SMUx0B_x8434_LclkDpmEn_MASK 0x1
+#define SMUx0B_x8434_LclkDpmType_OFFSET 1
+#define SMUx0B_x8434_LclkDpmType_WIDTH 1
+#define SMUx0B_x8434_LclkDpmType_MASK 0x2
+#define SMUx0B_x8434_Reserved_3_2_OFFSET 2
+#define SMUx0B_x8434_Reserved_3_2_WIDTH 2
+#define SMUx0B_x8434_Reserved_3_2_MASK 0xc
+#define SMUx0B_x8434_LclkTimerPrescalar_OFFSET 4
+#define SMUx0B_x8434_LclkTimerPrescalar_WIDTH 4
+#define SMUx0B_x8434_LclkTimerPrescalar_MASK 0xf0
+#define SMUx0B_x8434_Reserved_15_8_OFFSET 8
+#define SMUx0B_x8434_Reserved_15_8_WIDTH 8
+#define SMUx0B_x8434_Reserved_15_8_MASK 0xff00
+#define SMUx0B_x8434_LclkTimerPeriod_OFFSET 16
+#define SMUx0B_x8434_LclkTimerPeriod_WIDTH 16
+#define SMUx0B_x8434_LclkTimerPeriod_MASK 0xffff0000
+/// SMUx0B_x8434
+typedef union {
+ struct { ///<
+ UINT32 LclkDpmEn:1 ; ///<
+ UINT32 LclkDpmType:1 ; ///<
+ UINT32 Reserved_3_2:2 ; ///<
+ UINT32 LclkTimerPrescalar:4 ; ///<
+ UINT32 Reserved_15_8:8 ; ///<
+ UINT32 LclkTimerPeriod:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x8434_STRUCT;
-// **** D18F2x18C Register Definition ****
+// **** FCRxFF30_01E4 Register Definition ****
// Address
-#define D18F2x18C_ADDRESS 0x18c
+#define FCRxFF30_01E4_ADDRESS 0xff3001e4
+// Type
+#define FCRxFF30_01E4_TYPE TYPE_FCR
+// Field Data
+#define FCRxFF30_01E4_Fraction_OFFSET 0
+#define FCRxFF30_01E4_Fraction_WIDTH 8
+#define FCRxFF30_01E4_Fraction_MASK 0xff
+#define FCRxFF30_01E4_Hysteresis_OFFSET 8
+#define FCRxFF30_01E4_Hysteresis_WIDTH 12
+#define FCRxFF30_01E4_Hysteresis_MASK 0xfff00
+#define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20
+#define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1
+#define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000
+#define FCRxFF30_01E4_Reserved_31_21_OFFSET 21
+#define FCRxFF30_01E4_Reserved_31_21_WIDTH 11
+#define FCRxFF30_01E4_Reserved_31_21_MASK 0xffe00000
-// **** D18F2x190 Register Definition ****
+/// FCRxFF30_01E4
+typedef union {
+ struct { ///<
+ UINT32 Fraction:8 ; ///<
+ UINT32 Hysteresis:12; ///<
+ UINT32 VoltageChangeEn:1 ; ///<
+ UINT32 Reserved_31_21:11; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} FCRxFF30_01E4_STRUCT;
+// **** SMUx0B_x84AC Register Definition ****
// Address
-#define D18F2x190_ADDRESS 0x190
+#define SMUx0B_x84AC_ADDRESS 0x84ac
+// Type
+#define SMUx0B_x84AC_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x84AC_FstateCredits_1_OFFSET 0
+#define SMUx0B_x84AC_FstateCredits_1_WIDTH 16
+#define SMUx0B_x84AC_FstateCredits_1_MASK 0xffff
+#define SMUx0B_x84AC_FstateCredits_0_OFFSET 16
+#define SMUx0B_x84AC_FstateCredits_0_WIDTH 16
+#define SMUx0B_x84AC_FstateCredits_0_MASK 0xffff0000
-// **** D18F2x098 Register Definition ****
-// Address
-#define D18F2x098_ADDRESS 0x98
-
+/// SMUx0B_x84AC
+typedef union {
+ struct { ///<
+ UINT32 FstateCredits_1:16; ///<
+ UINT32 FstateCredits_0:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x84AC_STRUCT;
-// **** D18F2x198 Register Definition ****
+// **** SMUx0B_x848C Register Definition ****
// Address
-#define D18F2x198_ADDRESS 0x198
+#define SMUx0B_x848C_ADDRESS 0x848c
+// Type
+#define SMUx0B_x848C_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x848C_FstateDiv_7_OFFSET 0
+#define SMUx0B_x848C_FstateDiv_7_WIDTH 7
+#define SMUx0B_x848C_FstateDiv_7_MASK 0x7f
+#define SMUx0B_x848C_Reserved_7_7_OFFSET 7
+#define SMUx0B_x848C_Reserved_7_7_WIDTH 1
+#define SMUx0B_x848C_Reserved_7_7_MASK 0x80
+#define SMUx0B_x848C_FstateDiv_6_OFFSET 8
+#define SMUx0B_x848C_FstateDiv_6_WIDTH 7
+#define SMUx0B_x848C_FstateDiv_6_MASK 0x7f00
+#define SMUx0B_x848C_Reserved_15_15_OFFSET 15
+#define SMUx0B_x848C_Reserved_15_15_WIDTH 1
+#define SMUx0B_x848C_Reserved_15_15_MASK 0x8000
+#define SMUx0B_x848C_FstateDiv_5_OFFSET 16
+#define SMUx0B_x848C_FstateDiv_5_WIDTH 7
+#define SMUx0B_x848C_FstateDiv_5_MASK 0x7f0000
+#define SMUx0B_x848C_Reserved_23_23_OFFSET 23
+#define SMUx0B_x848C_Reserved_23_23_WIDTH 1
+#define SMUx0B_x848C_Reserved_23_23_MASK 0x800000
+#define SMUx0B_x848C_FstateDiv_4_OFFSET 24
+#define SMUx0B_x848C_FstateDiv_4_WIDTH 7
+#define SMUx0B_x848C_FstateDiv_4_MASK 0x7f000000
+#define SMUx0B_x848C_Reserved_31_31_OFFSET 31
+#define SMUx0B_x848C_Reserved_31_31_WIDTH 1
+#define SMUx0B_x848C_Reserved_31_31_MASK 0x80000000
+
+/// SMUx0B_x848C
+typedef union {
+ struct { ///<
+ UINT32 FstateDiv_7:7 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 FstateDiv_6:7 ; ///<
+ UINT32 Reserved_15_15:1 ; ///<
+ UINT32 FstateDiv_5:7 ; ///<
+ UINT32 Reserved_23_23:1 ; ///<
+ UINT32 FstateDiv_4:7 ; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x848C_STRUCT;
-// **** D18F2x09C_x0D0FE00A Register Definition ****
+// **** SMUx0B_x8470 Register Definition ****
// Address
-#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A
+#define SMUx0B_x8470_ADDRESS 0x8470
// Type
-#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C
+#define SMUx0B_x8470_TYPE TYPE_SMUx0B
// Field Data
-#define D18F2x09C_x0D0FE00A_Reserved_11_0_OFFSET 0
-#define D18F2x09C_x0D0FE00A_Reserved_11_0_WIDTH 12
-#define D18F2x09C_x0D0FE00A_Reserved_11_0_MASK 0xfff
-#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12
-#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2
-#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000
-#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14
-#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1
-#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000
-#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15
-#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17
-#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000
+#define SMUx0B_x8470_Raising_OFFSET 0
+#define SMUx0B_x8470_Raising_WIDTH 16
+#define SMUx0B_x8470_Raising_MASK 0xffff
+#define SMUx0B_x8470_Lowering_OFFSET 16
+#define SMUx0B_x8470_Lowering_WIDTH 16
+#define SMUx0B_x8470_Lowering_MASK 0xffff0000
-/// D18F2x09C_x0D0FE00A
+/// SMUx0B_x8470
typedef union {
struct { ///<
- UINT32 Reserved_11_0:12; ///<
- UINT32 CsrPhySrPllPdMode:2; ///<
- UINT32 SelCsrPllPdMode:1; ///<
- UINT32 Reserved_31_15:17; ///<
+ UINT32 Raising:16; ///<
+ UINT32 Lowering:16; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F2x09C_x0D0FE00A_STRUCT;
+} SMUx0B_x8470_STRUCT;
-// **** GMMx201C Register Definition ****
+// **** SMUx0B_x8440 Register Definition ****
// Address
-#define GMMx201C_ADDRESS 0x201c
+#define SMUx0B_x8440_ADDRESS 0x8440
+// Type
+#define SMUx0B_x8440_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x8440_FstatePeriod_5_OFFSET 0
+#define SMUx0B_x8440_FstatePeriod_5_WIDTH 16
+#define SMUx0B_x8440_FstatePeriod_5_MASK 0xffff
+#define SMUx0B_x8440_FstatePeriod_4_OFFSET 16
+#define SMUx0B_x8440_FstatePeriod_4_WIDTH 16
+#define SMUx0B_x8440_FstatePeriod_4_MASK 0xffff0000
-// **** GMMx217C Register Definition ****
-// Address
-#define GMMx217C_ADDRESS 0x217c
+/// SMUx0B_x8440
+typedef union {
+ struct { ///<
+ UINT32 FstatePeriod_5:16; ///<
+ UINT32 FstatePeriod_4:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x8440_STRUCT;
-// **** GMMx2188 Register Definition ****
+// **** SMUx51 Register Definition ****
// Address
-#define GMMx2188_ADDRESS 0x2188
-
+#define SMUx51_ADDRESS 0x51
-// **** GMMx28C8 Register Definition ****
-// Address
-#define GMMx28C8_ADDRESS 0x28c8
+// Type
+#define SMUx51_TYPE TYPE_SMU
+// Field Data
+#define SMUx51_DownTrendCoef_OFFSET 0
+#define SMUx51_DownTrendCoef_WIDTH 10
+#define SMUx51_DownTrendCoef_MASK 0x3ff
+#define SMUx51_UpTrendCoef_OFFSET 10
+#define SMUx51_UpTrendCoef_WIDTH 10
+#define SMUx51_UpTrendCoef_MASK 0xffc00
+#define SMUx51_Reserved_31_20_OFFSET 20
+#define SMUx51_Reserved_31_20_WIDTH 12
+#define SMUx51_Reserved_31_20_MASK 0xfff00000
+/// SMUx51
+typedef union {
+ struct { ///<
+ UINT32 DownTrendCoef:10; ///<
+ UINT32 UpTrendCoef:10; ///<
+ UINT32 Reserved_31_20:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx51_STRUCT;
-// **** SMUx01 Register Definition ****
+// **** FCRxFE00_70A2 Register Definition ****
// Address
-#define SMUx01_ADDRESS 0x1
+#define FCRxFE00_70A2_ADDRESS 0xfe0070a2
// Type
-#define SMUx01_TYPE TYPE_SMU
+#define FCRxFE00_70A2_TYPE TYPE_FCR
// Field Data
-#define SMUx01_RamSwitch_OFFSET 0
-#define SMUx01_RamSwitch_WIDTH 1
-#define SMUx01_RamSwitch_MASK 0x1
-#define SMUx01_Reset_OFFSET 1
-#define SMUx01_Reset_WIDTH 1
-#define SMUx01_Reset_MASK 0x2
-#define SMUx01_Reserved_17_2_OFFSET 2
-#define SMUx01_Reserved_17_2_WIDTH 16
-#define SMUx01_Reserved_17_2_MASK 0x3fffc
-#define SMUx01_VectorOverride_OFFSET 18
-#define SMUx01_VectorOverride_WIDTH 1
-#define SMUx01_VectorOverride_MASK 0x40000
-#define SMUx01_Reserved_31_19_OFFSET 19
-#define SMUx01_Reserved_31_19_WIDTH 13
-#define SMUx01_Reserved_31_19_MASK 0xfff80000
-//
-/// SMUx01
+#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0
+#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7
+#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f
+#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7
+#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4
+#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780
+#define FCRxFE00_70A2_SclkThermDid_OFFSET 11
+#define FCRxFE00_70A2_SclkThermDid_WIDTH 7
+#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800
+#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18
+#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2
+#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000
+#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20
+#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12
+#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000
+
+/// FCRxFE00_70A2
typedef union {
struct { ///<
- UINT32 RamSwitch:1 ; ///<
- UINT32 Reset:1 ; ///<
- UINT32 Reserved_17_2:16; ///<
- UINT32 VectorOverride:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
+ UINT32 Reserved_6_0:7 ; ///<
+ UINT32 PPlayTableRev:4 ; ///<
+ UINT32 SclkThermDid:7 ; ///<
+ UINT32 PcieGen2Vid:2 ; ///<
+ UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx01_STRUCT;
+} FCRxFE00_70A2_STRUCT;
// **** FCRxFE00_70A4 Register Definition ****
// Address
UINT32 Value; ///<
} FCRxFE00_70C7_STRUCT;
-// **** FCRxFE00_70A2 Register Definition ****
+// **** SMUx0B_x8490 Register Definition ****
// Address
-#define FCRxFE00_70A2_ADDRESS 0xfe0070a2
+#define SMUx0B_x8490_ADDRESS 0x8490
// Type
-#define FCRxFE00_70A2_TYPE TYPE_FCR
+#define SMUx0B_x8490_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x8490_LclkState0Valid_OFFSET 0
+#define SMUx0B_x8490_LclkState0Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState0Valid_MASK 0x1
+#define SMUx0B_x8490_LclkState1Valid_OFFSET 1
+#define SMUx0B_x8490_LclkState1Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState1Valid_MASK 0x2
+#define SMUx0B_x8490_LclkState2Valid_OFFSET 2
+#define SMUx0B_x8490_LclkState2Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState2Valid_MASK 0x4
+#define SMUx0B_x8490_LclkState3Valid_OFFSET 3
+#define SMUx0B_x8490_LclkState3Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState3Valid_MASK 0x8
+#define SMUx0B_x8490_LclkState4Valid_OFFSET 4
+#define SMUx0B_x8490_LclkState4Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState4Valid_MASK 0x10
+#define SMUx0B_x8490_LclkState5Valid_OFFSET 5
+#define SMUx0B_x8490_LclkState5Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState5Valid_MASK 0x20
+#define SMUx0B_x8490_LclkState6Valid_OFFSET 6
+#define SMUx0B_x8490_LclkState6Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState6Valid_MASK 0x40
+#define SMUx0B_x8490_LclkState7Valid_OFFSET 7
+#define SMUx0B_x8490_LclkState7Valid_WIDTH 1
+#define SMUx0B_x8490_LclkState7Valid_MASK 0x80
+#define SMUx0B_x8490_LclkDivTtExit_OFFSET 8
+#define SMUx0B_x8490_LclkDivTtExit_WIDTH 8
+#define SMUx0B_x8490_LclkDivTtExit_MASK 0xff00
+#define SMUx0B_x8490_MinDivAllowed_OFFSET 16
+#define SMUx0B_x8490_MinDivAllowed_WIDTH 8
+#define SMUx0B_x8490_MinDivAllowed_MASK 0xff0000
+#define SMUx0B_x8490_Reserved_31_24_OFFSET 24
+#define SMUx0B_x8490_Reserved_31_24_WIDTH 8
+#define SMUx0B_x8490_Reserved_31_24_MASK 0xff000000
+
+/// SMUx0B_x8490
+typedef union {
+ struct { ///<
+ UINT32 LclkState0Valid:1 ; ///<
+ UINT32 LclkState1Valid:1 ; ///<
+ UINT32 LclkState2Valid:1 ; ///<
+ UINT32 LclkState3Valid:1 ; ///<
+ UINT32 LclkState4Valid:1 ; ///<
+ UINT32 LclkState5Valid:1 ; ///<
+ UINT32 LclkState6Valid:1 ; ///<
+ UINT32 LclkState7Valid:1 ; ///<
+ UINT32 LclkDivTtExit:8 ; ///<
+ UINT32 MinDivAllowed:8 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x8490_STRUCT;
+
+// **** SMUx35 Register Definition ****
+// Address
+#define SMUx35_ADDRESS 0x35
+
+// Type
+#define SMUx35_TYPE TYPE_SMU
// Field Data
-#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0
-#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7
-#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f
-#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7
-#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4
-#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780
-#define FCRxFE00_70A2_SclkThermDid_OFFSET 11
-#define FCRxFE00_70A2_SclkThermDid_WIDTH 7
-#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800
-#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18
-#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2
-#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000
-#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20
-#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12
-#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000
+#define SMUx35_DownTrendCoef_OFFSET 0
+#define SMUx35_DownTrendCoef_WIDTH 10
+#define SMUx35_DownTrendCoef_MASK 0x3ff
+#define SMUx35_UpTrendCoef_OFFSET 10
+#define SMUx35_UpTrendCoef_WIDTH 10
+#define SMUx35_UpTrendCoef_MASK 0xffc00
+#define SMUx35_Reserved_31_20_OFFSET 20
+#define SMUx35_Reserved_31_20_WIDTH 12
+#define SMUx35_Reserved_31_20_MASK 0xfff00000
-/// FCRxFE00_70A2
+/// SMUx35
typedef union {
struct { ///<
- UINT32 Reserved_6_0:7 ; ///<
- UINT32 PPlayTableRev:4 ; ///<
- UINT32 SclkThermDid:7 ; ///<
- UINT32 PcieGen2Vid:2 ; ///<
+ UINT32 DownTrendCoef:10; ///<
+ UINT32 UpTrendCoef:10; ///<
UINT32 Reserved_31_20:12; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFE00_70A2_STRUCT;
+} SMUx35_STRUCT;
+
+// **** SMUx37 Register Definition ****
+// Address
+#define SMUx37_ADDRESS 0x37
+
+// Type
+#define SMUx37_TYPE TYPE_SMU
+// Field Data
+#define SMUx37_DownTrendCoef_OFFSET 0
+#define SMUx37_DownTrendCoef_WIDTH 10
+#define SMUx37_DownTrendCoef_MASK 0x3ff
+#define SMUx37_UpTrendCoef_OFFSET 10
+#define SMUx37_UpTrendCoef_WIDTH 10
+#define SMUx37_UpTrendCoef_MASK 0xffc00
+#define SMUx37_Reserved_31_20_OFFSET 20
+#define SMUx37_Reserved_31_20_WIDTH 12
+#define SMUx37_Reserved_31_20_MASK 0xfff00000
+
+/// SMUx37
+typedef union {
+ struct { ///<
+ UINT32 DownTrendCoef:10; ///<
+ UINT32 UpTrendCoef:10; ///<
+ UINT32 Reserved_31_20:12; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx37_STRUCT;
// **** FCRxFE00_70AA Register Definition ****
// Address
UINT32 Value; ///<
} FCRxFE00_70AA_STRUCT;
-// **** D18F3xD4 Register Definition ****
+// **** FCRxFE00_70C8 Register Definition ****
// Address
-#define D18F3xD4_ADDRESS 0xd4
+#define FCRxFE00_70C8_ADDRESS 0xfe0070c8
// Type
-#define D18F3xD4_TYPE TYPE_D18F3
+#define FCRxFE00_70C8_TYPE TYPE_FCR
// Field Data
-#define D18F3xD4_MainPllOpFreqId_OFFSET 0
-#define D18F3xD4_MainPllOpFreqId_WIDTH 6
-#define D18F3xD4_MainPllOpFreqId_MASK 0x3f
-#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6
-#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1
-#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40
-#define D18F3xD4_Reserved_7_7_OFFSET 7
-#define D18F3xD4_Reserved_7_7_WIDTH 1
-#define D18F3xD4_Reserved_7_7_MASK 0x80
-#define D18F3xD4_ClkRampHystSel_OFFSET 8
-#define D18F3xD4_ClkRampHystSel_WIDTH 4
-#define D18F3xD4_ClkRampHystSel_MASK 0xf00
-#define D18F3xD4_OnionOutHyst_OFFSET 12
-#define D18F3xD4_OnionOutHyst_WIDTH 4
-#define D18F3xD4_OnionOutHyst_MASK 0xf000
-#define D18F3xD4_DisNclkGatingIdle_OFFSET 16
-#define D18F3xD4_DisNclkGatingIdle_WIDTH 1
-#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000
-#define D18F3xD4_ClockGatingEnDram_OFFSET 17
-#define D18F3xD4_ClockGatingEnDram_WIDTH 1
-#define D18F3xD4_ClockGatingEnDram_MASK 0x20000
-#define D18F3xD4_Reserved_31_18_OFFSET 18
-#define D18F3xD4_Reserved_31_18_WIDTH 14
-#define D18F3xD4_Reserved_31_18_MASK 0xfffc0000
+#define FCRxFE00_70C8_Reserved_4_0_OFFSET 0
+#define FCRxFE00_70C8_Reserved_4_0_WIDTH 5
+#define FCRxFE00_70C8_Reserved_4_0_MASK 0x1f
+#define FCRxFE00_70C8_GpuBoostCap_OFFSET 5
+#define FCRxFE00_70C8_GpuBoostCap_WIDTH 1
+#define FCRxFE00_70C8_GpuBoostCap_MASK 0x20
+#define FCRxFE00_70C8_SclkDpmDid5_OFFSET 6
+#define FCRxFE00_70C8_SclkDpmDid5_WIDTH 7
+#define FCRxFE00_70C8_SclkDpmDid5_MASK 0x00001fc0
+#define FCRxFE00_70C8_SclkDpmVid5_OFFSET 13
+#define FCRxFE00_70C8_SclkDpmVid5_WIDTH 2
+#define FCRxFE00_70C8_SclkDpmVid5_MASK 0x00060000
+#define FCRxFE00_70C8_Reserved_31_15_OFFSET 15
+#define FCRxFE00_70C8_Reserved_31_15_WIDTH 17
+#define FCRxFE00_70C8_Reserved_31_15_MASK 0xffff8000
-/// D18F3xD4
+/// FCRxFE00_70C8
typedef union {
struct { ///<
- UINT32 MainPllOpFreqId:6 ; ///<
- UINT32 MainPllOpFreqIdEn:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 ClkRampHystSel:4 ; ///<
- UINT32 OnionOutHyst:4 ; ///<
- UINT32 DisNclkGatingIdle:1 ; ///<
- UINT32 ClockGatingEnDram:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
+ UINT32 Reserved_4_0:5 ; ///<
+ UINT32 GpuBoostCap:1 ; ///<
+ UINT32 SclkDpmDid5:7 ; ///<
+ UINT32 SclkDpmVid5:2 ; ///<
+ UINT32 Reserved_31_15:17; ///<
} Field; ///<
UINT32 Value; ///<
-} D18F3xD4_STRUCT;
+} FCRxFE00_70C8_STRUCT;
-// **** FCRxFF30_01F4 Register Definition ****
+// **** FCRxFE00_70C9 Register Definition ****
+// Address
+#define FCRxFE00_70C9_ADDRESS 0xfe0070c9
+
+// Type
+#define FCRxFE00_70C9_TYPE TYPE_FCR
+// Field Data
+#define FCRxFE00_70C9_Reserved_6_0_OFFSET 0
+#define FCRxFE00_70C9_Reserved_6_0_WIDTH 7
+#define FCRxFE00_70C9_Reserved_6_0_MASK 0x7f
+#define FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET 7
+#define FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH 12
+#define FCRxFE00_70C9_SclkDpmTdpLimit0_MASK 0x7ff80
+#define FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET 19
+#define FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH 12
+#define FCRxFE00_70C9_SclkDpmTdpLimit1_MASK 0x7ff80000
+#define FCRxFE00_70C9_Reserved_31_31_OFFSET 31
+#define FCRxFE00_70C9_Reserved_31_31_WIDTH 1
+#define FCRxFE00_70C9_Reserved_31_31_MASK 0x80000000
+
+/// FCRxFE00_70C9
+typedef union {
+ struct { ///<
+ UINT32 Reserved_6_0:7 ; ///<
+ UINT32 SclkDpmTdpLimit0:12; ///<
+ UINT32 SclkDpmTdpLimit1:12; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} FCRxFE00_70C9_STRUCT;
+
+// **** FCRxFE00_70CC Register Definition ****
+// Address
+#define FCRxFE00_70CC_ADDRESS 0xfe0070cc
+
+// Type
+#define FCRxFE00_70CC_TYPE TYPE_FCR
+// Field Data
+#define FCRxFE00_70CC_Reserved_6_0_OFFSET 0
+#define FCRxFE00_70CC_Reserved_6_0_WIDTH 7
+#define FCRxFE00_70CC_Reserved_6_0_MASK 0x7f
+#define FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET 7
+#define FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH 12
+#define FCRxFE00_70CC_SclkDpmTdpLimit2_MASK 0x7ff80
+#define FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET 19
+#define FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH 12
+#define FCRxFE00_70CC_SclkDpmTdpLimit3_MASK 0x7ff80000
+#define FCRxFE00_70CC_Reserved_31_31_OFFSET 31
+#define FCRxFE00_70CC_Reserved_31_31_WIDTH 1
+#define FCRxFE00_70CC_Reserved_31_31_MASK 0x80000000
+
+/// FCRxFE00_70CC
+typedef union {
+ struct { ///<
+ UINT32 Reserved_6_0:7 ; ///<
+ UINT32 SclkDpmTdpLimit2:12; ///<
+ UINT32 SclkDpmTdpLimit3:12; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} FCRxFE00_70CC_STRUCT;
+
+// **** FCRxFE00_70CF Register Definition ****
+// Address
+#define FCRxFE00_70CF_ADDRESS 0xfe0070cf
+
+// Type
+#define FCRxFE00_70CF_TYPE TYPE_FCR
+// Field Data
+#define FCRxFE00_70CF_Reserved_6_0_OFFSET 0
+#define FCRxFE00_70CF_Reserved_6_0_WIDTH 7
+#define FCRxFE00_70CF_Reserved_6_0_MASK 0x7f
+#define FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET 7
+#define FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH 12
+#define FCRxFE00_70CF_SclkDpmTdpLimit4_MASK 0x7ff80
+#define FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET 19
+#define FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH 12
+#define FCRxFE00_70CF_SclkDpmTdpLimit5_MASK 0x7ff80000
+#define FCRxFE00_70CF_Reserved_31_31_OFFSET 31
+#define FCRxFE00_70CF_Reserved_31_31_WIDTH 1
+#define FCRxFE00_70CF_Reserved_31_31_MASK 0x80000000
+
+/// FCRxFE00_70CF
+typedef union {
+ struct { ///<
+ UINT32 Reserved_6_0:7 ; ///<
+ UINT32 SclkDpmTdpLimit4:12; ///<
+ UINT32 SclkDpmTdpLimit5:12; ///<
+ UINT32 Reserved_31_31:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} FCRxFE00_70CF_STRUCT;
+
+// **** FCRxFE00_70D2 Register Definition ****
// Address
-#define FCRxFF30_01F4_ADDRESS 0xff3001f4
+#define FCRxFE00_70D2_ADDRESS 0xfe0070d2
// Type
-#define FCRxFF30_01F4_TYPE TYPE_FCR
+#define FCRxFE00_70D2_TYPE TYPE_FCR
// Field Data
-#define FCRxFF30_01F4_ReservedCgttSclk_21_0_OFFSET 0
-#define FCRxFF30_01F4_ReservedCgttSclk_21_0_WIDTH 21
-#define FCRxFF30_01F4_ReservedCgttSclk_21_0_MASK 0x3fffff
-#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22
-#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000
-#define FCRxFF30_01F4_ReservedCgttSclk_24_23_OFFSET 23
-#define FCRxFF30_01F4_ReservedCgttSclk_24_23_WIDTH 2
-#define FCRxFF30_01F4_ReservedCgttSclk_24_23_MASK 0x1800000
-#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25
-#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000
-#define FCRxFF30_01F4_ReservedCgttSclk_26_26_OFFSET 26
-#define FCRxFF30_01F4_ReservedCgttSclk_26_26_WIDTH 1
-#define FCRxFF30_01F4_ReservedCgttSclk_26_26_MASK 0x4000000
-#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27
-#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000
-#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28
-#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000
-#define FCRxFF30_01F4_ReservedCgttSclk_31_29_OFFSET 29
-#define FCRxFF30_01F4_ReservedCgttSclk_31_29_WIDTH 3
-#define FCRxFF30_01F4_ReservedCgttSclk_31_29_MASK 0xe0000000
+#define FCRxFE00_70D2_Reserved_6_0_OFFSET 0
+#define FCRxFE00_70D2_Reserved_6_0_WIDTH 7
+#define FCRxFE00_70D2_Reserved_6_0_MASK 0x7f
+#define FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET 7
+#define FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH 12
+#define FCRxFE00_70D2_SclkDpmTdpLimitPG_MASK 0x7ff80
+#define FCRxFE00_70D2_Reserved_31_19_OFFSET 19
+#define FCRxFE00_70D2_Reserved_31_19_WIDTH 13
+#define FCRxFE00_70D2_Reserved_31_19_MASK 0xfff80000
-/// FCRxFF30_01F4
+/// FCRxFE00_70D2
typedef union {
struct { ///<
- UINT32 ReservedCgttSclk_21_0:22; ///<
- UINT32 CgBifCgttSclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_24_23:2 ; ///<
- UINT32 CgDcCgttSclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_26_26:1 ; ///<
- UINT32 CgMcbCgttSclkOverride:1 ; ///<
- UINT32 CgMcdwCgttSclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_31_29:3 ; ///<
+ UINT32 Reserved_6_0:7 ; ///<
+ UINT32 SclkDpmTdpLimitPG:12; ///<
+ UINT32 Reserved_31_19:13; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_01F4_STRUCT;
+} FCRxFE00_70D2_STRUCT;
-// **** FCRxFF30_01F5 Register Definition ****
+// **** FCRxFE00_70D4 Register Definition ****
// Address
-#define FCRxFF30_01F5_ADDRESS 0xff3001f5
+#define FCRxFE00_70D4_ADDRESS 0xfe0070d4
// Type
-#define FCRxFF30_01F5_TYPE TYPE_FCR
+#define FCRxFE00_70D4_TYPE TYPE_FCR
// Field Data
-#define FCRxFF30_01F5_ReservedCgttSclk_10_0_OFFSET 0
-#define FCRxFF30_01F5_ReservedCgttSclk_10_0_WIDTH 11
-#define FCRxFF30_01F5_ReservedCgttSclk_10_0_MASK 0x7ff
-#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11
-#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800
-#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12
-#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000
-#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13
-#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000
-#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14
-#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000
-#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15
-#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000
-#define FCRxFF30_01F5_ReservedCgttSclk_27_16_OFFSET 16
-#define FCRxFF30_01F5_ReservedCgttSclk_27_16_WIDTH 12
-#define FCRxFF30_01F5_ReservedCgttSclk_27_16_MASK 0xfff0000
-#define FCRxFF30_01F5_CgDcCgttDispClkOverride_OFFSET 28
-#define FCRxFF30_01F5_CgDcCgttDispClkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgDcCgttDispClkOverride_MASK 0x10000000
-#define FCRxFF30_01F5_ReservedCgttSclk_31_29_OFFSET 29
-#define FCRxFF30_01F5_ReservedCgttSclk_31_29_WIDTH 3
-#define FCRxFF30_01F5_ReservedCgttSclk_31_29_MASK 0xe0000000
+#define FCRxFE00_70D4_Reserved_2_0_OFFSET 0
+#define FCRxFE00_70D4_Reserved_2_0_WIDTH 3
+#define FCRxFE00_70D4_Reserved_2_0_MASK 0x7
+#define FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET 3
+#define FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH 21
+#define FCRxFE00_70D4_SclkDpmBoostMargin_MASK 0xfffff8
+#define FCRxFE00_70D4_Reserved_31_24_OFFSET 24
+#define FCRxFE00_70D4_Reserved_31_24_WIDTH 8
+#define FCRxFE00_70D4_Reserved_31_24_MASK 0xff000000
-/// FCRxFF30_01F5
+/// FCRxFE00_70D4
typedef union {
struct { ///<
- UINT32 ReservedCgttSclk_10_0:11; ///<
- UINT32 CgVmcCgttSclkOverride:1 ; ///<
- UINT32 CgOrbCgttSclkOverride:1 ; ///<
- UINT32 CgOrbCgttLclkOverride:1 ; ///<
- UINT32 CgIocCgttSclkOverride:1 ; ///<
- UINT32 CgIocCgttLclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_27_16:12; ///<
- UINT32 CgDcCgttDispClkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_31_29:3 ; ///<
+ UINT32 Reserved_2_0:3 ; ///<
+ UINT32 SclkDpmBoostMargin:21; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_01F5_STRUCT;
+} FCRxFE00_70D4_STRUCT;
-// **** FCRxFF30_1512 Register Definition ****
+// **** FCRxFE00_70D7 Register Definition ****
// Address
-#define FCRxFF30_1512_ADDRESS 0xff301512
+#define FCRxFE00_70D7_ADDRESS 0xfe0070d7
// Type
-#define FCRxFF30_1512_TYPE TYPE_FCR
+#define FCRxFE00_70D7_TYPE TYPE_FCR
// Field Data
-#define FCRxFF30_1512_Reserved_30_0_OFFSET 0
-#define FCRxFF30_1512_Reserved_30_0_WIDTH 31
-#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff
-#define FCRxFF30_1512_SoftOverride0_OFFSET 31
-#define FCRxFF30_1512_SoftOverride0_WIDTH 1
-#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000
+#define FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET 0
+#define FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH 21
+#define FCRxFE00_70D7_SclkDpmThrottleMargin_MASK 0x1fffff
+#define FCRxFE00_70D7_Reserved_31_21_OFFSET 21
+#define FCRxFE00_70D7_Reserved_31_21_WIDTH 11
+#define FCRxFE00_70D7_Reserved_31_21_MASK 0xffe00000
-/// FCRxFF30_1512
+/// FCRxFE00_70D7
typedef union {
struct { ///<
- UINT32 Reserved_30_0:31; ///<
- UINT32 SoftOverride0:1 ; ///<
+ UINT32 SclkDpmThrottleMargin:21; ///<
+ UINT32 Reserved_31_21:11; ///<
} Field; ///<
UINT32 Value; ///<
-} FCRxFF30_1512_STRUCT;
+} FCRxFE00_70D7_STRUCT;
-// **** SMUx1B Register Definition ****
+// **** SMUx0B_x8410 Register Definition ****
// Address
-#define SMUx1B_ADDRESS 0x1b
+#define SMUx0B_x8410_ADDRESS 0x8410
// Type
-#define SMUx1B_TYPE TYPE_SMU
+#define SMUx0B_x8410_TYPE TYPE_SMUx0B
// Field Data
-#define SMUx1B_LclkDpSlpDiv_OFFSET 0
-#define SMUx1B_LclkDpSlpDiv_WIDTH 3
-#define SMUx1B_LclkDpSlpDiv_MASK 0x7
-#define SMUx1B_RampDis_OFFSET 3
-#define SMUx1B_RampDis_WIDTH 1
-#define SMUx1B_RampDis_MASK 0x8
-#define SMUx1B_Reserved_7_4_OFFSET 4
-#define SMUx1B_Reserved_7_4_WIDTH 4
-#define SMUx1B_Reserved_7_4_MASK 0xf0
-#define SMUx1B_LclkDpSlpMask_OFFSET 8
-#define SMUx1B_LclkDpSlpMask_WIDTH 8
-#define SMUx1B_LclkDpSlpMask_MASK 0xff00
+#define SMUx0B_x8410_PwrGatingEn_OFFSET 0
+#define SMUx0B_x8410_PwrGatingEn_WIDTH 1
+#define SMUx0B_x8410_PwrGatingEn_MASK 0x1
+#define SMUx0B_x8410_Reserved_2_1_OFFSET 1
+#define SMUx0B_x8410_Reserved_2_1_WIDTH 2
+#define SMUx0B_x8410_Reserved_2_1_MASK 0x6
+#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3
+#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5
+#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8
+#define SMUx0B_x8410_SavePsoDelay_OFFSET 8
+#define SMUx0B_x8410_SavePsoDelay_WIDTH 4
+#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00
+#define SMUx0B_x8410_NRestoreIsoDelay_OFFSET 12
+#define SMUx0B_x8410_NRestoreIsoDelay_WIDTH 4
+#define SMUx0B_x8410_NRestoreIsoDelay_MASK 0xf000
+#define SMUx0B_x8410_RstPulseWidth_OFFSET 16
+#define SMUx0B_x8410_RstPulseWidth_WIDTH 8
+#define SMUx0B_x8410_RstPulseWidth_MASK 0xff0000
+#define SMUx0B_x8410_IsoDelay_OFFSET 24
+#define SMUx0B_x8410_IsoDelay_WIDTH 4
+#define SMUx0B_x8410_IsoDelay_MASK 0xf000000
+#define SMUx0B_x8410_PwrGaterSel_OFFSET 28
+#define SMUx0B_x8410_PwrGaterSel_WIDTH 4
+#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000
-/// SMUx1B
+/// SMUx0B_x8410
typedef union {
struct { ///<
- UINT32 LclkDpSlpDiv:3 ; ///<
- UINT32 RampDis:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 LclkDpSlpMask:8 ; ///<
+ UINT32 PwrGatingEn:1 ; ///<
+ UINT32 Reserved_2_1:2 ; ///<
+ UINT32 PsoControlValidNum:5 ; ///<
+ UINT32 SavePsoDelay:4 ; ///<
+ UINT32 NRestoreIsoDelay:4 ; ///<
+ UINT32 RstPulseWidth:8 ; ///<
+ UINT32 IsoDelay:4 ; ///<
+ UINT32 PwrGaterSel:4 ; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx1B_STRUCT;
+} SMUx0B_x8410_STRUCT;
-// **** SMUx1D Register Definition ****
+// **** SMUx0B_x8504 Register Definition ****
// Address
-#define SMUx1D_ADDRESS 0x1d
+#define SMUx0B_x8504_ADDRESS 0x8504
// Type
-#define SMUx1D_TYPE TYPE_SMU
+#define SMUx0B_x8504_TYPE TYPE_SMUx0B
// Field Data
-#define SMUx1D_LclkDpSlpHyst_OFFSET 0
-#define SMUx1D_LclkDpSlpHyst_WIDTH 12
-#define SMUx1D_LclkDpSlpHyst_MASK 0xfff
-#define SMUx1D_LclkDpSlpEn_OFFSET 12
-#define SMUx1D_LclkDpSlpEn_WIDTH 1
-#define SMUx1D_LclkDpSlpEn_MASK 0x1000
-#define SMUx1D_Reserved_15_13_OFFSET 13
-#define SMUx1D_Reserved_15_13_WIDTH 3
-#define SMUx1D_Reserved_15_13_MASK 0xe000
+#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0
+#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8
+#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff
+#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8
+#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8
+#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00
+#define SMUx0B_x8504_Reserved_31_16_OFFSET 16
+#define SMUx0B_x8504_Reserved_31_16_WIDTH 16
+#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000
-/// SMUx1D
+/// SMUx0B_x8504
typedef union {
struct { ///<
- UINT32 LclkDpSlpHyst:12; ///<
- UINT32 LclkDpSlpEn:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
+ UINT32 SaveRestoreWidth:8 ; ///<
+ UINT32 PsoRestoreTimer:8 ; ///<
+ UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx1D_STRUCT;
-
-// **** SMUx6F Register Definition ****
-// Address
-#define SMUx6F_ADDRESS 0x6f
-
+} SMUx0B_x8504_STRUCT;
-// **** SMUx71 Register Definition ****
+// **** SMUx0B_x8408 Register Definition ****
// Address
-#define SMUx71_ADDRESS 0x71
+#define SMUx0B_x8408_ADDRESS 0x8408
+// Type
+#define SMUx0B_x8408_TYPE TYPE_SMUx0B
+// Field Data
+#define SMUx0B_x8408_PsoControlId0_OFFSET 0
+#define SMUx0B_x8408_PsoControlId0_WIDTH 4
+#define SMUx0B_x8408_PsoControlId0_MASK 0xf
+#define SMUx0B_x8408_PsoControlId1_OFFSET 4
+#define SMUx0B_x8408_PsoControlId1_WIDTH 4
+#define SMUx0B_x8408_PsoControlId1_MASK 0xf0
+#define SMUx0B_x8408_PsoControlId2_OFFSET 8
+#define SMUx0B_x8408_PsoControlId2_WIDTH 4
+#define SMUx0B_x8408_PsoControlId2_MASK 0xf00
+#define SMUx0B_x8408_PsoControlId3_OFFSET 12
+#define SMUx0B_x8408_PsoControlId3_WIDTH 4
+#define SMUx0B_x8408_PsoControlId3_MASK 0xf000
+#define SMUx0B_x8408_PsoControlId4_OFFSET 16
+#define SMUx0B_x8408_PsoControlId4_WIDTH 4
+#define SMUx0B_x8408_PsoControlId4_MASK 0xf0000
+#define SMUx0B_x8408_PsoControlId5_OFFSET 20
+#define SMUx0B_x8408_PsoControlId5_WIDTH 4
+#define SMUx0B_x8408_PsoControlId5_MASK 0xf00000
+#define SMUx0B_x8408_PsoControlId6_OFFSET 24
+#define SMUx0B_x8408_PsoControlId6_WIDTH 4
+#define SMUx0B_x8408_PsoControlId6_MASK 0xf000000
+#define SMUx0B_x8408_PsoControlId7_OFFSET 28
+#define SMUx0B_x8408_PsoControlId7_WIDTH 4
+#define SMUx0B_x8408_PsoControlId7_MASK 0xf0000000
+
+/// SMUx0B_x8408
+typedef union {
+ struct { ///<
+ UINT32 PsoControlId0:4 ; ///<
+ UINT32 PsoControlId1:4 ; ///<
+ UINT32 PsoControlId2:4 ; ///<
+ UINT32 PsoControlId3:4 ; ///<
+ UINT32 PsoControlId4:4 ; ///<
+ UINT32 PsoControlId5:4 ; ///<
+ UINT32 PsoControlId6:4 ; ///<
+ UINT32 PsoControlId7:4 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} SMUx0B_x8408_STRUCT;
-// **** SMUx73 Register Definition ****
+// **** FCRxFF30_0398 Register Definition ****
// Address
-#define SMUx73_ADDRESS 0x73
+#define FCRxFF30_0398_ADDRESS 0xff300398
// Type
-#define SMUx73_TYPE TYPE_SMU
+#define FCRxFF30_0398_TYPE TYPE_FCR
// Field Data
-#define SMUx73_DisLclkGating_OFFSET 0
-#define SMUx73_DisLclkGating_WIDTH 1
-#define SMUx73_DisLclkGating_MASK 0x1
-#define SMUx73_DisSclkGating_OFFSET 1
-#define SMUx73_DisSclkGating_WIDTH 1
-#define SMUx73_DisSclkGating_MASK 0x2
-#define SMUx73_Reserved_15_2_OFFSET 2
-#define SMUx73_Reserved_15_2_WIDTH 14
-#define SMUx73_Reserved_15_2_MASK 0xfffc
+#define FCRxFF30_0398_Reserved_0_0_OFFSET 0
+#define FCRxFF30_0398_Reserved_0_0_WIDTH 1
+#define FCRxFF30_0398_Reserved_0_0_MASK 0x1
+#define FCRxFF30_0398_SoftResetCg_OFFSET 2
+#define FCRxFF30_0398_SoftResetCg_WIDTH 1
+#define FCRxFF30_0398_SoftResetCg_MASK 0x4
+#define FCRxFF30_0398_Reserved_4_3_OFFSET 3
+#define FCRxFF30_0398_Reserved_4_3_WIDTH 2
+#define FCRxFF30_0398_Reserved_4_3_MASK 0x18
+#define FCRxFF30_0398_SoftResetDc_OFFSET 5
+#define FCRxFF30_0398_SoftResetDc_WIDTH 1
+#define FCRxFF30_0398_SoftResetDc_MASK 0x20
+#define FCRxFF30_0398_Reserved_6_6_OFFSET 6
+#define FCRxFF30_0398_Reserved_6_6_WIDTH 1
+#define FCRxFF30_0398_Reserved_6_6_MASK 0x40
+#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8
+#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1
+#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100
+#define FCRxFF30_0398_SoftResetMc_OFFSET 11
+#define FCRxFF30_0398_SoftResetMc_WIDTH 1
+#define FCRxFF30_0398_SoftResetMc_MASK 0x800
+#define FCRxFF30_0398_Reserved_12_12_OFFSET 12
+#define FCRxFF30_0398_Reserved_12_12_WIDTH 1
+#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000
+#define FCRxFF30_0398_SoftResetRlc_OFFSET 13
+#define FCRxFF30_0398_SoftResetRlc_WIDTH 1
+#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000
+#define FCRxFF30_0398_Reserved_16_16_OFFSET 16
+#define FCRxFF30_0398_Reserved_16_16_WIDTH 1
+#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000
+#define FCRxFF30_0398_SoftResetUvd_OFFSET 18
+#define FCRxFF30_0398_SoftResetUvd_WIDTH 1
+#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000
+#define FCRxFF30_0398_Reserved_19_19_OFFSET 19
+#define FCRxFF30_0398_Reserved_19_19_WIDTH 1
+#define FCRxFF30_0398_Reserved_19_19_MASK 0x80000
-/// SMUx73
+#define FCRxFF30_0398_Reserved_31_24_OFFSET 24
+#define FCRxFF30_0398_Reserved_31_24_WIDTH 8
+#define FCRxFF30_0398_Reserved_31_24_MASK 0xff000000
+
+/// FCRxFF30_0398
typedef union {
struct { ///<
- UINT32 DisLclkGating:1 ; ///<
- UINT32 DisSclkGating:1 ; ///<
- UINT32 Reserved_15_2:14; ///<
+ UINT32 Reserved_0_0:1 ; ///<
+ UINT32 Reserved_1_1:1 ; ///<
+ UINT32 SoftResetCg:1 ; ///<
+ UINT32 Reserved_4_3:2 ; ///<
+ UINT32 SoftResetDc:1 ; ///<
+ UINT32 Reserved_6_6:1 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 SoftResetGrbm:1 ; ///<
+ UINT32 Reserved_9_9:1 ; ///<
+ UINT32 Reserved_10_10:1 ; ///<
+ UINT32 SoftResetMc:1 ; ///<
+ UINT32 Reserved_12_12:1 ; ///<
+ UINT32 SoftResetRlc:1 ; ///<
+ UINT32 Reserved_14_14:1 ; ///<
+ UINT32 Reserved_15_15:1 ; ///<
+ UINT32 Reserved_16_16:1 ; ///<
+ UINT32 Reserved_17_17:1 ; ///<
+ UINT32 SoftResetUvd:1 ; ///<
+ UINT32 Reserved_19_19:1 ; ///<
+ UINT32 Reserved_20_20:1 ; ///<
+ UINT32 Reserved_21_21:1 ; ///<
+ UINT32 Reserved_22_22:1 ; ///<
+ UINT32 Reserved_23_23:1 ; ///<
+ UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
-} SMUx73_STRUCT;
+} FCRxFF30_0398_STRUCT;
-// **** D0F0x98_x49 Register Definition ****
+// **** FCRxFF30_1512 Register Definition ****
// Address
-#define D0F0x98_x49_ADDRESS 0x49
+#define FCRxFF30_1512_ADDRESS 0xff301512
// Type
-#define D0F0x98_x49_TYPE TYPE_D0F0x98
+#define FCRxFF30_1512_TYPE TYPE_FCR
// Field Data
-#define D0F0x98_x49_Reserved_23_0_OFFSET 0
-#define D0F0x98_x49_Reserved_23_0_WIDTH 24
-#define D0F0x98_x49_Reserved_23_0_MASK 0xffffff
-#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24
-#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000
-#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25
-#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000
-#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26
-#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000
-#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27
-#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28
-#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29
-#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30
-#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x98_x49_Reserved_31_31_OFFSET 31
-#define D0F0x98_x49_Reserved_31_31_WIDTH 1
-#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000
+#define FCRxFF30_1512_Reserved_30_0_OFFSET 0
+#define FCRxFF30_1512_Reserved_30_0_WIDTH 31
+#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff
+#define FCRxFF30_1512_SoftOverride0_OFFSET 31
+#define FCRxFF30_1512_SoftOverride0_WIDTH 1
+#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000
-/// D0F0x98_x49
+/// FCRxFF30_1512
typedef union {
struct { ///<
- UINT32 Reserved_23_0:24; ///<
- UINT32 SoftOverrideClk6:1 ; ///<
- UINT32 SoftOverrideClk5:1 ; ///<
- UINT32 SoftOverrideClk4:1 ; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 Reserved_30_0:31; ///<
+ UINT32 SoftOverride0:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x98_x49_STRUCT;
+} FCRxFF30_1512_STRUCT;
-// **** D0F0x98_x4A Register Definition ****
+// **** SMUx0B_x84A0 Register Definition ****
// Address
-#define D0F0x98_x4A_ADDRESS 0x4a
+#define SMUx0B_x84A0_ADDRESS 0x84a0
// Type
-#define D0F0x98_x4A_TYPE TYPE_D0F0x98
+#define SMUx0B_x84A0_TYPE TYPE_SMUx0B
// Field Data
-#define D0F0x98_x4A_Reserved_23_0_OFFSET 0
-#define D0F0x98_x4A_Reserved_23_0_WIDTH 24
-#define D0F0x98_x4A_Reserved_23_0_MASK 0xffffff
-#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24
-#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000
-#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25
-#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000
-#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26
-#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000
-#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27
-#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28
-#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29
-#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30
-#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x98_x4A_Reserved_31_31_OFFSET 31
-#define D0F0x98_x4A_Reserved_31_31_WIDTH 1
-#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000
+#define SMUx0B_x84A0_MothPsoPwrup_OFFSET 0
+#define SMUx0B_x84A0_MothPsoPwrup_WIDTH 16
+#define SMUx0B_x84A0_MothPsoPwrup_MASK 0xffff
+#define SMUx0B_x84A0_MothPsoPwrdn_OFFSET 16
+#define SMUx0B_x84A0_MothPsoPwrdn_WIDTH 16
+#define SMUx0B_x84A0_MothPsoPwrdn_MASK 0xffff0000
-/// D0F0x98_x4A
+/// SMUx0B_x84A0
typedef union {
struct { ///<
- UINT32 Reserved_23_0:24; ///<
- UINT32 SoftOverrideClk6:1 ; ///<
- UINT32 SoftOverrideClk5:1 ; ///<
- UINT32 SoftOverrideClk4:1 ; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 MothPsoPwrup:16; ///<
+ UINT32 MothPsoPwrdn:16; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x98_x4A_STRUCT;
-
-// **** D0F0x98_x4B Register Definition ****
+} SMUx0B_x84A0_STRUCT;
+// **** GMMxCAC Register Definition ****
// Address
-#define D0F0x98_x4B_ADDRESS 0x4b
+#define GMMxCAC_ADDRESS 0xcac
// Type
-#define D0F0x98_x4B_TYPE TYPE_D0F0x98
+#define GMMxCAC_TYPE TYPE_GMM
// Field Data
-#define D0F0x98_x4B_Reserved_29_0_OFFSET 0
-#define D0F0x98_x4B_Reserved_29_0_WIDTH 30
-#define D0F0x98_x4B_Reserved_29_0_MASK 0x3fffffff
-#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30
-#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1
-#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000
-#define D0F0x98_x4B_Reserved_31_31_OFFSET 31
-#define D0F0x98_x4B_Reserved_31_31_WIDTH 1
-#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000
+#define GMMxCAC_NbPstateChangeEnable_OFFSET 0
+#define GMMxCAC_NbPstateChangeEnable_WIDTH 1
+#define GMMxCAC_NbPstateChangeEnable_MASK 0x1
+#define GMMxCAC_Reserved_3_1_OFFSET 1
+#define GMMxCAC_Reserved_3_1_WIDTH 3
+#define GMMxCAC_Reserved_3_1_MASK 0xe
+#define GMMxCAC_NbPstateChangeUrgentDuringRequest_OFFSET 4
+#define GMMxCAC_NbPstateChangeUrgentDuringRequest_WIDTH 1
+#define GMMxCAC_NbPstateChangeUrgentDuringRequest_MASK 0x10
+#define GMMxCAC_Reserved_7_5_OFFSET 5
+#define GMMxCAC_Reserved_7_5_WIDTH 3
+#define GMMxCAC_Reserved_7_5_MASK 0xe0
+#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8
+#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1
+#define GMMxCAC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100
+#define GMMxCAC_NbPstateChangeForceOn_OFFSET 9
+#define GMMxCAC_NbPstateChangeForceOn_WIDTH 1
+#define GMMxCAC_NbPstateChangeForceOn_MASK 0x200
+#define GMMxCAC_Reserved_11_10_OFFSET 10
+#define GMMxCAC_Reserved_11_10_WIDTH 2
+#define GMMxCAC_Reserved_11_10_MASK 0xc00
+#define GMMxCAC_NbPstateChangeWatermarkMask_OFFSET 12
+#define GMMxCAC_NbPstateChangeWatermarkMask_WIDTH 2
+#define GMMxCAC_NbPstateChangeWatermarkMask_MASK 0x3000
+#define GMMxCAC_Reserved_15_14_OFFSET 14
+#define GMMxCAC_Reserved_15_14_WIDTH 2
+#define GMMxCAC_Reserved_15_14_MASK 0xc000
+#define GMMxCAC_NbPstateChangeWatermark_OFFSET 16
+#define GMMxCAC_NbPstateChangeWatermark_WIDTH 16
+#define GMMxCAC_NbPstateChangeWatermark_MASK 0xffff0000
-/// D0F0x98_x4B
+/// GMMxCAC
typedef union {
struct { ///<
- UINT32 Reserved_29_0:30; ///<
- UINT32 SoftOverrideClk:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 NbPstateChangeEnable:1 ; ///<
+ UINT32 Reserved_3_1:3 ; ///<
+ UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///<
+ UINT32 Reserved_7_5:3 ; ///<
+ UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///<
+ UINT32 NbPstateChangeForceOn:1 ; ///<
+ UINT32 Reserved_11_10:2 ; ///<
+ UINT32 NbPstateChangeWatermarkMask:2 ; ///<
+ UINT32 Reserved_15_14:2 ; ///<
+ UINT32 NbPstateChangeWatermark:16; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} GMMxCAC_STRUCT;
+
+// **** GMMxCCC Register Definition ****
+// Address
+#define GMMxCCC_ADDRESS 0xccc
+
+// Type
+#define GMMxCCC_TYPE TYPE_GMM
+// Field Data
+#define GMMxCCC_NbPstateChangeEnable_OFFSET 0
+#define GMMxCCC_NbPstateChangeEnable_WIDTH 1
+#define GMMxCCC_NbPstateChangeEnable_MASK 0x1
+#define GMMxCCC_Reserved_3_1_OFFSET 1
+#define GMMxCCC_Reserved_3_1_WIDTH 3
+#define GMMxCCC_Reserved_3_1_MASK 0xe
+#define GMMxCCC_NbPstateChangeUrgentDuringRequest_OFFSET 4
+#define GMMxCCC_NbPstateChangeUrgentDuringRequest_WIDTH 1
+#define GMMxCCC_NbPstateChangeUrgentDuringRequest_MASK 0x10
+#define GMMxCCC_Reserved_7_5_OFFSET 5
+#define GMMxCCC_Reserved_7_5_WIDTH 3
+#define GMMxCCC_Reserved_7_5_MASK 0xe0
+#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_OFFSET 8
+#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_WIDTH 1
+#define GMMxCCC_NbPstateChangeNotSelfRefreshDuringRequest_MASK 0x100
+#define GMMxCCC_NbPstateChangeForceOn_OFFSET 9
+#define GMMxCCC_NbPstateChangeForceOn_WIDTH 1
+#define GMMxCCC_NbPstateChangeForceOn_MASK 0x200
+#define GMMxCCC_Reserved_11_10_OFFSET 10
+#define GMMxCCC_Reserved_11_10_WIDTH 2
+#define GMMxCCC_Reserved_11_10_MASK 0xc00
+#define GMMxCCC_NbPstateChangeWatermarkMask_OFFSET 12
+#define GMMxCCC_NbPstateChangeWatermarkMask_WIDTH 2
+#define GMMxCCC_NbPstateChangeWatermarkMask_MASK 0x3000
+#define GMMxCCC_Reserved_15_14_OFFSET 14
+#define GMMxCCC_Reserved_15_14_WIDTH 2
+#define GMMxCCC_Reserved_15_14_MASK 0xc000
+#define GMMxCCC_NbPstateChangeWatermark_OFFSET 16
+#define GMMxCCC_NbPstateChangeWatermark_WIDTH 16
+#define GMMxCCC_NbPstateChangeWatermark_MASK 0xffff0000
+
+/// GMMxCCC
+typedef union {
+ struct { ///<
+ UINT32 NbPstateChangeEnable:1 ; ///<
+ UINT32 Reserved_3_1:3 ; ///<
+ UINT32 NbPstateChangeUrgentDuringRequest:1 ; ///<
+ UINT32 Reserved_7_5:3 ; ///<
+ UINT32 NbPstateChangeNotSelfRefreshDuringRequest:1 ; ///<
+ UINT32 NbPstateChangeForceOn:1 ; ///<
+ UINT32 Reserved_11_10:2 ; ///<
+ UINT32 NbPstateChangeWatermarkMask:2 ; ///<
+ UINT32 Reserved_15_14:2 ; ///<
+ UINT32 NbPstateChangeWatermark:16; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x98_x4B_STRUCT;
+} GMMxCCC_STRUCT;
-// **** D0F0x64_x22 Register Definition ****
+// **** GMMx6B30 Register Definition ****
// Address
-#define D0F0x64_x22_ADDRESS 0x22
+#define GMMx6B30_ADDRESS 0x6b30
// Type
-#define D0F0x64_x22_TYPE TYPE_D0F0x64
+#define GMMx6B30_TYPE TYPE_GMM
// Field Data
-#define D0F0x64_x22_Reserved_25_0_OFFSET 0
-#define D0F0x64_x22_Reserved_25_0_WIDTH 26
-#define D0F0x64_x22_Reserved_25_0_MASK 0x3ffffff
-#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26
-#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000
-#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27
-#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28
-#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29
-#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30
-#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x64_x22_Reserved_31_31_OFFSET 31
-#define D0F0x64_x22_Reserved_31_31_WIDTH 1
-#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000
+#define GMMx6B30_DcAllowNbPstatesForceOne_OFFSET 25
+#define GMMx6B30_DcAllowNbPstatesForceOne_WIDTH 1
+#define GMMx6B30_DcAllowNbPstatesForceOne_MASK 0x2000000
-/// D0F0x64_x22
+/// GMMx6B30
typedef union {
struct { ///<
- UINT32 Reserved_25_0:26; ///<
- UINT32 SoftOverrideClk4:1 ; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 Reserved_0_24:25 ; ///<
+ UINT32 DcAllowNbPstatesForceOne:1 ; ///<
+ UINT32 Reserved_31_26:6 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x64_x22_STRUCT;
+} GMMx6B30_STRUCT;
-// **** D0F0x64_x23 Register Definition ****
+// **** GMMx7730 Register Definition ****
// Address
-#define D0F0x64_x23_ADDRESS 0x23
+#define GMMx7730_ADDRESS 0x7730
// Type
-#define D0F0x64_x23_TYPE TYPE_D0F0x64
+#define GMMx7730_TYPE TYPE_GMM
// Field Data
-#define D0F0x64_x23_Reserved_26_0_OFFSET 0
-#define D0F0x64_x23_Reserved_26_0_WIDTH 27
-#define D0F0x64_x23_Reserved_26_0_MASK 0x7ffffff
-#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27
-#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28
-#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29
-#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30
-#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x64_x23_Reserved_31_31_OFFSET 31
-#define D0F0x64_x23_Reserved_31_31_WIDTH 1
-#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000
-/// D0F0x64_x23
+#define GMMx7730_DcAllowNbPstatesForceOne_OFFSET 25
+#define GMMx7730_DcAllowNbPstatesForceOne_WIDTH 1
+#define GMMx7730_DcAllowNbPstatesForceOne_MASK 0x2000000
+
+/// GMMx7730
typedef union {
struct { ///<
- UINT32 Reserved_26_0:27; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 Reserved_0_24:25 ; ///<
+ UINT32 DcAllowNbPstatesForceOne:1 ; ///<
+ UINT32 Reserved_31_26:6 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x64_x23_STRUCT;
+} GMMx7730_STRUCT;
+// **** GMMx2854 Register Definition ****
+// Address
+#define GMMx2854_ADDRESS 0x2854
-// **** D0F0x64_x24 Register Definition ****
+// Type
+#define GMMx2854_TYPE TYPE_GMM
+// **** D0F0x98_x0C Register Definition ****
// Address
-#define D0F0x64_x24_ADDRESS 0x24
+#define D0F0x98_x0C_ADDRESS 0xc
// Type
-#define D0F0x64_x24_TYPE TYPE_D0F0x64
+#define D0F0x98_x0C_TYPE TYPE_D0F0x98
+#define D0F0x98_x0C_IntrHiPriClr_OFFSET 31
+#define D0F0x98_x0C_IntrHiPriClr_WIDTH 1
+#define D0F0x98_x0C_IntrHiPriClr_MASK 0x80000000
+// **** D0F0x98_x0D Register Definition ****
+// Address
+#define D0F0x98_x0D_ADDRESS 0xd
+
+// Type
+#define D0F0x98_x0D_TYPE TYPE_D0F0x98
+// **** D18F3xA0 Register Definition ****
+// Address
+#define D18F3xA0_ADDRESS 0xa0
+
+// Type
+#define D18F3xA0_TYPE TYPE_D18F3
// Field Data
-#define D0F0x64_x24_Reserved_28_0_OFFSET 0
-#define D0F0x64_x24_Reserved_28_0_WIDTH 29
-#define D0F0x64_x24_Reserved_28_0_MASK 0x1fffffff
-#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29
-#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1
-#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30
-#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1
-#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x64_x24_Reserved_31_31_OFFSET 31
-#define D0F0x64_x24_Reserved_31_31_WIDTH 1
-#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000
+#define D18F3xA0_PsiVid_OFFSET 0
+#define D18F3xA0_PsiVid_WIDTH 7
+#define D18F3xA0_PsiVid_MASK 0x7f
+#define D18F3xA0_PsiVidEn_OFFSET 7
+#define D18F3xA0_PsiVidEn_WIDTH 1
+#define D18F3xA0_PsiVidEn_MASK 0x80
+#define D18F3xA0_Reserved_8_8_OFFSET 8
+#define D18F3xA0_Reserved_8_8_WIDTH 1
+#define D18F3xA0_Reserved_8_8_MASK 0x100
+#define D18F3xA0_SviHighFreqSel_OFFSET 9
+#define D18F3xA0_SviHighFreqSel_WIDTH 1
+#define D18F3xA0_SviHighFreqSel_MASK 0x200
+#define D18F3xA0_Reserved_15_10_OFFSET 10
+#define D18F3xA0_Reserved_15_10_WIDTH 6
+#define D18F3xA0_Reserved_15_10_MASK 0xfc00
+#define D18F3xA0_ConfigId_OFFSET 16
+#define D18F3xA0_ConfigId_WIDTH 12
+#define D18F3xA0_ConfigId_MASK 0xfff0000
+#define D18F3xA0_Reserved_30_28_OFFSET 28
+#define D18F3xA0_Reserved_30_28_WIDTH 3
+#define D18F3xA0_Reserved_30_28_MASK 0x70000000
+#define D18F3xA0_CofVidProg_OFFSET 31
+#define D18F3xA0_CofVidProg_WIDTH 1
+#define D18F3xA0_CofVidProg_MASK 0x80000000
-/// D0F0x64_x24
+/// D18F3xA0
typedef union {
struct { ///<
- UINT32 Reserved_28_0:29; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
+ UINT32 PsiVid:7 ; ///<
+ UINT32 PsiVidEn:1 ; ///<
+ UINT32 Reserved_8_8:1 ; ///<
+ UINT32 SviHighFreqSel:1 ; ///<
+ UINT32 Reserved_15_10:6 ; ///<
+ UINT32 ConfigId:12; ///<
+ UINT32 Reserved_30_28:3 ; ///<
+ UINT32 CofVidProg:1 ; ///<
} Field; ///<
UINT32 Value; ///<
-} D0F0x64_x24_STRUCT;
+} D18F3xA0_STRUCT;
+// **** D18F6x110 Register Definition ****
+// Address
+#define D18F6x110_ADDRESS 0x110
+
+// Type
+#define D18F6x110_TYPE TYPE_D18F6
+// Field Data
+#define D18F6x110_NclkFifoOff_OFFSET 0
+#define D18F6x110_NclkFifoOff_WIDTH 3
+#define D18F6x110_NclkFifoOff_MASK 0x7
+#define D18F6x110_Reserved_3_3_OFFSET 3
+#define D18F6x110_Reserved_3_3_WIDTH 1
+#define D18F6x110_Reserved_3_3_MASK 0x8
+#define D18F6x110_LclkFifoOff_OFFSET 4
+#define D18F6x110_LclkFifoOff_WIDTH 3
+#define D18F6x110_LclkFifoOff_MASK 0x70
+#define D18F6x110_Reserved_7_7_OFFSET 7
+#define D18F6x110_Reserved_7_7_WIDTH 1
+#define D18F6x110_Reserved_7_7_MASK 0x80
+#define D18F6x110_PllMult_OFFSET 8
+#define D18F6x110_PllMult_WIDTH 6
+#define D18F6x110_PllMult_MASK 0x3f00
+#define D18F6x110_Reserved_14_14_OFFSET 14
+#define D18F6x110_Reserved_14_14_WIDTH 1
+#define D18F6x110_Reserved_14_14_MASK 0x4000
+#define D18F6x110_Enable_OFFSET 15
+#define D18F6x110_Enable_WIDTH 1
+#define D18F6x110_Enable_MASK 0x8000
+#define D18F6x110_LclkFreq_OFFSET 16
+#define D18F6x110_LclkFreq_WIDTH 7
+#define D18F6x110_LclkFreq_MASK 0x7f0000
+#define D18F6x110_LclkFreqType_OFFSET 23
+#define D18F6x110_LclkFreqType_WIDTH 1
+#define D18F6x110_LclkFreqType_MASK 0x800000
+#define D18F6x110_NclkFreq_OFFSET 24
+#define D18F6x110_NclkFreq_WIDTH 7
+#define D18F6x110_NclkFreq_MASK 0x7f000000
+#define D18F6x110_NclkFreqType_OFFSET 31
+#define D18F6x110_NclkFreqType_WIDTH 1
+#define D18F6x110_NclkFreqType_MASK 0x80000000
+/// D18F6x110
+typedef union {
+ struct { ///<
+ UINT32 NclkFifoOff:3 ; ///<
+ UINT32 Reserved_3_3:1 ; ///<
+ UINT32 LclkFifoOff:3 ; ///<
+ UINT32 Reserved_7_7:1 ; ///<
+ UINT32 PllMult:6 ; ///<
+ UINT32 Reserved_14_14:1 ; ///<
+ UINT32 Enable:1 ; ///<
+ UINT32 LclkFreq:7 ; ///<
+ UINT32 LclkFreqType:1 ; ///<
+ UINT32 NclkFreq:7 ; ///<
+ UINT32 NclkFreqType:1 ; ///<
+ } Field; ///<
+ UINT32 Value; ///<
+} D18F6x110_STRUCT;
#endif
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 48507 $ @e \$Date: 2011-03-09 13:25:11 -0700 (Wed, 09 Mar 2011) $
*
*/
/*
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
+#include "heapManager.h"
#include "GeneralServices.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "GfxIntegratedInfoTableInit.h"
#include "GfxRegisterAcc.h"
#include "GfxLib.h"
+#include "GnbFuseTable.h"
#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
-#include "GnbRegistersON.h"
+#include "GnbCommonLib.h"
+#include "GnbCommonLib.h"
+#include "GnbGfxFamServices.h"
+#include "GfxFamilyServices.h"
#include "F14NbPowerGate.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
UINT8 PrimaryDisplayPathId;
UINT8 SecondaryDisplayPathId;
UINTN DisplayPathIndex;
+ UINT32 D18F3x1FC;
+
PrimaryDisplayPathId = 0xff;
SecondaryDisplayPathId = 0xff;
for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) {
// Display config invalid for ON
PrimaryDisplayPathId = 0xff;
}
+
+ GnbLibPciRead (
+ MAKE_SBDFO ( 0, 0, 0x18, 3, 0x1FC),
+ AccessWidth32,
+ &D18F3x1FC,
+ GnbLibGetHeader (Gfx)
+ );
+
+ if ((D18F3x1FC & BIT4) == BIT4) {
+ if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeAutoDetect ||
+ (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds)) {
+ PrimaryDisplayPathId = 0xff;
+ }
+ }
+
if (PrimaryDisplayPathId != 0xff) {
ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3);
IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
IN GFX_PLATFORM_CONFIG *Gfx
)
{
+ PP_FUSE_ARRAY *PpFuseArray;
+ D18F4x15C_STRUCT D18F4x15C;
+
+ PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
+ ASSERT (PpFuseArray != NULL);
+ if (PpFuseArray != NULL) {
+ if (PpFuseArray->GpuBoostCap == 1) {
+ GnbLibPciRead (
+ MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS),
+ AccessWidth32,
+ &D18F4x15C.Value,
+ GnbLibGetHeader (Gfx)
+ );
+
+ D18F4x15C.Field.BoostSrc = 1;
+
+ GnbLibPciWrite (
+ MAKE_SBDFO ( 0, 0, 0x18, 4, D18F4x15C_ADDRESS),
+ AccessS3SaveWidth32,
+ &D18F4x15C.Value,
+ GnbLibGetHeader (Gfx)
+ );
+ }
+ }
+
IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380;
IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 30000;
IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx));
}
}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize Allow_Nb_Pstate High
+ *
+ *
+ *
+ * @param[in] Gfx Graphics configuration
+ */
+
+VOID
+GfxFmGmcAllowPstateHigh (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ )
+{
+ GMMxCAC_STRUCT GMMxCAC;
+ GMMxCCC_STRUCT GMMxCCC;
+ GMMx6B30_STRUCT GMMx6B30;
+ GMMx7730_STRUCT GMMx7730;
+ CPU_LOGICAL_ID LogicalId;
+
+ GetLogicalIdOfCurrentCore (&LogicalId, GnbLibGetHeader (Gfx));
+ //
+ //A workaround for F14 A0. This has be fixed in the future vesions.
+ //
+ if ((LogicalId.Revision & AMD_F14_ON_A0) != 0) {
+
+ //For PCIE Enhanced Mode
+ GMMx6B30.Value = GmmRegisterRead (GMMx6B30_ADDRESS, Gfx);
+ GMMx7730.Value = GmmRegisterRead (GMMx7730_ADDRESS, Gfx);
+ GMMx6B30.Field.DcAllowNbPstatesForceOne = 1;
+ GMMx7730.Field.DcAllowNbPstatesForceOne = 1;
+ GmmRegisterWrite (GMMx6B30_ADDRESS, GMMx6B30.Value, TRUE, Gfx);
+ GmmRegisterWrite (GMMx7730_ADDRESS, GMMx7730.Value, TRUE, Gfx);
+ //For Legacy mode
+ GMMxCAC.Value = GmmRegisterRead (GMMxCAC_ADDRESS, Gfx);
+ GMMxCCC.Value = GmmRegisterRead (GMMxCCC_ADDRESS, Gfx);
+ GMMxCAC.Field.NbPstateChangeForceOn = 1;
+ GMMxCCC.Field.NbPstateChangeForceOn = 1;
+ GmmRegisterWrite (GMMxCAC_ADDRESS, GMMxCAC.Value, TRUE, Gfx);
+ GmmRegisterWrite (GMMxCCC_ADDRESS, GMMxCCC.Value, TRUE, Gfx);
+ }
+}
+
/*----------------------------------------------------------------------------------------*/
/**
* Calculate COF for DFS out of Main PLL
* @retval COF in 10khz
*/
-AGESA_STATUS
+UINT32
GfxFmCalculateClock (
IN UINT8 Did,
IN AMD_CONFIG_PARAMS *StdHeader
MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100;
return GfxLibCalculateClk (Did, MainPllFreq10kHz);
}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set idle voltage mode for GFX
+ *
+ *
+ * @param[in] Gfx Pointer to global GFX configuration
+ */
+
+VOID
+GfxFmSetIdleVoltageMode (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ )
+{
+
+}
+
/*----------------------------------------------------------------------------------------
* GMC Disable Clock Gating
*----------------------------------------------------------------------------------------
*/
GMM_REG_ENTRY GmcDisableClockGating[] = {
- { 0x20C0, 0x00000C80 },
- { 0x20B8, 0x00000400 },
- { 0x20BC, 0x00000400 },
- { 0x2640, 0x00000400 },
- { 0x263C, 0x00000400 },
- { 0x2638, 0x00000400 },
- { 0x15C0, 0x00081401 }
+ { GMMx20C0_ADDRESS, 0x00000C80 },
+ { GMMx20B8_ADDRESS, 0x00000400 },
+ { GMMx20BC_ADDRESS, 0x00000400 },
+ { GMMx2640_ADDRESS, 0x00000400 },
+ { GMMx263C_ADDRESS, 0x00000400 },
+ { GMMx2638_ADDRESS, 0x00000400 },
+ { GMMx15C0_ADDRESS, 0x00081401 }
};
TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = {
*----------------------------------------------------------------------------------------
*/
GMM_REG_ENTRY GmcEnableClockGating[] = {
- { 0x20C0, 0x00040C80 },
- { 0x20B8, 0x00040400 },
- { 0x20BC, 0x00040400 },
- { 0x2640, 0x00040400 },
- { 0x263C, 0x00040400 },
- { 0x2638, 0x00040400 },
- { 0x15C0, 0x000C1401 }
+ { GMMx20C0_ADDRESS, 0x00040C80 },
+ { GMMx20B8_ADDRESS, 0x00040400 },
+ { GMMx20BC_ADDRESS, 0x00040400 },
+ { GMMx2640_ADDRESS, 0x00040400 },
+ { GMMx263C_ADDRESS, 0x00040400 },
+ { GMMx2638_ADDRESS, 0x00040400 },
+ { GMMx15C0_ADDRESS, 0x000C1401 }
};
GMM_REG_ENTRY GmcMiscInitTable [] = {
{ GMMx25C8_ADDRESS, 0x007F605F },
{ GMMx25CC_ADDRESS, 0x00007F7E },
- { 0x20B4, 0x00000000 },
+ { GMMx20B4_ADDRESS, 0x00000000 },
{ GMMx28C8_ADDRESS, 0x00000003 },
{ GMMx202C_ADDRESS, 0x0003FFFF }
};
*/
GMM_REG_ENTRY GmcRemoveBlackoutTable [] = {
{ GMMx25C0_ADDRESS, 0x00000000 },
- { 0x20EC, 0x000001FC },
- { 0x20D4, 0x00000016 }
+ { GMMx20EC_ADDRESS, 0x000001FC },
+ { GMMx20D4_ADDRESS, 0x00000016 }
};
TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = {
{ GMMx2B90_ADDRESS, 0x002e09d7 },
{ GMMx2B8C_ADDRESS, 0x0000015e },
{ GMMx2B90_ADDRESS, 0x00170a26 },
- { 0x2B94, 0x5d976000 },
- { 0x2B98, 0x410af020 }
+ { GMMx2B94_ADDRESS, 0x5d976000 },
+ { GMMx2B98_ADDRESS, 0x410af020 }
};
TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = {
GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH
},
{
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS),
+ MAKE_SBDFO (0, 0, 0x18, 2, D18F2x94_ADDRESS),
GMMx284C_ADDRESS,
- D18F2x094_BankSwizzleMode_OFFSET,
- D18F2x094_BankSwizzleMode_WIDTH,
+ D18F2x94_BankSwizzleMode_OFFSET,
+ D18F2x94_BankSwizzleMode_WIDTH,
GMMx284C_BankSwizzleMode_OFFSET,
GMMx284C_BankSwizzleMode_WIDTH
},
GMMx284C_BankSwap_OFFSET,
GMMx284C_BankSwap_WIDTH
},
+ {
+ MAKE_SBDFO (0, 0, 0x18, 2, D18F2x110_ADDRESS),
+ GMMx2854_ADDRESS,
+ 0,
+ 31,
+ 0,
+ 31
+ },
{
MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS),
GMMx2858_ADDRESS,
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
IN GFX_PLATFORM_CONFIG *Gfx
);
+VOID
+GfxFmGmcAllowPstateHigh (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
#endif
#include "GnbGfx.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include "GfxStrapsInit.h"
+#include "GfxConfigData.h"
#include "OptionGnb.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 46545 $ @e \$Date: 2011-02-04 13:42:42 -0700 (Fri, 04 Feb 2011) $
*
*/
/*
#ifndef _GFXCONFIGDATA_H_
#define _GFXCONFIGDATA_H_
-AGESA_STATUS
-GfxAllocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT GFX_PLATFORM_CONFIG **Gfx,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- );
-
-AGESA_STATUS
-GfxLocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT GFX_PLATFORM_CONFIG **Gfx
- );
-
AGESA_STATUS
GfxEnableGmmAccess (
IN OUT GFX_PLATFORM_CONFIG *Gfx
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
/// DCT channel information
typedef struct {
- D18F2x094_STRUCT D18F2x094; ///< Register 0x94
- D18F2x084_STRUCT D18F2x084; ///< Register 0x84
- D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C
+ D18F2x94_STRUCT D18F2x094; ///< Register 0x94
+ D18F2x84_STRUCT D18F2x084; ///< Register 0x84
+ D18F2x8C_STRUCT D18F2x08C; ///< Register 0x8C
D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40
D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41
} DCT_CHANNEL_INFO;
*----------------------------------------------------------------------------------------
*/
+VOID
+GfxGmcSetMemoryAddressTranslation (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcDisableClockGating (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcInitializeRegisterEngine (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcDctMemoryChannelInfo (
+ IN UINT8 Channel,
+ OUT DCT_CHANNEL_INFO *DctChannelInfo,
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcInitializeSequencerModel (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcInitializeFbLocation (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcSecureGarlicAccess (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcPerformanceTuning (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcMiscInit (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcLockCriticalRegisters (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcRemoveBlackout (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcEnableClockGating (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcUmaSteering (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcInitializeC6Aperture (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+VOID
+GfxGmcInitializePowerGating (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+AGESA_STATUS
+GfxGmcInit (
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
)
{
GnbLibCpuPciIndirectRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS),
+ MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS),
D18F2x0F4_x40_ADDRESS,
&DctChannelInfo->D18F2x0F4_x40.Value,
GnbLibGetHeader (Gfx)
);
GnbLibCpuPciIndirectRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS),
+ MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2xF0_ADDRESS : D18F2x1F0_ADDRESS),
D18F2x0F4_x41_ADDRESS,
&DctChannelInfo->D18F2x0F4_x41.Value,
GnbLibGetHeader (Gfx)
);
GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS),
+ MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x84_ADDRESS : D18F2x184_ADDRESS),
AccessWidth32,
&DctChannelInfo->D18F2x084.Value,
GnbLibGetHeader (Gfx)
);
GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS),
+ MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x94_ADDRESS : D18F2x194_ADDRESS),
AccessWidth32,
&DctChannelInfo->D18F2x094.Value,
GnbLibGetHeader (Gfx)
);
GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS),
+ MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x8C_ADDRESS : D18F2x18C_ADDRESS),
AccessWidth32,
&DctChannelInfo->D18F2x08C.Value,
GnbLibGetHeader (Gfx)
GfxGmcEnableClockGating (Gfx);
}
GfxGmcInitializePowerGating (Gfx);
+ GfxFmGmcAllowPstateHigh (Gfx);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n");
return Status;
}
+
#include "amdlib.h"
#include "Ids.h"
#include "Gnb.h"
+#include "GnbPcie.h"
#include "GnbGfx.h"
#include GNB_MODULE_DEFINITIONS (GnbGfxConfig)
#include "GfxConfigData.h"
#include "GfxStrapsInit.h"
#include "GfxGmcInit.h"
#include "GfxInitAtMidPost.h"
+#include "GnbGfxFamServices.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE
/*----------------------------------------------------------------------------------------
*/
-
/*----------------------------------------------------------------------------------------*/
/**
* Init GFX at Mid Post.
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
- GfxSetIdleVoltageMode (Gfx);
+ GfxFmSetIdleVoltageMode (Gfx);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
#include "GnbPcie.h"
#include "GnbGfx.h"
#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
+#include GNB_MODULE_DEFINITIONS (GnbGfxConfig)
#include "GfxStrapsInit.h"
#include "GfxLib.h"
#include "GfxConfigData.h"
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 41507 $ @e \$Date: 2010-11-05 23:13:47 +0800 (Fri, 05 Nov 2010) $
+ * @e \$Revision: 48924 $ @e \$Date: 2011-03-14 12:45:15 -0600 (Mon, 14 Mar 2011) $
*
*/
/*
#include "GfxConfigData.h"
#include "GfxRegisterAcc.h"
#include "GfxFamilyServices.h"
+#include "GnbGfxFamServices.h"
#include "GfxIntegratedInfoTableInit.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
*----------------------------------------------------------------------------------------
*/
-
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = {
0x80040810,
0x00040810,
};
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+UINT32
+GfxLibGetCsrPhySrPllPdMode (
+ IN UINT8 Channel,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+GfxIntegratedInfoTableEntry (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+GfxLibGetDisDllShutdownSR (
+ IN UINT8 Channel,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
VOID
GfxIntegratedInfoInitDispclkTable (
IN PP_FUSE_ARRAY *PpFuseArray,
D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A;
GnbLibCpuPciIndirectRead (
- MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS),
+ MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x98_ADDRESS : D18F2x198_ADDRESS),
D18F2x09C_x0D0FE00A_ADDRESS,
&D18F2x09C_x0D0FE00A.Value,
StdHeader
IN AMD_CONFIG_PARAMS *StdHeader
)
{
- D18F2x090_STRUCT D18F2x090;
+ D18F2x90_STRUCT D18F2x090;
GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS),
+ MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x90_ADDRESS : D18F2x190_ADDRESS),
AccessWidth32,
&D18F2x090.Value,
StdHeader
SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate;
+ SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
+// SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
)
{
UINTN Index;
+ UINTN TargetIndex;
+ UINTN ValidSclkStateMask;
+ UINT8 TempDID;
UINT8 SclkVidArray[4];
UINTN AvailSclkIndex;
ATOM_AVAILABLE_SCLK_LIST *AvailSclkList;
}
}
} while (Sorting);
+
+ if (PpFuseArray->GpuBoostCap == 1) {
+ IntegratedInfoTable->SclkDpmThrottleMargin = PpFuseArray->SclkDpmThrottleMargin;
+ IntegratedInfoTable->SclkDpmTdpLimitPG = PpFuseArray->SclkDpmTdpLimitPG;
+ IntegratedInfoTable->EnableBoost = PpFuseArray->GpuBoostCap;
+ IntegratedInfoTable->SclkDpmBoostMargin = PpFuseArray->SclkDpmBoostMargin;
+ IntegratedInfoTable->SclkDpmTdpLimitBoost = (PpFuseArray->SclkDpmTdpLimit)[5];
+ IntegratedInfoTable->ulBoostEngineCLock = GfxFmCalculateClock ((PpFuseArray->SclkDpmDid)[5], GnbLibGetHeader (Gfx));
+ IntegratedInfoTable->ulBoostVid_2bit = (PpFuseArray->SclkDpmVid)[5];
+
+ ValidSclkStateMask = 0;
+ TargetIndex = 0;
+ for (Index = 0; Index < 6; Index++) {
+ ValidSclkStateMask |= (PpFuseArray->SclkDpmValid)[Index];
+ }
+ TempDID = 0x7F;
+ for (Index = 0; Index < 6; Index++) {
+ if ((ValidSclkStateMask & ((UINTN)1 << Index)) != 0) {
+ if ((PpFuseArray->SclkDpmDid)[Index] <= TempDID) {
+ TempDID = (PpFuseArray->SclkDpmDid)[Index];
+ TargetIndex = Index;
+ }
+ }
+ }
+ IntegratedInfoTable->GnbTdpLimit = (PpFuseArray->SclkDpmTdpLimit)[TargetIndex];
+ }
+
}
/*----------------------------------------------------------------------------------------*/
&D18F3x64.Value,
GnbLibGetHeader (Gfx)
);
- IntegratedInfoTable->ucHtcTmpLmt = (UCHAR)D18F3x64.Field.HtcTmpLmt;
- IntegratedInfoTable->ucHtcHystLmt = (UCHAR)D18F3x64.Field.HtcHystLmt;
+ IntegratedInfoTable->ucHtcTmpLmt = (UCHAR) (D18F3x64.Field.HtcTmpLmt / 2 + 52);
+ IntegratedInfoTable->ucHtcHystLmt = (UCHAR) (D18F3x64.Field.HtcHystLmt / 2);
}
/*----------------------------------------------------------------------------------------*/
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n");
return AGESA_SUCCESS;
}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set idle voltage mode for GFX
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxSetIdleVoltageMode (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
-}
IN GFX_PLATFORM_CONFIG *Gfx
);
-VOID
-GfxSetIdleVoltageMode (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
#endif
#include "OptionGnb.h"
#include "GnbLibFeatures.h"
+#include "GnbInterface.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
+ * @e \$Revision: 47417 $ @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
*
*/
/*
#include "Gnb.h"
#include "OptionGnb.h"
#include "GnbLibFeatures.h"
+#include "GnbInterface.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GNBINITATENV_FILECODE
/*----------------------------------------------------------------------------------------
GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex;
GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum;
GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate;
+ GnbEnvConfigPtr->LvdsMiscControl.Value = 0;
+ GnbEnvConfigPtr->LvdsMiscControl.Value = UserOptions.CfgLvdsMiscControl.Value;
+ GnbEnvConfigPtr->PcieRefClkSpreadSpectrum = UserOptions.CfgPcieRefClkSpreadSpectrum;
}
/*----------------------------------------------------------------------------------------*/
#include "Gnb.h"
#include "OptionGnb.h"
#include "GnbLibFeatures.h"
+#include "GnbInterface.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE
/*----------------------------------------------------------------------------------------
#include "Gnb.h"
#include "OptionGnb.h"
#include "GnbLibFeatures.h"
+#include "GnbInterface.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GNBINITATMID_FILECODE
/*----------------------------------------------------------------------------------------
#include "OptionGnb.h"
#include "Ids.h"
#include "GnbLibFeatures.h"
+#include "GnbInterface.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE
/*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Gnb.h"
+#include "GnbInterface.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+VOID
+GnbLibPciIndirectReadField (
+ IN UINT32 Address,
+ IN UINT32 IndirectAddress,
+ IN UINT8 FieldOffset,
+ IN UINT8 FieldWidth,
+ OUT UINT32 *Value,
+ IN VOID *Config
+ );
/*----------------------------------------------------------------------------------------*/
#include "Porting.h"
#include "AMD.h"
#include "GnbLibPciAcc.h"
+#include "GnbLibCpuAcc.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE
/*----------------------------------------------------------------------------------------
#include "AMD.h"
#include "heapManager.h"
#include "GnbLibPciAcc.h"
+#include "GnbLibHeap.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE
/*----------------------------------------------------------------------------------------
typedef struct _GNB_PCI_SCAN_DATA {
GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device
AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header
-};
+} Unused_GNB_PCI_SCAN_DATA;
#define PCIE_CAP_ID 0x10
#define PCIE_LINK_CAP_REGISTER 0x0C
IN AMD_CONFIG_PARAMS *StdHeader
);
+UINT16
+GnbLibFindPcieExtendedCapability (
+ IN UINT32 Address,
+ IN UINT16 ExtendedCapabilityId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
VOID
GnbLibPciScan (
IN PCI_ADDR Start,
#include "heapManager.h"
#include "Gnb.h"
#include "GnbGfx.h"
+#include "GnbGfxConfig.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
+#include "GfxConfigData.h"
#include "GfxConfigPost.h"
#include "OptionGnb.h"
#include "Filecode.h"
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+GfxConfigEnvInterface (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
IDS_ERROR_TRAP;
return AGESA_FATAL;
}
- (*Gfx)->StdHeader = (PVOID) StdHeader;
+ (*Gfx)->StdHeader = StdHeader;
return AGESA_SUCCESS;
}
Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex;
Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum;
Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate;
+ Gfx->LvdsMiscControl.Value = EnvParamsPtr->GnbEnvConfiguration.LvdsMiscControl.Value;
+ Gfx->PcieRefClkSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.PcieRefClkSpreadSpectrum;
GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader);
}
GNB_DEBUG_CODE (
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+GfxConfigPostInterface (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
/*----------------------------------------------------------------------------------------*/
Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
}
- Gfx->StdHeader = (PVOID) StdHeader;
+ Gfx->StdHeader = StdHeader;
Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include "GnbGfxFamServices.h"
+#include "GfxEnumConnectors.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE
*----------------------------------------------------------------------------------------
*/
+EXT_CONNECTOR_INFO*
+GfxIntegratedExtConnectorInfo (
+ IN UINT8 ConnectorType
+ );
+
+EXT_DISPLAY_DEVICE_INFO*
+GfxIntegratedExtDisplayDeviceInfo (
+ IN UINT8 DisplayDeviceEnum,
+ IN UINT8 DisplayDeviceIndex
+ );
+
AGESA_STATUS
GfxIntegratedEnumConnectorsForDevice (
IN UINT8 DisplayDeviceEnum,
BOOLEAN Valid; ///< State valid
UINT32 Sclk; ///< Sclk in kHz
UINT8 Vid; ///< VID index
+ UINT16 Tdp; ///< Tdp limit
} DPM_STATE;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+UINT16
+GfxPowerPlayLocateTdp (
+ IN PP_FUSE_ARRAY *PpFuses,
+ IN UINT32 Sclk,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+SW_STATE*
+GfxPowerPlayCreateSwState (
+ IN OUT SW_STATE *SwStateArray
+ );
+
+UINT8
+GfxPowerPlayCreateDpmState (
+ IN DPM_STATE *DpmStateArray,
+ IN UINT32 Sclk,
+ IN UINT8 Vid,
+ IN UINT16 Tdp
+ );
+
+UINT8
+GfxPowerPlayAddDpmState (
+ IN DPM_STATE *DpmStateArray,
+ IN UINT32 Sclk,
+ IN UINT8 Vid,
+ IN UINT16 Tdp
+ );
+
+VOID
+GfxPowerPlayAddDpmStateToSwState (
+ IN OUT SW_STATE *SwStateArray,
+ IN UINT8 DpmStateIndex
+ );
+
+UINT32
+GfxPowerPlayCopyStateInfo (
+ IN OUT STATE_ARRAY *StateArray,
+ IN SW_STATE *SwStateArray,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+GfxPowerPlayCopyClockInfo (
+ IN CLOCK_INFO_ARRAY *ClockInfoArray,
+ IN DPM_STATE *DpmStateArray,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+GfxPowerPlayCopyNonClockInfo (
+ IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray,
+ IN SW_STATE *SwStateArray,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+GfxPowerPlayIsFusedStateValid (
+ IN UINT8 Index,
+ IN PP_FUSE_ARRAY *PpFuses,
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
+
+UINT16
+GfxPowerPlayGetClassificationFromFuses (
+ IN UINT8 Index,
+ IN PP_FUSE_ARRAY *PpFuses,
+ IN GFX_PLATFORM_CONFIG *Gfx
+ );
VOID
GfxIntegratedDebugDumpPpTable (
IN GFX_PLATFORM_CONFIG *Gfx
);
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Locate existing tdp
+ *
+ *
+ * @param[in ] PpFuses Pointer to PP_FUSE_ARRAY
+ * @param[in] Sclk Sclk in 10kHz
+ * @param[in] StdHeader Standard configuration header
+ * @retval Tdp limit in DPM state array
+ */
+
+UINT16
+GfxPowerPlayLocateTdp (
+ IN PP_FUSE_ARRAY *PpFuses,
+ IN UINT32 Sclk,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 Index;
+ UINT32 DpmIndex;
+ UINT32 DpmSclk;
+ UINT32 DeltaSclk;
+ UINT32 MinDeltaSclk;
+
+ DpmIndex = 0;
+ MinDeltaSclk = 0xFFFFFFFF;
+ for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
+ if (PpFuses->SclkDpmDid[Index] != 0) {
+ DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader);
+ DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk);
+ if (DeltaSclk < MinDeltaSclk) {
+ MinDeltaSclk = MinDeltaSclk;
+ DpmIndex = Index;
+ }
+ }
+ }
+ return PpFuses->SclkDpmTdpLimit[DpmIndex];
+}
+
/*----------------------------------------------------------------------------------------*/
/**
* Create new software state
* @param[in, out] DpmStateArray Pointer to DPM state array
* @param[in] Sclk SCLK in kHz
* @param[in] Vid Vid index
+ * @param[in] Tdp Tdp limit
* @retval Index of state entry in DPM state array
*/
GfxPowerPlayCreateDpmState (
IN DPM_STATE *DpmStateArray,
IN UINT32 Sclk,
- IN UINT8 Vid
+ IN UINT8 Vid,
+ IN UINT16 Tdp
)
{
UINT8 Index;
DpmStateArray[Index].Sclk = Sclk;
DpmStateArray[Index].Vid = Vid;
DpmStateArray[Index].Valid = TRUE;
+ DpmStateArray[Index].Tdp = Tdp;
return Index;
}
}
* @param[in, out] DpmStateArray Pointer to DPM state array
* @param[in] Sclk SCLK in kHz
* @param[in] Vid Vid index
+ * @param[in] Tdp Tdp limit
* @retval Index of state entry in DPM state array
*/
GfxPowerPlayAddDpmState (
IN DPM_STATE *DpmStateArray,
IN UINT32 Sclk,
- IN UINT8 Vid
+ IN UINT8 Vid,
+ IN UINT16 Tdp
)
{
UINT8 Index;
return Index;
}
}
- return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid);
+ return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid, Tdp);
}
/*----------------------------------------------------------------------------------------*/
* @param[in] DpmStateArray Pointer to DPM state array
* @param[in] StdHeader Standard configuration header
*/
-
UINT32
GfxPowerPlayCopyClockInfo (
IN CLOCK_INFO_ARRAY *ClockInfoArray,
ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16);
ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk);
ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid;
+ ClockInfoArray->ClockInfo[ClkStateIndex].tdpLimit = DpmStateArray[Index].Tdp;
ClkStateIndex++;
}
}
* @param[in] Gfx Gfx configuration info
* @retval State classification
*/
-
UINT16
GfxPowerPlayGetClassificationFromFuses (
IN UINT8 Index,
UINT32 NonClockArrayLength;
SW_STATE *State;
PP_FUSE_ARRAY *PpFuses;
+ UINT32 Sclk;
PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
ASSERT (PpFuses != NULL);
}
for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) {
if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) {
- UINT32 Sclk;
Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0;
if (Sclk != 0) {
- ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex]);
+ ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex], PpFuses->SclkDpmTdpLimit[DpmFuseIndex]);
GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
}
}
// Create Boot State
State = GfxPowerPlayCreateSwState (SwStateArray);
State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT;
- ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0);
+ Sclk = 200 * 100;
+ ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx)));
GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
// Create Thermal State
State = GfxPowerPlayCreateSwState (SwStateArray);
State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL;
- ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0);
+ Sclk = GfxFmCalculateClock (PpFuses->SclkThermDid, GnbLibGetHeader (Gfx));
+ ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, 0, GfxPowerPlayLocateTdp (PpFuses, Sclk, GnbLibGetHeader (Gfx)));
GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
//Copy state info to actual PP table
IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n",
ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16)
);
- IDS_HDT_CONSOLE (GFX_MISC, " Cac = %d\n",
- ClockInfoArrayPtr->ClockInfo[Index].leakage
- );
IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n",
ClockInfoArrayPtr->ClockInfo[Index].vddcIndex
);
+ IDS_HDT_CONSOLE (GFX_MISC, " tdpLimit = %d\n",
+ ClockInfoArrayPtr->ClockInfo[Index].tdpLimit
+ );
}
}
USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz)
UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz)
UCHAR vddcIndex; ///< 2-bit VDDC index;
- UCHAR leakage; ///< Absolute Cac value;
- UCHAR rsv; ///< Reserved
+ USHORT tdpLimit; ///< TDP Limit
USHORT rsv1; ///< Reserved
ULONG rsv2[2]; ///< Reserved
} ATOM_PPLIB_SUMO_CLOCK_INFO;
#include "amdlib.h"
#include "Gnb.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
+#include "GnbNbInitLibV1.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE
*/
extern UINT8 AlibSsdt[];
+extern AGESA_STATUS PcieFmAlibBuildAcpiTable (VOID *AlibSsdtPtr, AMD_CONFIG_PARAMS *StdHeader);
+;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
VOID
STATIC
-PcieAlibSetPortGenCapabilityCallback (
+PcieAlibSetPortMaxSpeedCallback (
+ IN PCIe_ENGINE_CONFIG *Engine,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+STATIC
+PcieAlibSetPortOverrideSpeedCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
// Copy template to buffer
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
- AmlObjName = '10DA';
+// AmlObjName = '10DA';
+ AmlObjName = Int32FromChar ('1', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
if (AmlObjPtr != NULL) {
- UINT64 MsrRegister;
- LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader);
- if ((MsrRegister & BIT0) != 0 && (MsrRegister & 0xFFFFFFFF00000000) == 0) {
- *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrRegister & 0xFFFFF00000);
+ UINT64 MsrReg;
+ LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
+ if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) {
+ *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000);
} else {
Status = AGESA_ERROR;
}
// Set voltage configuration
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
- AmlObjName = '30DA';
+// AmlObjName = '30DA';
+ AmlObjName = Int32FromChar ('3', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
BootUpVidIndex = (UINT8) Index;
}
}
- AmlObjName = '40DA';
+// AmlObjName = '40DA';
+ AmlObjName = Int32FromChar ('4', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
} else {
Status = AGESA_ERROR;
}
- AmlObjName = '50DA';
+// AmlObjName = '50DA';
+ AmlObjName = Int32FromChar ('5', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
}
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
- AmlObjName = '20DA';
+// AmlObjName = '20DA';
+ AmlObjName = Int32FromChar ('2', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
} else {
Status = AGESA_ERROR;
}
- AmlObjName = '60DA';
+// AmlObjName = '60DA';
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
+ AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+ ASSERT (AmlObjPtr != NULL);
+ if (AmlObjPtr != NULL) {
+ PcieConfigRunProcForAllEngines (
+ DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+ PcieAlibSetPortMaxSpeedCallback,
+ (UINT8*)((UINT8*)AmlObjPtr + 7),
+ Pcie
+ );
+ } else {
+ Status = AGESA_ERROR;
+ }
+// AmlObjName = '80DA';
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PcieAlibSetPortGenCapabilityCallback,
+ PcieAlibSetPortOverrideSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
- AmlObjName = '70DA';
+// AmlObjName = '70DA';
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
ASSERT (FALSE);
Status = AGESA_ERROR;
}
- if (Status == AGESA_ERROR) {
+ if (Status == AGESA_SUCCESS) {
+ Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader);
+ }
+ if (Status != AGESA_SUCCESS) {
//Shrink table length to size of the header
((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
}
/*----------------------------------------------------------------------------------------*/
/**
- * Callback to init max port Gen capability
+ * Callback to init max port speed capability
*
*
*
VOID
STATIC
-PcieAlibSetPortGenCapabilityCallback (
+PcieAlibSetPortMaxSpeedCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
- UINT8 *PsppMaxPortCapbilityArray;
- PsppMaxPortCapbilityArray = (UINT8*) Buffer;
+ UINT8 *PsppMaxPortSpeedPackage;
+ PsppMaxPortSpeedPackage = (UINT8*) Buffer;
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
- PsppMaxPortCapbilityArray[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie) + 1;
+ PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie);
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init max port speed capability
+ *
+ *
+ *
+ *
+ * @param[in] Engine Pointer to engine config descriptor
+ * @param[in, out] Buffer Not used
+ * @param[in] Pcie Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PcieAlibSetPortOverrideSpeedCallback (
+ IN PCIe_ENGINE_CONFIG *Engine,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ )
+{
+ UINT8 *PsppOverridePortSpeedPackage;
+ PsppOverridePortSpeedPackage = (UINT8*) Buffer;
+ if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+ PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode;
+ }
+ if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
+ PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1;
}
}
PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane;
PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane;
PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId;
- PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId);
+// PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId);
+ PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130u | (PcieEngineGetParentWrapper (Engine)->WrapId);
PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie);
}
#define DEF_PSPP_STATE_AC 0
#define DEF_PSPP_STATE_DC 1
+#define DEF_TRAINING_STATE_COMPLETE 0
+#define DEF_TRAINING_STATE_DETECT_PRESENCE 1
+#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2
+#define DEF_TRAINING_GEN2_WORKAROUND 3
+#define DEF_TRAINING_STATE_NOT_PRESENT 4
+#define DEF_TRAINING_DEVICE_PRESENT 5
+#define DEF_TRAINING_STATE_RELEASE_TRAINING 6
+#define DEF_TRAINING_STATE_REQUEST_RESET 7
+#define DEF_TRAINING_STATE_EXIT 8
+
+#define DEF_LINK_SPEED_GEN1 1
+#define DEF_LINK_SPEED_GEN2 2
+
+#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0
+#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1
+
+#define DEF_PORT_NOT_ALLOCATED 0
+#define DEF_PORT_ALLOCATED 1
+
+#define DEF_PCIE_LANE_POWERON 1
+#define DEF_PCIE_LANE_POWEROFF 0
+#define DEF_PCIE_LANE_POWEROFFUNUSED 2
+
+#define DEF_SCARTCH_PSPP_START_OFFSET 0
+#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1
+#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5
+#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6
+#define DEF_SCARTCH_PSPP_REQ_OFFSET 16
+
+#define DEF_LINKWIDTH_ACTIVE 0
+#define DEF_LINKWIDTH_MAX_PHY 1
+
+#define TRUE 1
+#define FALSE 0
+
#endif
Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6
Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7
Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8
+ Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev9
}
)
varPortInfo
)
+
+ Name (varStringBuffer, Buffer (256) {})
+
/*----------------------------------------------------------------------------------------*/
/**
* Master control method
return (0)
}
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCI config register
- *
- * Arg0 - Port Index
- *
- */
-
/*----------------------------------------------------------------------------------------*/
/**
* Read PCI config register through MMIO
* Arg0 - PCI address Bus/device/func
* Arg1 - Register offset
*/
- Method (procPciDwordRead, 2, NotSerialized) {
+ Method (procPciDwordRead, 2, Serialized) {
Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
Add (Arg1, Local0, Local0)
OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
* Arg1 - Register offset
* Arg2 - Value
*/
- Method (procPciDwordWrite, 3, NotSerialized) {
+ Method (procPciDwordWrite, 3, Serialized) {
Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
Add (Arg1, Local0, Local0)
OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
* Arg2 - AND mask
* Arg3 - OR mask
*/
- Method (procPciDwordRMW, 4, NotSerialized) {
+ Method (procPciDwordRMW, 4, Serialized) {
Store (procPciDwordRead (Arg0, Arg1), Local0)
Or (And (Local0, Arg2), Arg3, Local0)
procPciDwordWrite (Arg0, Arg1, Local0)
Store (1, Local0)
while (LEqual (Local0, 1)) {
Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1)
- if (LNotEqual (Local1, 0)) {
+ if (LEqual (Local1, 0)) {
+ break
+ }
if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) {
Store (0, Local0)
} else {
Increment (Local1)
}
}
- }
return (Local1)
}
* Arg0 - Aspm
* Arg1 - 0: Read, 1: Write
*/
- Method (procPcieSbAspmControl, 2, NotSerialized) {
+ Method (procPcieSbAspmControl, 2, Serialized) {
// Create an opregion for PM IO Registers
OperationRegion (PMIO, SystemIO, 0xCD6, 0x2)
Field (PMIO, ByteAcc, NoLock, Preserve)
Or (And (Local0, 0xfffffffc), Arg0, Local0)
Store (Local0, ABDA)
}
-
- }
-
-#ifdef ALIB_DEBUG
- Name (ABUF, Buffer (256) {})
- Name (AFUN, 0xff)
- Method (ADBG, 0, Serialized) {
- ALIB (AFUN, ABUF);
}
- Alias (procPciDwordRead, AXPR)
-#endif
*
*/
/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of Advanced Micro Devices, Inc. nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+****************************************************************************
+*
+*/
+ External(\_SB.ALIC, MethodObj)
+
+ Name (varStartPhyLane, 0)
+ Name (varEndPhyLane, 0)
+ Name (varStartCoreLane, 0)
+ Name (varEndCoreLane, 0)
+ Name (varWrapperId, 0)
+ Name (varPortId, 0)
/*----------------------------------------------------------------------------------------*/
/**
*
* Arg0 - Data Buffer
*/
- Method (procPcieSetBusWidth, 1, Serialized) {
+ Method (procPcieSetBusWidth, 1, NotSerialized) {
Store (Buffer (256) {}, Local7)
CreateWordField (Local7, 0x0, varReturnBufferLength)
CreateWordField (Local7, 0x2, varReturnBusWidth)
CreateByteField (Arg0, 0x2, varArgBusWidth)
- //@todo deternime correct lane bitmap (check for reversal) gate/ungate unused lanes
+ //deternime correct lane bitmap (check for reversal) gate/ungate unused lanes
Store (3, varReturnBufferLength)
Store (varArgBusWidth, varReturnBusWidth)
return (Local7)
/**
* PCIe port hotplug
*
- * Arg0 - Data Buffer
- * Local7 - Return buffer
+ * Arg0 - Data Buffer
+ * Retval - Return buffer
*/
Method (procPciePortHotplug, 1, Serialized) {
Store ("PciePortHotplug Enter", Debug)
- Store (Buffer (256) {}, Local7)
- CreateWordField (Local7, 0x0, varReturnBufferLength)
- CreateByteField (Local7, 0x2, varReturnStatus)
- CreateByteField (Local7, 0x3, varReturnDeviceStatus)
- CreateWordField (Arg0, 0x2, varPortBdf)
- CreateByteField (Arg0, 0x4, varHotplugState)
- Subtract (ShiftRight (varPortBdf, 3), 2, Local1);
- if (LEqual(varHotplugState, 1)) {
+ Store (DerefOf (Index (Arg0, 4)), varHotplugStateLocal0)
+ Store (DerefOf (Index (Arg0, 2)), varPortIndexLocal1)
+
+ Subtract (ShiftRight (varPortBdfLocal1, 3), 2, varPortIndexLocal1)
+ if (LEqual(varHotplugStateLocal0, 1)) {
// Enable port
- Store (procPciePortEnable (Local1), varHotplugState);
+ Store (DEF_TRAINING_STATE_RELEASE_TRAINING, Local2)
} else {
// Disable port
- Store (procPciePortDisable (Local1), varHotplugState);
+ Store (DEF_TRAINING_STATE_NOT_PRESENT, Local2)
}
+
+ Store (procPciePortTraining (varPortIndexLocal1, Local2), varHotplugStateLocal0)
+
+ Store (Buffer (10) {}, Local7)
+ CreateWordField (Local7, 0x0, varReturnBufferLength)
+ CreateByteField (Local7, 0x2, varReturnStatus)
+ CreateByteField (Local7, 0x3, varReturnDeviceStatus)
Store (0x4, varReturnBufferLength)
Store (0x0, varReturnStatus)
- Store (varHotplugState, varReturnDeviceStatus)
+ Store (varHotplugStateLocal0, varReturnDeviceStatus)
Store ("PciePortHotplug Exit", Debug)
return (Local7)
}
-
+ Name (varSpeedRequest, Buffer (10) {0,0,0,0,0,0,0,0,0,0})
+
/*----------------------------------------------------------------------------------------*/
/**
- * Enable PCIe port
- *
- * 1) Ungate lanes
- * 2) Enable Lanes
- * 3) Train port
- * 4) Disable unused lanes
- * 5) Gate unused lanes
+ * Train PCIe port
+ *
*
* Arg0 - Port Index
- *
+ * Arg1 - Initial state
*/
- Method (procPciePortEnable, 1, NotSerialized) {
- Store ("PciePortEnable Enter", Debug)
- Name (varLinkIsLinkReversed, 0)
+ Method (procPciePortTraining, 2, Serialized) {
+ Store ("PciePortTraining Enter", Debug)
+ Store (DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT, varResultLocal4)
Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType)
- if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) {
+ // Check if port supports basic hotplug
+ Store (DerefOf (Index (Local7, DEF_OFFSET_LINK_HOTPLUG)), varTempLocal1)
+ if (LNotEqual (varTempLocal1, DEF_BASIC_HOTPLUG)) {
Store (" No action.[Hotplug type]", Debug)
- Store ("PciePortEnable Exit", Debug)
- return (1)
+ Store ("procPciePortTraining Exit", Debug)
+ return (varResultLocal4)
}
- // Poweron phy lanes
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
- procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0)
- // Enable lanes
- CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane)
- CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane)
- procPcieLaneEnableControl (Arg0, varStartPhyLane, varEndPhyLane, 0)
- //Release training
- procPcieTrainingControl (Arg0, 0)
- //Train link
- Store (procPcieCheckDevicePrecence (Arg0), Local1)
- if (LEqual (Local1, 1)) {
- Store (" Device detected", Debug)
- Store (procPcieIsPortReversed (Arg0), varLinkIsLinkReversed)
- Subtract (procPcieGetLinkWidth (Arg0, 1), procPcieGetLinkWidth (Arg0, 0), Local2)
- if (LNotEqual (Local2, 0)) {
- //There is unused lanes after device plugged
- if (LNotEqual(varLinkIsLinkReversed, 0)) {
- Add (varStartCoreLane, Local2, Local3)
- Store (varEndCoreLane, Local4)
- } else {
- Subtract (varEndCoreLane, Local2, Local4)
- Store (varStartCoreLane, Local3)
+ Store (Arg1, varStateLocal2)
+ while (LNotEqual (varStateLocal2, DEF_TRAINING_STATE_EXIT)) {
+ if (LEqual (varStateLocal2, DEF_TRAINING_STATE_RELEASE_TRAINING)) {
+ Store (" State: Release training", Debug)
+ // Remove link speed override
+ Store (0, Index (varOverrideLinkSpeed, Arg0))
+ // Enable link width upconfigure
+ procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x0000)
+ // Request Max link speed for hotplug by going to AC state
+ Store (0, varPsppAcDcOverride)
+ procApplyPsppState ()
+ // Power on/enable port lanes
+ procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWERON)
+ // Release training
+ procPcieTrainingControl (Arg0, 0)
+ // Move to next state to check presence detection
+ Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2)
+ // Initialize retry count
+ Store(0, varCountLocal3)
+ }
+ if (LEqual (varStateLocal2, DEF_TRAINING_STATE_DETECT_PRESENCE)) {
+ Store (" State: Detect presence", Debug)
+ And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, varTempLocal1)
+ if (LGreater (varTempLocal1, 0x4)) {
+ // device connection detected move to next state
+ Store (DEF_TRAINING_STATE_PRESENCE_DETECTED, varStateLocal2)
+ // reset retry counter
+ Store(0, varCountLocal3)
+ continue
}
- procPcieLaneEnableControl (Arg0, Local3, Local4, 1)
- if (LGreater (varStartPhyLane, varEndPhyLane)) {
- Store (varEndPhyLane, Local3)
- Store (varStartPhyLane, Local4)
+ if (LLess (varCountLocal3, 80)) {
+ Sleep (1)
+ Increment (varCountLocal3)
} else {
- Store (varEndPhyLane, Local4)
- Store (varStartPhyLane, Local3)
+ // detection time expired move to device not present state
+ Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
}
- if (LNotEqual(varLinkIsLinkReversed, 0)) {
- Add (Local3, Local2, Local3)
- } else {
- Subtract (Local4, Local2, Local4)
+ }
+ if (LEqual (varStateLocal2, DEF_TRAINING_STATE_PRESENCE_DETECTED)) {
+ Store (" State: Device detected", Debug)
+ Store (procPciePortIndirectRegisterRead (Arg0, 0xa5), varTempLocal1)
+ And (varTempLocal1, 0x3f, varTempLocal1)
+ if (LEqual (varTempLocal1, 0x10)) {
+ Store (DEF_TRAINING_DEVICE_PRESENT, varStateLocal2)
+ continue
+ }
+ if (LLess (varCountLocal3, 80)) {
+ Sleep (1)
+ Increment (varCountLocal3)
+ continue
+ }
+ Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+
+ if (LEqual (DeRefOf (Index (varOverrideLinkSpeed, Arg0)), DEF_LINK_SPEED_GEN1)) {
+ // GEN2 workaround already applied but device not trained successfully move device not present state
+ continue
+ }
+
+ if (LEqual (procPcieCheckForGen2Workaround (Arg0), TRUE)) {
+ Store (" Request Gen2 workaround", Debug)
+ procPciePortIndirectRegisterRMW (Arg0, 0xA2, Not (0x2000), 0x2000)
+ Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0))
+ procPcieSetLinkSpeed (Arg0, DEF_LINK_SPEED_GEN1)
+ Store (DEF_TRAINING_STATE_REQUEST_RESET, varStateLocal2)
}
- procPcieLanePowerControl (Local3, Local4, 1)
}
- Store ("PciePortEnable Exit", Debug)
- return (1)
- }
- Store (" Device detection fail", Debug)
- procPciePortDisable (Arg0)
- Store ("PciePortEnable Exit", Debug)
- return (0)
+ if (LEqual (varStateLocal2, DEF_TRAINING_STATE_NOT_PRESENT)) {
+ Store (" State: Device not present", Debug)
+ procPcieTrainingControl (Arg0, 1)
+ procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFF)
+ // Exclude device from PSPP managment since it is not present
+ Store (DEF_LINK_SPEED_GEN1, Index (varOverrideLinkSpeed, Arg0))
+ Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2)
+ }
+ if (LEqual (varStateLocal2, DEF_TRAINING_STATE_REQUEST_RESET)) {
+ Store (" State: Request Reset", Debug)
+ if (CondRefOf (\_SB.ALIC, Local6)) {
+ Store (" Call ALIC method", Debug)
+ //varTempLocal1 contain port BDF
+ Store(ShiftLeft (Add (Arg0, 2), 3), varTempLocal1)
+ \_SB.ALIC (varTempLocal1, 0)
+ Sleep (2)
+ \_SB.ALIC (varTempLocal1, 1)
+ Store (0, varCountLocal3)
+ Store (DEF_TRAINING_STATE_DETECT_PRESENCE, varStateLocal2)
+ continue
+ }
+ Store (DEF_TRAINING_STATE_NOT_PRESENT, varStateLocal2)
+ }
+ if (LEqual (varStateLocal2, DEF_TRAINING_DEVICE_PRESENT)) {
+ Store (" State: Device present", Debug)
+ Store (DEF_HOTPLUG_STATUS_DEVICE_PRESENT, varResultLocal4)
+ Store (DEF_TRAINING_STATE_COMPLETE, varStateLocal2)
+ procPcieLaneControl (Arg0, DEF_PCIE_LANE_POWEROFFUNUSED)
+ }
+ if (LEqual (varStateLocal2, DEF_TRAINING_STATE_COMPLETE)) {
+
+ Store (1, varPsppAcDcOverride)
+ procApplyPsppState ()
+
+ Store (DEF_TRAINING_STATE_EXIT, varStateLocal2)
+ }
+ }
+ Store ("PciePortTraining Exit", Debug)
+ return (varResultLocal4)
}
- /*----------------------------------------------------------------------------------------*/
+
+ /*----------------------------------------------------------------------------------------*/
/**
- * Disable PCIe port
- *
- * 1) Hold training
- * 2) Disable lanes
- * 3) Gate lanes
+ * Lane control
*
- * Arg0 - Port Index
- *
+ * Arg0 - Port Index
+ * Arg1 - 0 - Power off all lanes / 1 - Power on all Lanes / 2 Power off unused lanes
*/
- Method (procPciePortDisable, 1, NotSerialized) {
- Store ("PciePortDisable Enter", Debug)
+
+ Method (procPcieLaneControl, 2, Serialized) {
+ Store ("PcieLaneControl Enter", Debug)
+ Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+ Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType)
- if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) {
- Store (" No action. [Hotplug type]", Debug)
- Store ("PciePortDisable Exit", Debug)
- return (0)
+#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT
+ Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+ Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
+#endif
+ Store (DerefOf (Index (Local7, DEF_OFFSET_START_CORE_LANE)), varStartCoreLane)
+ Store (DerefOf (Index (Local7, DEF_OFFSET_END_CORE_LANE)), varEndCoreLane)
+
+ if (LEqual (Arg1, DEF_PCIE_LANE_POWEROFF)) {
+ procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1)
+#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT
+ procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1)
+#endif
+ }
+ if (LEqual (Arg1, DEF_PCIE_LANE_POWERON)) {
+#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT
+ procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0)
+#endif
+ procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 0)
+ }
+ if (LNotEqual (Arg1, DEF_PCIE_LANE_POWEROFFUNUSED)) {
+ return (0)
+ }
+ Store (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_ACTIVE), varActiveLinkWidthLocal2)
+ if (LLessEqual (procPcieGetLinkWidth (Arg0, DEF_LINKWIDTH_MAX_PHY), varActiveLinkWidthLocal2)) {
+ // Active link equal max link width, nothing needs to be done
+ return (0)
+ }
+ Store (procPcieIsPortReversed (Arg0), varIsReversedLocal1)
+ //There is unused lanes after device plugged
+ if (LEqual(varIsReversedLocal1, FALSE)) {
+ Store (" Port Not Reversed", Debug)
+ // Link not reversed
+ Add (varStartCoreLane, varActiveLinkWidthLocal2, Local3)
+ Store (varEndCoreLane, Local4)
+ } else {
+ // Link reversed
+ Store (" Port Reversed", Debug)
+ Subtract (varEndCoreLane, varActiveLinkWidthLocal2, Local4)
+ Store (varStartCoreLane, Local3)
+ }
+ procPcieLaneEnableControl (Arg0, Local3, Local4, 1)
+#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT
+ if (LGreater (varStartPhyLane, varEndPhyLane)) {
+ Store (varEndPhyLane, Local3)
+ Store (varStartPhyLane, Local4)
+ } else {
+ Store (varEndPhyLane, Local4)
+ Store (varStartPhyLane, Local3)
}
- //Hold training
- procPcieTrainingControl (Arg0, 1)
- CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane)
- CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane)
- // Disable lane
- procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1)
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
- // Poweroff phy lanes
- procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1)
-
- Store ("PciePortDisable Exit", Debug)
+ if (LEqual(varIsReversedLocal1, FALSE)) {
+ // Not reversed
+ Add (Local3, varActiveLinkWidthLocal2, Local3)
+ } else {
+ // Link reversed
+ Subtract (Local4, varActiveLinkWidthLocal2, Local4)
+ }
+ procPcieLanePowerControl (Local3, Local4, 1)
+#endif
return (0)
}
+
/*----------------------------------------------------------------------------------------*/
+ /**
+ * Check if GEN2 workaround applicable
+ *
+ * Arg0 - Port Index
+ * Retval - TRUE / FALSE
+ */
+
+ Method (procPcieCheckForGen2Workaround, 1, NotSerialized) {
+ Store (Buffer (16) {}, Local1)
+ Store (0x0, Local0)
+ while (LLessEqual (Local0, 0x3)) {
+ Store (procPciePortIndirectRegisterRead (Arg0, Add (Local0, 0xA5)), Local2)
+ Store (Local2, Index (Local1, Multiply (Local0, 4)))
+ Store (ShiftRight (Local2, 8), Index (Local1, Add (Multiply (Local0, 4), 1)))
+ Store (ShiftRight (Local2, 16), Index (Local1, Add (Multiply (Local0, 4), 2)))
+ Store (ShiftRight (Local2, 24), Index (Local1, Add (Multiply (Local0, 4), 3)))
+ Increment (Local0)
+ }
+ Store (0, Local0)
+ while (LLess (Local0, 15)) {
+ if (LAnd (LEqual (DeRefOf (Index (Local1, Local0)), 0x2a), LEqual (DeRefOf (Index (Local1, Add (Local0, 1))), 0x9))) {
+ return (TRUE)
+ }
+ Increment (Local0)
+ }
+ return (FALSE)
+ }
+
+ /*----------------------------------------------------------------------------------------*/
/**
* Is port reversed
- *
+ *
* Arg0 - Port Index
- * Retval - 0 - Not reversed / 1 - Reversed
+ * Retval - 0 - Not reversed / !=0 - Reversed
*/
- Method (procPcieIsPortReversed , 1, NotSerialized) {
+ Method (procPcieIsPortReversed , 1, Serialized) {
Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
+
+ Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+ Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
Store (0, Local0)
if (LGreater (varStartPhyLane, varEndPhyLane)) {
Store (1, Local0)
}
And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1)
- return (Xor (Local0, Local1))
+ return (And (Xor (Local0, Local1), 0x1))
}
/*----------------------------------------------------------------------------------------*/
/**
* Training Control
- *
+ *
* Arg0 - Port Index
- * Arg1 - Hold Training (1) / Release Training (0)
+ * Arg1 - Hold Training (1) / Release Training (0)
*/
Method (procPcieTrainingControl , 2, NotSerialized) {
Store ("PcieTrainingControl Enter", Debug)
Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_PORT_ID, varPortId)
- CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId)
+ Store (DerefOf (Index (Local7, DEF_OFFSET_PORT_ID)), varPortId)
+ Store (
+ Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))),
+ varWrapperId
+ )
procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1);
Store ("PcieTrainingControl Exit", Debug)
}
- /*----------------------------------------------------------------------------------------*/
- /**
- * Check device presence
- *
- * Arg0 - Port Index
- * Retval - 1 - Device present, 0 - Device not present
- */
- Method (procPcieCheckDevicePrecence, 1, NotSerialized) {
- Store ("PcieCheckDevicePrecence Enter", Debug)
- Store (0, Local0)
- Store (0, Local7)
- while (LLess (Local0, 320)) { // @todo for debug only should be 80
- And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, Local1)
- if (LEqual (Local1, 0x10)) {
- Store (1, Local7)
- Store (320, Local0)
- Break
- }
- Stall (250)
- Increment (Local0)
- }
- //Store (Concatenate ("Device Presence Status :", ToHexString (Local7)), Debug)
- Store ("PcieCheckDevicePrecence Exit", Debug)
- return (Local7)
- }
-
- /*----------------------------------------------------------------------------------------*/
+Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
+/*----------------------------------------------------------------------------------------*/
/**
* Get actual negotiated/PHY or core link width
*
* Retval - Link Width
*/
Method (procPcieGetLinkWidth, 2, NotSerialized) {
- if (LEqual (Arg0, 0)){
- //Get negotiated length
+ Store ("PcieGetLinkWidth Enter", Debug)
+ Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+ Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+
+ if (LEqual (Arg1, DEF_LINKWIDTH_ACTIVE)){
+ //Get negotiated length
And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0)
- Store (DeRefOf (Index (Buffer (){0, 1, 2, 4, 8, 12, 16}, Local0)), Local1)
+ Store (DeRefOf (Index (varLinkWidthBuffer, Local0)), Local1)
+ Store (Concatenate (" Active Link Width :", ToHexString (Local1), varStringBuffer), Debug)
} else {
//Get phy length
Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
+ Store (DerefOf (Index (Local7, DEF_OFFSET_START_PHY_LANE)), varStartPhyLane)
+ Store (DerefOf (Index (Local7, DEF_OFFSET_END_PHY_LANE)), varEndPhyLane)
if (LGreater (varStartPhyLane, varEndPhyLane)) {
Subtract (varStartPhyLane, varEndPhyLane, Local1)
} else {
Subtract (varEndPhyLane, varStartPhyLane, Local1)
}
- Increment (Local1)
+ Increment (Local1)
+ Store (Concatenate (" PHY Link Width :", ToHexString (Local1), varStringBuffer), Debug)
}
- //Store (Concatenate ("Link Width :", ToHexString (Local7)), Debug)
+ Store ("PcieGetLinkWidth Exit", Debug)
return (Local1)
}
* Arg0 - Port Index
* Arg1 - Start Lane
* Arg2 - End Lane
- * Arg3 - Enable(0) / Disable(1)
+ * Arg3 - Enable(0) / Disable(1)
*/
- Method (procPcieLaneEnableControl, 4, NotSerialized) {
+ Method (procPcieLaneEnableControl, 4, Serialized) {
Store ("PcieLaneEnableControl Enter", Debug)
- Name (varStartCoreLane, 0)
- Name (varEndCoreLane, 0)
+ Store (Concatenate (" Arg0 : ", ToHexString (Arg0), varStringBuffer), Debug)
+ Store (Concatenate (" Arg1 : ", ToHexString (Arg1), varStringBuffer), Debug)
+ Store (Concatenate (" Arg2 : ", ToHexString (Arg2), varStringBuffer), Debug)
+ Store (Concatenate (" Arg3 : ", ToHexString (Arg3), varStringBuffer), Debug)
Store (procPcieGetPortInfo (Arg0), Local7)
Store (Arg1, varStartCoreLane)
Store (Arg2, varEndCoreLane)
- CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId)
+ Store (
+ Or (ShiftLeft (DerefOf (Index (Local7, Add (DEF_OFFSET_WRAPPER_ID, 1))), 8), DerefOf (Index (Local7, DEF_OFFSET_WRAPPER_ID))),
+ varWrapperId
+ )
if (LGreater (varStartCoreLane, varEndCoreLane)) {
Subtract (varStartCoreLane, varEndCoreLane, Local1)
Store (varEndCoreLane, Local2)
Subtract (varEndCoreLane, varStartCoreLane, Local1)
Store (varStartCoreLane, Local2)
}
- ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, Local1)
- //Store (Concatenate ("Lane Bitmap :", ToHexString (Local1)), Debug)
- if (Lequal (Arg3, 0)) {
- procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), 0xffffffff, Local1);
- } else {
- procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), Not (Local1), 0x0);
+ ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, varLaneBitmapOrMaskLocal3)
+ Store (Not (varLaneBitmapOrMaskLocal3), varLaneBitmapAndMaskLocal4)
+ Store (Concatenate ("Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug)
+ if (Lequal (Arg3, 1)) {
+ Store (0, varLaneBitmapOrMaskLocal3)
}
+ procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3);
Stall (10)
Store ("PcieLaneEnableControl Exit", Debug)
}
*
*/
/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of Advanced Micro Devices, Inc. nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+****************************************************************************
+*
+*/
/*----------------------------------------------------------------------------------------*/
/**
/*----------------------------------------------------------------------------------------*/
/**
- * Max Port GEN capability
+ * Max Port link speed
*
*/
- Name (
- AD06,
- Package () {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- }
- )
+ Name (AD06, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+ Alias (AD06, varMaxLinkSpeed)
- Alias (
- AD06,
- varPsppMaxPortCapabilityArray
- )
+
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Max link speed that was changed during runtime (hotplug for instance)
+ *
+ */
+
+ Name (AD08, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+ Alias (AD08, varOverrideLinkSpeed)
/*----------------------------------------------------------------------------------------*/
/**
* 1 (Started)
*/
- Name (
- varPsppPolicyService,
- 0x0
- )
+ Name (varPsppPolicyService, 0x0 )
/*----------------------------------------------------------------------------------------*/
/**
* 1 (DC)
*/
- Name (
- varPsppAcDcState,
- 0x0
- )
+ Name (varPsppAcDcState, 0x0)
+ Name (varPsppAcDcOverride, 0x1)
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Client ID array
+ *
+ */
- Name (
- varPsppClientIdArray,
- Package () {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000
- }
- )
+ Name (varPsppClientIdArray,
+ Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+ )
- Name (
- varPsppClientCapabilityArray,
- Package () {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- }
- )
+ Name (varDefaultPsppClientIdArray,
+ Package () {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
+ )
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * LInk speed requested by device driver
+ *
+ */
+ Name (varRequestedLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Current link speed
+ *
+ */
+ Name (AD09, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+ Alias (AD09, varCurrentLinkSpeed)
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Template link speed
+ *
+ */
Name (
- varPsppCurrentCapabilityArray,
- Package () {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- }
- )
- Name (
- varDefaultGen1CapabilityArray,
+ varGen1LinkSpeedTemplate,
Package () {
- 0x2,
- 0x2,
- 0x2,
- 0x2,
- 0x2,
- 0x2,
- 0x2
- }
- )
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1,
+ DEF_LINK_SPEED_GEN1
+ })
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Template link speed
+ *
+ */
+ Name (varLowVoltageRequest, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 })
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Global varuable
+ *
+ */
+ Name (varPortIndex, 0)
/*----------------------------------------------------------------------------------------*/
/**
* Report AC/DC state
*/
Method (procPsppReportAcDsState, 1, Serialized) {
Store ("PsppReportAcDsState Enter", Debug)
- CreateByteField (Arg0, 0x2, varArgAcDcState)
- Store ("AC/DC state = ", Debug)
- Store (varArgAcDcState, Debug)
- if (LEqual (varArgAcDcState, varPsppAcDcState)) {
+ Store (DeRefOf (Index (Arg0, 0x2)), varArgAcDcStateLocal1)
+ Store (Concatenate (" AC/DC state: ", ToHexString (varArgAcDcStateLocal1), varStringBuffer), Debug)
+
+ Store (procPsppGetAcDcState(), varCurrentAcDcStateLocal0)
+ Store (varArgAcDcStateLocal1, varPsppAcDcState)
+
+ Or (ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (1, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local2)
+ Or (ShiftLeft (varPsppAcDcState, DEF_SCARTCH_PSPP_ACDC_OFFSET), ShiftLeft (varPsppAcDcOverride, DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET), Local3)
+ procIndirectRegisterRMW (0x0, 0x60, 0xF4, Not (Local2), And (Local2, Local3))
+
+
+ if (LEqual (varArgAcDcStateLocal1, varCurrentAcDcStateLocal0)) {
Store (" No action. [AC/DC state not changed]", Debug)
Store ("PsppReportAcDsState Exit", Debug)
return (0)
}
- Store (varArgAcDcState, varPsppAcDcState)
+
+ // Disable both APM (boost) and PDM flow on DC event enable it on AC.
+ procApmPdmActivate(varPsppAcDcState)
+
// Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service.
if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
- procNbLclkDpmActivate(1, varPsppAcDcState)
+ procNbLclkDpmActivate(1, procPsppGetAcDcState())
}
if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
Store (" No action. [Policy type]", Debug)
*
* Arg0 - Data Buffer
*/
- Method (procPsppPerformanceRequest, 1) {
- Store ("PsppPerformanceRequest Enter", Debug)
+ Method (procPsppPerformanceRequest, 1, NotSerialized) {
+ Store (procPsppProcessPerformanceRequest (Arg0), Local7)
+ Store (DeRefOf (Index (Local7, 2)), varReturnStatusLocal0)
+ if (LNotEqual (varReturnStatusLocal0, 2)) {
+ return (Local7)
+ }
+ procApplyPsppState ()
+ return (Local7)
+ }
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * PCIe Performance Request
+ *
+ * Arg0 - Data Buffer
+ */
+ Method (procPsppProcessPerformanceRequest, 1, NotSerialized) {
+ Store ("PsppProcessPerformanceRequest Enter", Debug)
Name (varClientBus, 0)
- Name (varPortIndex, 0)
- Store (Buffer (256) {}, Local7)
+ Store (0, varPortIndex)
+ Store (Buffer (10) {}, Local7)
CreateWordField (Local7, 0x0, varReturnBufferLength)
Store (3, varReturnBufferLength)
CreateByteField (Local7, 0x2, varReturnStatus)
Store (1, varReturnStatus)
+
if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
Store (" No action. [Policy type]", Debug)
Store ("PsppPerformanceRequest Exit", Debug)
CreateByteField (Arg0, 0x8, varRequestType)
CreateByteField (Arg0, 0x9, varRequestData)
- Store (" Client ID:", Debug)
- Store (varClientId, Debug)
- Store (" Valid Flags:", Debug)
- Store (varValidFlag, Debug)
- Store (" Flags:", Debug)
- Store (varFlag, Debug)
- Store (" Request Type:", Debug)
- Store (varRequestType, Debug)
- Store (" Request Data:", Debug)
- Store (varRequestData, Debug)
+ Store (Concatenate (" Client ID : ", ToHexString (varClientId), varStringBuffer), Debug)
+ Store (Concatenate (" Valid Flags : ", ToHexString (varValidFlag), varStringBuffer), Debug)
+ Store (Concatenate (" Flags : ", ToHexString (varFlag), varStringBuffer), Debug)
+ Store (Concatenate (" Request Type: ", ToHexString (varRequestType), varStringBuffer), Debug)
+ Store (Concatenate (" Request Data: ", ToHexString (varRequestData), varStringBuffer), Debug)
+
And (ShiftRight (varClientId, 8), 0xff, varClientBus)
- While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
- if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) {
- Increment (varPortIndex)
- Continue
- }
- Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
- And (ShiftRight (Local1, 16), 0xff, Local2) //Local2 Port Subordinate Bus number
- And (ShiftRight (Local1, 8), 0xff, Local1) //Local1 Port Secondary Bus number
- if (LAnd (LLess (varClientBus, Local1), LGreater (varClientBus, Local2))) {
- Increment (varPortIndex)
- Continue
- }
- Store ("Performance request for port index", Debug)
- Store (varPortIndex, Debug)
-
- if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) {
- Store (varClientId, Index (varPsppClientIdArray, varPortIndex))
- } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) {
- // We already have registered client
- Store (" No action. [Unsupported request]", Debug)
- Store ("PsppPerformanceRequest Exit", Debug)
- return (Local7)
- }
- if (LEqual (varRequestData, 0)) {
- Store (0x0000, Index (varPsppClientIdArray, varPortIndex))
- } else {
- if (LEqual (And (varValidFlag, varFlag), 0x1)) {
- Store (DerefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), Index (varPsppClientCapabilityArray, varPortIndex))
- } else {
- Store (varRequestData, Index (varPsppClientCapabilityArray, varPortIndex))
+ while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+ if (LEqual (procChecPortAllocated (varPortIndex), DEF_PORT_ALLOCATED)) {
+ Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
+ And (ShiftRight (Local1, 16), 0xff, varSubordinateBusLocal2) //Local2 Port Subordinate Bus number
+ And (ShiftRight (Local1, 8), 0xff, varSecondaryBusLocal1) //Local1 Port Secondary Bus number
+ if (LAnd (LGreaterEqual (varClientBus, Local1), LLessEqual(varClientBus, Local2))) {
+ break
}
}
- procApplyPsppState ()
- Store (2, varReturnStatus)
+ Increment (varPortIndex)
+ }
+ if (LGreater (varPortIndex, varMaxPortIndexNumber)) {
+ Store ("PsppPerformanceRequest Exit", Debug)
+ return (Local7)
+ }
+
+ Store (Concatenate (" Performance request for port index : ", ToHexString (varPortIndex), Local6), Debug)
+
+ if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) {
+ Store (varClientId, Index (varPsppClientIdArray, varPortIndex))
+ } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) {
+ // We already have registered client
+ Store (" No action. [Unsupported request]", Debug)
Store ("PsppPerformanceRequest Exit", Debug)
return (Local7)
}
- Store ("PsppPerformanceRequest Exit", Debug)
+ Store (0, Index (varLowVoltageRequest, varPortIndex))
+ if (LEqual (varRequestData, 0)) {
+ Store (0x0000, Index (varPsppClientIdArray, varPortIndex))
+ }
+ if (LEqual (varRequestData, 1)) {
+ Store (1, Index (varLowVoltageRequest, varPortIndex))
+ }
+ if (LEqual (varRequestData, 2)) {
+ Store (DEF_LINK_SPEED_GEN1, Index (varRequestedLinkSpeed, varPortIndex))
+ }
+ if (LEqual (varRequestData, 3)) {
+ Store (DEF_LINK_SPEED_GEN2, Index (varRequestedLinkSpeed, varPortIndex))
+ }
+ if (LEqual (And (varValidFlag, varFlag), 0x1)) {
+ Store (DerefOf (Index (varMaxLinkSpeed, varPortIndex)), Index (varRequestedLinkSpeed, varPortIndex))
+ }
+ Store (2, varReturnStatus)
+ Store ("PsppProcessPerformanceRequest Exit", Debug)
return (Local7)
}
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * PSPP Start/Stop Management Request
+ *
+ * Arg0 - Data Buffer
+ */
+
+ Method (procChecPortAllocated, 1, Serialized) {
+ if (LEqual (DeRefOf (Index (varMaxLinkSpeed, Arg0)), 0)) {
+ return (DEF_PORT_NOT_ALLOCATED)
+ }
+ return (DEF_PORT_ALLOCATED)
+ }
+
/*----------------------------------------------------------------------------------------*/
/**
* PSPP Start/Stop Management Request
Method (procPsppControl, 1, Serialized) {
Store ("PsppControl Enter", Debug)
Store (Buffer (256) {}, Local7)
- CreateWordField (Local7, 0x0, varReturnBufferLength)
- Store (3, varReturnBufferLength)
- CreateByteField (Local7, 0x2, varReturnStatus)
- CreateByteField (Arg0, 0x2, varArgPsppRequest)
- Store (varArgPsppRequest, varPsppPolicyService)
+ Store (3, Index (Local7, 0x0)) // Return Buffer Length
+ Store (0, Index (Local7, 0x1)) // Return Buffer Length
+ Store (0, Index (Local7, 0x2)) // Return Status
+
+ Store (DerefOf (Index (Arg0, 0x2)), varPsppPolicyService)
+
+ Store (procIndirectRegisterRead (0x0, 0x60, 0xF4), varPsppScratchLocal0)
+
+ if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_START)) {
+ if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_START)) {
+ // Policy already started
+ Store (" No action. [Policy already started]", Debug)
+ Store ("PsppControl Exit", Debug)
+ return (Local7)
+ }
+ Or (varPsppScratchLocal0, DEF_PSPP_POLICY_START, varPsppScratchLocal0)
+ }
+ if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
+ if (LEqual (And (varPsppScratchLocal0, 1), DEF_PSPP_POLICY_STOP)) {
+ // Policy already stopped
+ Store (" No action. [Policy already stopped]", Debug)
+ Store ("PsppControl Exit", Debug)
+ return (Local7)
+ }
+ And (varPsppScratchLocal0, Not (DEF_PSPP_POLICY_START), varPsppScratchLocal0)
+ }
+ Or (varPsppScratchLocal0, Shiftleft (varPsppPolicy, DEF_SCARTCH_PSPP_POLICY_OFFSET), varPsppScratchLocal0)
+ procIndirectRegisterWrite (0x0, 0x60, 0xF4, varPsppScratchLocal0)
+
+ procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray))
+
+ // Reevaluate APM/PDM state here on S3 resume while staying on DC.
+ procApmPdmActivate(varPsppAcDcState)
+
// Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service.
if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
- procNbLclkDpmActivate(1, varPsppAcDcState)
+ procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1, procPsppGetAcDcState())
}
//Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage
if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
// Load default speed capability state
if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) {
- procCopyPackage (RefOf (varPsppMaxPortCapabilityArray), RefOf (varPsppCurrentCapabilityArray))
+ procCopyPackage (RefOf (varMaxLinkSpeed), RefOf (varCurrentLinkSpeed))
+ Store (0, varPortIndex)
+ while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+ if (LNotEqual (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), 0)) {
+ Store (DeRefOf (Index (varOverrideLinkSpeed, varPortIndex)), Index (varCurrentLinkSpeed, varPortIndex))
+ }
+ Increment (varPortIndex)
+ }
} else {
- procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPsppCurrentCapabilityArray))
- }
- // Unregister all clients
- if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
- Name (varDefaultPsppClientIdArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
- procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray))
+ procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varCurrentLinkSpeed))
}
procApplyPsppState ()
}
- Store (3, varReturnBufferLength)
- Store (0, varReturnStatus)
Store ("PsppControl Exit", Debug)
return (Local7)
}
+ Name (varNewLinkSpeed, Package () {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00})
+
/*----------------------------------------------------------------------------------------*/
/**
* Evaluate PCIe speed on all links according to PSPP state and client requests
*/
Method (procApplyPsppState, 0, Serialized) {
Store ("ApplyPsppState Enter", Debug)
- Name (varPortIndex, 0)
- Name (varLowPowerMode, 0)
- Name (varPcieCapabilityArray, Package () {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02})
-
Store (0, varPortIndex)
- While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
- if (LNotEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) {
- Store (procGetPortRequestedCapability (varPortIndex), Index (varPcieCapabilityArray, varPortIndex))
+
+ procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed))
+ while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+ if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_ALLOCATED)) {
+ Store (procGetPortRequestedCapability (varPortIndex), Index (varNewLinkSpeed, varPortIndex))
}
Increment (varPortIndex)
}
- if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x01, MTR, 0, 0), ONES)) {
- procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPcieCapabilityArray))
+ if (LNotEqual(Match (varLowVoltageRequest, MEQ, 0x01, MTR, 0, 0), ONES)) {
+ procCopyPackage (RefOf (varGen1LinkSpeedTemplate), RefOf (varNewLinkSpeed))
}
- if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) {
+ if (LNotEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) {
// Set GEN2 voltage
Store ("Set GEN2 VID", Debug)
procPcieSetVoltage (varGen2Vid, 1)
- procPcieAdjustPll (2)
- procNbLclkDpmActivate(2, varPsppAcDcState)
+ procPcieAdjustPll (DEF_LINK_SPEED_GEN2)
+ procNbLclkDpmActivate(DEF_LINK_SPEED_GEN2, procPsppGetAcDcState())
}
Store (0, varPortIndex)
- While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
- if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) {
+ while (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
+ if (LEqual (procChecPortAllocated(varPortIndex), DEF_PORT_NOT_ALLOCATED)) {
Increment (varPortIndex)
- Continue
+ continue
}
- Store (procGetPortCurrentCapability (varPortIndex), Local0)
- Store (DerefOf (Index (varPcieCapabilityArray, varPortIndex)), Local2)
- if (LEqual (Local0, Local2)) {
+ Store (DerefOf (Index (varCurrentLinkSpeed, varPortIndex)), varCurrentLinkSpeedLocal0)
+ Store (DerefOf (Index (varNewLinkSpeed, varPortIndex)), varNewLinkSpeedLocal2)
+ if (LEqual (varCurrentLinkSpeedLocal0, varNewLinkSpeedLocal2)) {
Increment (varPortIndex)
- Continue
+ continue
}
- procSetPortCapabilityAndSpeed (varPortIndex, Local2, 0)
+ Store (varNewLinkSpeedLocal2, Index (varCurrentLinkSpeed, varPortIndex))
+ procSetPortCapabilityAndSpeed (varPortIndex, varNewLinkSpeedLocal2)
Increment (varPortIndex)
}
- if (LEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) {
+ if (LEqual(Match (varNewLinkSpeed, MEQ, DEF_LINK_SPEED_GEN2, MTR, 0, 0), ONES)) {
// Set GEN1 voltage
Store ("Set GEN1 VID", Debug)
- procNbLclkDpmActivate(1, varPsppAcDcState)
- procPcieAdjustPll (1)
+ procNbLclkDpmActivate(DEF_LINK_SPEED_GEN1, procPsppGetAcDcState())
+ procPcieAdjustPll (DEF_LINK_SPEED_GEN1)
procPcieSetVoltage (varGen1Vid, 0)
}
Store ("ApplyPsppState Exit", Debug)
*
*/
Method (procGetPortRequestedCapability, 1) {
- Store (0x3, Local0)
+ Store (DEF_LINK_SPEED_GEN2, Local0)
if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
- if (LOr (LEqual (varPsppAcDcState, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
+ if (LOr (LEqual (procPsppGetAcDcState(), DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
// Default policy cap to GEN1
- Store (0x2, Local0)
+ Store (DEF_LINK_SPEED_GEN1, Local0)
+ }
+ if (LNotEqual (DerefOf (Index (varOverrideLinkSpeed, Arg0)), 0)) {
+ Store (DerefOf (Index (varOverrideLinkSpeed, Arg0)), Local0)
}
} else {
- Store (DerefOf (Index (varPsppClientCapabilityArray, Arg0)), Local0)
+ Store (DerefOf (Index (varRequestedLinkSpeed, Arg0)), Local0)
}
return (Local0)
}
/*----------------------------------------------------------------------------------------*/
/**
- * Read PCI config register
+ * Set capability and speed
*
* Arg0 - Port Index
- *
+ * Arg1 - Link speed
*/
- Method (procGetPortCurrentCapability, 1) {
- return (DerefOf (Index (varPsppCurrentCapabilityArray, Arg0)))
+ Method (procSetPortCapabilityAndSpeed, 2, NotSerialized) {
+ Store ("SetPortCapabilityAndSpeed Enter", Debug)
+ Store (Concatenate (" Port Index : ", ToHexString (Arg0), varStringBuffer), Debug)
+ Store (Concatenate (" Speed : ", ToHexString (Arg1), varStringBuffer), Debug)
+
+ //UnHide UMI port
+ if (LEqual (Arg0, 6)) {
+ procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40);
+ }
+
+ procPcieSetLinkSpeed (Arg0, Arg1)
+
+ // Programming for LcInitSpdChgWithCsrEn
+ if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
+ // Registered port, LcInitSpdChgWithCsrEn = 0.
+ procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0)
+ } else {
+ procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000)
+ }
+
+ // Determine port PCI address and check port present
+ Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+ And (procPciDwordRead (varPortBdfLocal1, 0x70), 0x400000, varPortPresentLocal3)
+ if (LNotEqual (varPortPresentLocal3, 0)) {
+ procDisableAndSaveAspm (Arg0)
+ Store (1, Local2)
+ while (Local2) {
+ //retrain port
+ procPciDwordRMW (varPortBdfLocal1, 0x68, Not (0x00000000), 0x20)
+ Sleep (30)
+ while (And (procPciDwordRead (varPortBdfLocal1, 0x68), 0x08000000)) {
+ Sleep (10)
+ }
+ Store (0, Local2)
+ if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) {
+ Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRateLocal4)
+ if (LNotEqual (And (varLcCurrentDataRateLocal4, 0x800), 0)) {
+ Store (1, Local2)
+ }
+ }
+ }
+ procRestoreAspm (Arg0)
+ } else {
+ Store (" Device not present. Set capability and speed only", Debug)
+ }
+ //Hide UMI port
+ if (LEqual (Arg0, 6)) {
+ procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00);
+ }
+ Store ("SetPortCapabilityAndSpeed Exit", Debug)
}
+ Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
+ Name (varPcieLinkControlOffset, 0)
+ Name (varPcieLinkControlData, 0)
+
/*----------------------------------------------------------------------------------------*/
/**
- * Set capability and speed
+ * Disable and save ASPM state
*
* Arg0 - Port Index
- * Arg1 - Capability
- * Arg2 - Speed
*/
- Method (procSetPortCapabilityAndSpeed, 3) {
- Store ("SetPortCapabilityAndSpeed Enter", Debug)
- if (LOr (LEqual (Arg1, 0x2), LEqual (Arg1, 0x3))) {
- Store ("Port Index = ", Debug)
- Store (Arg0, Debug)
- Store ("Cap = ", Debug)
- Store (Arg1, Debug)
- Store ("Speed = ", Debug)
- Store (Arg2, Debug)
-
- Name (varDxF0xE4_xA4, 0x20000001)
- Name (varPortPresent, 0x00000000)
- Name (varDxF0x88, 0x00000002)
- Name (varAXCFGx68_PmCtrl, 0x00000000)
- Name (varLcCurrentDataRate,0x00000000)
- Name (varSecondaryBus, 0x00000000)
- Name (varHeaderType, 0x00000000)
- Name (varMultiFunction, 0x00000000)
- Name (varPcieLinkControlOffset, 0x00000000)
- Name (varPcieLinkControlData, 0x00000000)
- Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
-
-
- //If request for UMI unhihe port congig space
- if (LEqual (Arg0, 6)) {
- procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40);
+ Method (procDisableAndSaveAspm, 1, Serialized) {
+ Store (0, varPcieLinkControlOffset)
+ Store (0, varPcieLinkControlData)
+
+ Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+ if (LEqual (Arg0, 6)) {
+ Store (" Disable SB ASPM", Debug)
+ Store (procPcieSbAspmControl (0, 0), Index (varPcieLinkControlArray, 0))
+ Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug)
+ procPcieSbAspmControl (0, 1)
+ return (0)
+ }
- }
- Store (Arg1, Index (varPsppCurrentCapabilityArray, Arg0))
- if (LEqual (Arg1, 0x2)) {
- //Gen1
- Store (0x00000000, varDxF0xE4_xA4)
- Store (0x21, varDxF0x88)
- }
+ Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3)
+ Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3)
- // Programming for LcInitSpdChgWithCsrEn
- if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
- // Registered port, LcInitSpdChgWithCsrEn = 0.
- procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0)
- } else {
- procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000)
+ Store (Concatenate (" Disable EP ASPM on Secondary Bus : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+ Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2)
+ Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3)
+ Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3)
+
+ Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+ if (LNotEqual (And (varTempLocal3, 0x80), 0)) {
+ Store (0x7, varMaxFunctionLocal0)
+ } else {
+ Store (0x0, varMaxFunctionLocal0)
+ }
+ Store (0, varFunctionLocal4)
+ while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) {
+ //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+ Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset)
+ if (LEqual (varPcieLinkControlOffset, 0)) {
+ Increment (varFunctionLocal4)
+ continue
}
+ Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
- // Initialize port
- procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), varDxF0xE4_xA4)
- //set target link speed
- Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
- procPciDwordRMW (Local0, 0x88, Not (0x0000002f), varDxF0x88)
-
- // Determine port PCI address and check port present
- Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
- And (procPciDwordRead (Local0, 0x70), 0x400000, varPortPresent)
- if (LNotEqual (varPortPresent, 0)) {
- //Disable ASPM on EP
- if (LNotEqual (Arg0, 6)) {
- Store (procPciDwordRead (Local0, 0x18), Local3)
- Store (And (ShiftRight (Local3, 8), 0xFF), varSecondaryBus)
- Store ("Disable EP ASPM on SecondaryBus = ", Debug)
- Store (varSecondaryBus, Debug)
- Store (ShiftLeft (varSecondaryBus, 8), Local3)
- Store (procPciDwordRead (Local3, 0xC), Local3)
- Store (And (ShiftRight (Local3, 16), 0xFF), varHeaderType)
- Store ("Header Type = ", Debug)
- Store (varHeaderType, Debug)
-
- if (LNotEqual (And (varHeaderType, 0x80), 0)) {
- Store (0x7, varMultiFunction)
- }
-
- Store (ShiftLeft (varSecondaryBus, 8), Local3)
- Store (0, Local2)
- while (LLessEqual (Local2, varMultiFunction)) {
-
- //Find PcieLinkControl register offset = PcieCapPtr + 0x10
- Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset)
- if (LNotEqual (varPcieLinkControlOffset, 0)) {
- Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
-
- Store ("Function number of SecondaryBus = ", Debug)
- Store (Local2, Debug)
- Store ("Find PcieLinkControl register offset = ", Debug)
- Store (varPcieLinkControlOffset, Debug)
- // Save ASPM on EP
- Store (procPciDwordRead (Local3, varPcieLinkControlOffset), varPcieLinkControlData)
- Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, Local2))
- Store ("PcieLinkControlData = ", Debug)
- Store (varPcieLinkControlData, Debug)
- Store ("Save ASPM = ", Debug)
- Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug)
- // Disable ASPM
- if (LNotEqual (And (varPcieLinkControlData, 0x3), 0x0)) {
- procPciDwordRMW (Local3, varPcieLinkControlOffset, Not (0x00000003), 0x00)
- Store ("Disable ASPM on EP Complete!!", Debug)
- }
- }
- Increment (Local2)
- Increment (Local3)
- }
+ Store (Concatenate (" Function number of Secondary Bus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug)
+ Store (Concatenate (" PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug)
+ // Save ASPM on EP
+ Store (procPciDwordRead (Add (varEndpointBdfLocal2, varFunctionLocal4) , varPcieLinkControlOffset), varPcieLinkControlData)
+ Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, varFunctionLocal4))
- } else {
+ Store (Concatenate (" PcieLinkControl Data : ", ToHexString (varPcieLinkControlData), varStringBuffer), Debug)
- Store (procPcieSbAspmControl (0, 0), varAXCFGx68_PmCtrl)
- And (varAXCFGx68_PmCtrl, 0x3, Local1)
- if (LNotEqual (Local1, 0x0)) {
- procPcieSbAspmControl (0, 1)
- }
- }
- Store (1, Local2)
- while (Local2) {
- //retrain port
- procPciDwordRMW (Local0, 0x68, Not (0x00000000), 0x20)
- Sleep (30)
- while (And (procPciDwordRead (Local0, 0x68), 0x08000000)) {Sleep (10)}
- Store (0, Local2)
- if (LEqual (Arg1, 0x2)) { // if Gen1
- Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRate)
- if (LNotEqual (And (varLcCurrentDataRate, 0x800), 0)) {
- Store (1, Local2)
- }
- }
- }
- //restore ASPM setting
- if (LNotEqual (Arg0, 6)) {
- // Restore EP
- //if (LNotEqual (varPcieLinkControlOffset, 0)) {
- // procPciDwordWrite (Local3, varPcieLinkControlOffset, varPcieLinkControlData)
- //}
- Store (ShiftLeft (varSecondaryBus, 8), Local3)
- Store (0, Local2)
- while (LLessEqual (Local2, varMultiFunction)) {
-
- //Find PcieLinkControl register offset = PcieCapPtr + 0x10
- Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset)
- if (LNotEqual (varPcieLinkControlOffset, 0)) {
- Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
-
- Store ("Restore Function number of SecondaryBus = ", Debug)
- Store (Local2, Debug)
- Store ("Restore Find PcieLinkControl register offset = ", Debug)
- Store (varPcieLinkControlOffset, Debug)
- Store ("Restore ASPM = ", Debug)
- Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug)
- procPciDwordWrite (Local3, varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, Local2)))
- }
- Increment (Local2)
- Increment (Local3)
- }
+ procPciDwordRMW (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, Not (0x00000003), 0x00)
+ Store ("Disable ASPM on EP Complete!!", Debug)
+ Increment (varFunctionLocal4)
+ }
+ }
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Restore ASPM
+ *
+ * Arg0 - Port Index
+ */
+ Method (procRestoreAspm, 1, Serialized) {
- } else {
- // Restore SB
- procPcieSbAspmControl (varAXCFGx68_PmCtrl, 1)
- }
- } else {
- Store (" Device not present. Set capability and speed only", Debug)
- }
- //If request for UMI hide port congig space
- if (LEqual (Arg0, 6)) {
- procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00);
+ Store (0, varPcieLinkControlOffset)
+ Store (0, varPcieLinkControlData)
+
+
+ // Restore SB ASPM
+ if (LEqual (Arg0, 6)) {
+ Store (" Restore SB ASPM", Debug)
+ Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf(Index (varPcieLinkControlArray, 0))), varStringBuffer), Debug)
+ procPcieSbAspmControl (DerefOf(Index (varPcieLinkControlArray, 0)), 1)
+ return (0)
+ }
+ Store (ShiftLeft (Add( Arg0, 2), 3), varPortBdfLocal1)
+ // Restore EP ASPM
+ Store (procPciDwordRead (varPortBdfLocal1, 0x18), varTempLocal3)
+ Store (And (ShiftRight (varTempLocal3, 8), 0xFF), varTempLocal3)
+
+ Store (Concatenate (" Disable EP ASPM on SecondaryBus : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+ Store (ShiftLeft (varTempLocal3, 8), varEndpointBdfLocal2)
+ Store (procPciDwordRead (varEndpointBdfLocal2, 0xC), varTempLocal3)
+ Store (And (ShiftRight (varTempLocal3, 16), 0xFF), varTempLocal3)
+
+ Store (Concatenate (" EP Header type : ", ToHexString (varTempLocal3), varStringBuffer), Debug)
+
+ if (LNotEqual (And (varTempLocal3, 0x80), 0)) {
+ Store (0x7, varMaxFunctionLocal0)
+ } else {
+ Store (0x0, varMaxFunctionLocal0)
+ }
+ Store (0, varFunctionLocal4)
+ while (LLessEqual (varFunctionLocal4, varMaxFunctionLocal0)) {
+ //Find PcieLinkControl register offset = PcieCapPtr + 0x10
+ Store (procFindPciCapability (Add (varEndpointBdfLocal2, varFunctionLocal4), 0x10), varPcieLinkControlOffset)
+ if (LEqual (varPcieLinkControlOffset, 0)) {
+ Increment (varFunctionLocal4)
+ continue
}
+ Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
+
+ Store (Concatenate (" Restore Function number of SecondaryBus : ", ToHexString (varFunctionLocal4), varStringBuffer), Debug)
+ Store (Concatenate (" Restore PcieLinkControl register offset : ", ToHexString (varPcieLinkControlOffset), varStringBuffer), Debug)
+ Store (Concatenate (" PcieLinkControl Data : ", ToHexString (DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4))), varStringBuffer), Debug)
+
+ procPciDwordWrite (Add (varEndpointBdfLocal2, varFunctionLocal4), varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, varFunctionLocal4)))
+ Increment (varFunctionLocal4)
+ }
+ }
+
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Request VID
+ *
+ * Arg0 - Port Index
+ * Arg1 - PCIe speed
+ */
+
+ Method (procPcieSetLinkSpeed, 2) {
+ Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
+ if (LEqual (Arg1, DEF_LINK_SPEED_GEN1)) {
+ procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x21)
+ procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x0)
+ } else {
+ procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), 0x20000001)
+ procPciDwordRMW (Local0, 0x88, Not (0x0000002f), 0x2)
}
- Store ("SetPortCapabilityAndSpeed Exit", Debug)
}
- Mutex (varVoltageChangeMutex, 0)
+
+
/*----------------------------------------------------------------------------------------*/
/**
* Request VID
* Arg1 - 0 = do not wait intil voltage is set
* 1 = wait until voltage is set
*/
- Method (procPcieSetVoltage, 2) {
- Store ("PcieSetVoltage(procPcieSetVoltage) Enter", Debug)
- Acquire(varVoltageChangeMutex, 0xFFFF)
+ Method (procPcieSetVoltage, 2, Serialized) {
+ Store ("PcieSetVoltage Enter", Debug)
Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1)
//Enable voltage change
Or (Local1, 0x2, Local1)
procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
//Clear voltage index
And (Local1, Not (ShiftLeft (0x3, 3)), Local1)
+
+ Store (Concatenate (" Voltage Index:", ToHexString (Arg0), Local6), Debug)
//Set new voltage index
- Store (" Voltage Index:", Debug)
- Store (Arg0, Debug)
Or (Local1, ShiftLeft (Arg0, 3), Local1)
//Togle request
And (Not (Local1), 0x4, Local2)
And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1)
}
}
- Release (varVoltageChangeMutex)
- Store ("PcieSetVoltage(procPcieSetVoltage) Exit", Debug)
+ Store ("PcieSetVoltage Exit", Debug)
}
/*----------------------------------------------------------------------------------------*/
}
}
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * Read PCIe port indirect register
+ *
+ * Arg0 - Ref Source Pckage
+ * Arg1 - Ref to Destination Package
+ *
+ */
+ Method (procPsppGetAcDcState, 0 , NotSerialized) {
+ Return (And (varPsppAcDcState, varPsppAcDcOverride))
+ }
#include "Ids.h"
#include "amdlib.h"
#include "heapManager.h"
+#include "OptionGnb.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "GnbPcieFamServices.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
+#include "PcieConfigData.h"
#include "PcieMapTopology.h"
#include "PcieInputParser.h"
#include "Filecode.h"
#define REBASE_PTR( Ptr, OldBase, NewBase) *(UINTN *)Ptr = (*(UINTN *)Ptr + (UINTN) NewBase - (UINTN) OldBase);
extern BUILD_OPT_CFG UserOptions;
+extern GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
return AGESA_FATAL;
}
LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
- Pcie->StdHeader = (PVOID) StdHeader;
+ Pcie->StdHeader = StdHeader;
Pcie->This = (UINTN) (Pcie);
Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
ComplexIndex = 0;
IDS_ERROR_TRAP;
return AGESA_FATAL;
}
- Pcie->ComplexList[ComplexIndex].SiliconList = (PPCIe_SILICON_CONFIG) Buffer;
+ Pcie->ComplexList[ComplexIndex].SiliconList = (PCIe_SILICON_CONFIG *) &Buffer;
PcieFmBuildComplexConfiguration (Buffer, StdHeader);
for (Index = 0; Index < NumberOfComplexes; Index++) {
ComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexList, Index);
}
}
Pcie->ComplexList[ComplexIndex - 1].Flags |= DESCRIPTOR_TERMINATE_LIST;
- Pcie->LinkReceiverDetectionPooling = PCIE_LINK_RECEIVER_DETECTION_POOLING;
- Pcie->LinkL0Pooling = PCIE_LINK_L0_POOLING;
- Pcie->LinkGpioResetAssertionTime = PCIE_LINK_GPIO_RESET_ASSERT_TIME;
- Pcie->LinkResetToTrainingTime = PCIE_LINK_RESET_TO_TRAINING_TIME;
+ Pcie->LinkReceiverDetectionPooling = GnbBuildOptions.LinkReceiverDetectionPooling;
+ Pcie->LinkL0Pooling = GnbBuildOptions.LinkL0Pooling;
+ Pcie->LinkGpioResetAssertionTime = GnbBuildOptions.LinkGpioResetAssertionTime;
+ Pcie->LinkResetToTrainingTime = GnbBuildOptions.LinkResetToTrainingTime;
Pcie->GfxCardWorkaround = GfxWorkaroundEnable;
+ Pcie->TrainingExitState = LinkStateTrainingCompleted;
+ Pcie->TrainingAlgorithm = GnbBuildOptions.TrainingAlgorithm;
if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) {
Pcie->GfxCardWorkaround = GfxWorkaroundDisable;
}
}
(*Pcie)->This = (UINTN)(*Pcie);
}
- (*Pcie)->StdHeader = (PVOID) StdHeader;
+ (*Pcie)->StdHeader = StdHeader;
return AGESA_SUCCESS;
}
#ifndef _PCIECONFIGDATA_H_
#define _PCIECONFIGDATA_H_
+AGESA_STATUS
+PcieConfigurationInit (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
AGESA_STATUS
PcieLocateConfigurationData (
UINT32 LaneBitMap;
LaneBitMap = 0;
if (PcieLibIsEngineAllocated (Engine)) {
- LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane);
+ LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieLibGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane);
}
return LaneBitMap;
}
#include "Ids.h"
#include "Gnb.h"
#include "GnbPcie.h"
+#include "PcieInputParser.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+UINTN
+PcieInputParserGetLengthOfPcieEnginesList (
+ IN PCIe_COMPLEX_DESCRIPTOR *Complex
+ );
+UINTN
+PcieInputParserGetLengthOfDdiEnginesList (
+ IN PCIe_COMPLEX_DESCRIPTOR *Complex
+ );
/*----------------------------------------------------------------------------------------*/
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+PcieEnginesToWrapper (
+ IN PCIE_ENGINE_TYPE EngineType,
+ IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
+ IN PCIe_WRAPPER_CONFIG *Wrapper
+ );
AGESA_STATUS
STATIC
IN OUT GNB_PCI_SCAN_DATA *ScanData
);
+VOID
+PcieAspmEnableOnFunction (
+ IN PCI_ADDR Function,
+ IN PCIE_ASPM_TYPE Aspm,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+PcieAspmEnableOnDevice (
+ IN PCI_ADDR Device,
+ IN PCIE_ASPM_TYPE Aspm,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
VOID
PcieAspmEnableOnLink (
IN PCI_ADDR Downstream,
GnbLibPciRMW (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
AccessS3SaveWidth8,
- ~(BIT0 & BIT1),
+ ~(UINT32)(BIT0 & BIT1),
Aspm,
StdHeader
);
0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s),
0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s),
0x168C, 0xFFFF, (UINT16) ~(AspmL0s),
- 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s)
+ 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s),
+ 0x1B4B, 0x9123, (UINT16) ~(AspmL0s)
};
/*----------------------------------------------------------------------------------------*/
D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0;
+ D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
#include "GnbPcie.h"
#include "GnbPcieFamServices.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
+#include "PciePortRegAcc.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE
/*----------------------------------------------------------------------------------------
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
- Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1;
PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie);
PciePortRegisterRMW (
Engine,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
+
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
)
{
UINT8 AlinkPortIndex;
+ if (AlinkPort == NULL) {
+ return AGESA_UNSUPPORTED;
+ }
AlinkPortIndex = 0xE0;
GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader);
GnbLibIoRead (0xCD7, AccessWidth8, AlinkPort, StdHeader);
AlinkPortIndex = 0xE1;
GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader);
GnbLibIoRead (0xCD7, AccessWidth8, (VOID*) ((UINT8*) AlinkPort + 1), StdHeader);
- if (&AlinkPort == 0) {
- return AGESA_UNSUPPORTED;
- }
+// if (&AlinkPort == 0) {
+// return AGESA_UNSUPPORTED;
+// }
return AGESA_SUCCESS;
}
GnbLibPciRMW (
Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
AccessS3SaveWidth8,
- ~(BIT0 | BIT1),
+ ~(UINT32)(BIT0 | BIT1),
Aspm,
StdHeader
);
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
- ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
+ ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
0x0,
GnbLibGetHeader (Pcie)
);
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
- ~BIT6,
+ ~(UINT32)BIT6,
BIT6,
GnbLibGetHeader (Pcie)
);
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
- ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
+ ~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
D0F0x64_x0C.Value,
GnbLibGetHeader (Pcie)
);
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
- ~BIT6,
+ ~(UINT32)BIT6,
0x0,
GnbLibGetHeader (Pcie)
);
}
}
// Clear IRQ register
- procNbSmuIndirectRegisterWrite (0x3, 0, 0)
+ procNbSmuIndirectRegisterWrite (0x3, 0, 1)
Store ("NbSmuServiceRequest Exit", Debug)
}
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+UINT8
+PcieTopologyLocateMuxIndex (
+ IN OUT UINT8 *LaneMuxSelectorArrayPtr,
+ IN UINT8 LaneMuxValue
+ );
/*----------------------------------------------------------------------------------------*/
);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
- CurrentPhyLane = (UINT8) PcieUtilGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
+ CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
D0F0xE4_WRAP_8023.Value,
- FALSE,
+ TRUE,
Pcie
);
}
if ((IncludeLaneType & LANE_TYPE_DDI_LANES) && Engine->EngineData.EngineType == PcieDdiEngine) {
if (PcieLibIsEngineAllocated (Engine)) {
if (IncludeLaneType & (LANE_TYPE_DDI_ALLOCATED | LANE_TYPE_DDI_ALL)) {
- LaneOffset = PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane;
+ LaneOffset = PcieLibGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane;
LaneBitmap |= ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << LaneOffset;
}
if (IncludeLaneType & LANE_TYPE_DDI_ACTIVE) {
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include "PcieWorkarounds.h"
+#include "PcieTraining.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+VOID
+PcieSetResetStateOnEngines (
+ IN PCIe_ENGINE_CONFIG *Engine,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
VOID
-STATIC
-PcieTrainingDebugDumpPortState (
+PcieTrainingCheckResetDuration (
+ IN PCIe_ENGINE_CONFIG *CurrentEngine,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+PcieTrainingDeassertReset (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
);
+VOID
+PcieTrainingBrokenLine (
+ IN PCIe_ENGINE_CONFIG *CurrentEngine,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+PcieTrainingGen2Fail (
+ IN PCIe_ENGINE_CONFIG *CurrentEngine,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+GNB_DEBUG_CODE (
+ VOID
+ STATIC
+ PcieTrainingDebugDumpPortState (
+ IN PCIe_ENGINE_CONFIG *CurrentEngine,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+)
/*----------------------------------------------------------------------------------------*/
/**
GNB_DEBUG_CODE (
PcieTrainingDebugDumpPortState (CurrentEngine, Pcie)
);
+
}
UINT8 LinkTrainingState;
CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie);
if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) {
- CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_GEN2_RECOVERY;
+ CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY;
PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie);
LinkTrainingState = LinkStateResetAssert;
PutEventLog (
{
BOOLEAN *TrainingComplete;
TrainingComplete = (BOOLEAN *) Buffer;
- if (Engine->Type.Port.State != LinkStateTrainingCompleted) {
+ if (Engine->Type.Port.State < Pcie->TrainingExitState) {
*TrainingComplete = FALSE;
+ } else {
+ return;
}
switch (Engine->Type.Port.State) {
case LinkStateResetAssert:
*
*/
+GNB_DEBUG_CODE (
VOID
STATIC
PcieTrainingDebugDumpPortState (
CurrentEngine->Type.Port.TimeStamp
);
}
+)
\ No newline at end of file
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include "GnbRegistersON.h"
+#include "PcieWorkarounds.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE
/*----------------------------------------------------------------------------------------
return GFX_WORKAROUND_SUCCESS;
}
GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader);
- GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~BIT1, BIT1, StdHeader);
+ GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~(UINT32)BIT1, BIT1, StdHeader);
GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader);
GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader);
if (MmioData1 == 0xb700) {
}
}
}
- GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~BIT1, 0x0, StdHeader);
+ GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~(UINT32)BIT1, 0x0, StdHeader);
GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader);
return GFX_WORKAROUND_SUCCESS;
#include "NbSmuLib.h"
#include "NbConfigData.h"
#include "NbFamilyServices.h"
+#include "F14NbPowerGate.h"
#include "GfxLib.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_NB_FAMILY_0x14_F14NBPOWERGATE_FILECODE
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 41363 $ @e \$Date: 2010-11-04 03:24:17 +0800 (Thu, 04 Nov 2010) $
+ * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $
*
*/
/*
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
+#include "NbConfigData.h"
#include "OptionGnb.h"
#include "NbLclkDpm.h"
#include "NbFamilyServices.h"
+#include "NbPowerMgmt.h"
#include "GfxLib.h"
#include "GnbRegistersON.h"
#include "cpuFamilyTranslation.h"
*----------------------------------------------------------------------------------------
*/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB family specific clock gating
+ *
+ *
+ * @param[in, out] NbClkGatingCtrl Pointer to NB_CLK_GATING_CTRL
+ * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
+ */
+VOID
+NbFmNbClockGating (
+ IN OUT VOID *NbClkGatingCtrl,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ NB_CLK_GATING_CTRL *NbClkGatingCtrlPtr;
+ CPU_LOGICAL_ID LogicalId;
+
+ NbClkGatingCtrlPtr = (NB_CLK_GATING_CTRL *)NbClkGatingCtrl;
+ GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+ if ((LogicalId.Revision & AMD_F14_ON_Cx) != 0) {
+ NbClkGatingCtrlPtr->Smu_Sclk_Gating = FALSE;
+ }
+}
/*----------------------------------------------------------------------------------------*/
/**
if (GfxLibIsControllerPresent (StdHeader)) {
//VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0).
for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) {
- if (PpFuseArray->PolicyLabel[SwSatateIndex] == 1) {
+ if (PpFuseArray->PolicyLabel[SwSatateIndex] == POLICY_LABEL_PERFORMANCE) {
break;
}
}
}
// - use fused values for LclkDpmDid[0,1,2] and appropriate voltage
//Keep using actual fusing
- IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actaul fusing.\n");
+ IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actual fusing.\n");
}
+ //Patch SclkThermDid to 175Mhz if not fused
+ if (PpFuseArray->SclkThermDid == 0) {
+ PpFuseArray->SclkThermDid = GfxLibCalculateDid (175 * 100, GfxLibGetMainPllFreq (StdHeader) * 100);
+ }
}
}
};
-
FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = {
{
FCRxFE00_70BC_SclkDpmValid0_OFFSET,
},
};
+FUSE_REGISTER_ENTRY FCRxFE00_70C8_TABLE [] = {
+ {
+ FCRxFE00_70C8_GpuBoostCap_OFFSET,
+ FCRxFE00_70C8_GpuBoostCap_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, GpuBoostCap)
+ },
+ {
+ FCRxFE00_70C8_SclkDpmVid5_OFFSET,
+ FCRxFE00_70C8_SclkDpmVid5_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[5])
+ },
+ {
+ FCRxFE00_70C8_SclkDpmDid5_OFFSET,
+ FCRxFE00_70C8_SclkDpmDid5_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[5])
+ },
+};
+FUSE_REGISTER_ENTRY FCRxFE00_70C9_TABLE [] = {
+ {
+ FCRxFE00_70C9_SclkDpmTdpLimit0_OFFSET,
+ FCRxFE00_70C9_SclkDpmTdpLimit0_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[0])
+ },
+ {
+ FCRxFE00_70C9_SclkDpmTdpLimit1_OFFSET,
+ FCRxFE00_70C9_SclkDpmTdpLimit1_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[1])
+ }
+};
+FUSE_REGISTER_ENTRY FCRxFE00_70CC_TABLE [] = {
+ {
+ FCRxFE00_70CC_SclkDpmTdpLimit2_OFFSET,
+ FCRxFE00_70CC_SclkDpmTdpLimit2_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[2])
+ },
+ {
+ FCRxFE00_70CC_SclkDpmTdpLimit3_OFFSET,
+ FCRxFE00_70CC_SclkDpmTdpLimit3_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[3])
+ }
+};
+
+FUSE_REGISTER_ENTRY FCRxFE00_70CF_TABLE [] = {
+ {
+ FCRxFE00_70CF_SclkDpmTdpLimit4_OFFSET,
+ FCRxFE00_70CF_SclkDpmTdpLimit4_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[4])
+ },
+ {
+ FCRxFE00_70CF_SclkDpmTdpLimit5_OFFSET,
+ FCRxFE00_70CF_SclkDpmTdpLimit5_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimit[5])
+ }
+};
+
+FUSE_REGISTER_ENTRY FCRxFE00_70D2_TABLE [] = {
+ {
+ FCRxFE00_70D2_SclkDpmTdpLimitPG_OFFSET,
+ FCRxFE00_70D2_SclkDpmTdpLimitPG_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmTdpLimitPG)
+ }
+};
+
+FUSE_REGISTER_ENTRY FCRxFE00_70D4_TABLE [] = {
+ {
+ FCRxFE00_70D4_SclkDpmBoostMargin_OFFSET,
+ FCRxFE00_70D4_SclkDpmBoostMargin_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmBoostMargin)
+ }
+};
+
+FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = {
+ {
+ FCRxFE00_70D7_SclkDpmThrottleMargin_OFFSET,
+ FCRxFE00_70D7_SclkDpmThrottleMargin_WIDTH,
+ (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmThrottleMargin)
+ }
+};
FUSE_TABLE_ENTRY FuseRegisterTable [] = {
{
sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
FCRxFE00_70C7_TABLE
},
-
+ {
+ FCRxFE00_70C8_ADDRESS,
+ sizeof (FCRxFE00_70C8_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70C8_TABLE
+ },
+ {
+ FCRxFE00_70C9_ADDRESS,
+ sizeof (FCRxFE00_70C9_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70C9_TABLE
+ },
+ {
+ FCRxFE00_70CC_ADDRESS,
+ sizeof (FCRxFE00_70CC_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70CC_TABLE
+ },
+ {
+ FCRxFE00_70CF_ADDRESS,
+ sizeof (FCRxFE00_70CF_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70CF_TABLE
+ },
+ {
+ FCRxFE00_70D2_ADDRESS,
+ sizeof (FCRxFE00_70D2_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70D2_TABLE
+ },
+ {
+ FCRxFE00_70D4_ADDRESS,
+ sizeof (FCRxFE00_70D4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70D4_TABLE
+ },
+ {
+ FCRxFE00_70D7_ADDRESS,
+ sizeof (FCRxFE00_70D7_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+ FCRxFE00_70D7_TABLE
+ },
};
FUSE_TABLE FuseTable = {
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+F14NbSmuInitFeature (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
/*----------------------------------------------------------------------------------------*/
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 37675 $ @e \$Date: 2010-09-09 22:33:48 +0800 (Thu, 09 Sep 2010) $
+ * @e \$Revision: 51210 $ @e \$Date: 2011-04-20 11:41:43 -0600 (Wed, 20 Apr 2011) $
*
*/
/*
- *****************************************************************************
+ ******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * ***************************************************************************
- *
+ ******************************************************************************
*/
#define _F14NBSMUFIRMWARE_H_
UINT32 DataBlock0[] = {
- 0x00020100,
+ 0x01060100,
+ 0x68d699d6,
0xbdff018e,
- 0x00ce3d9d,
+ 0x00cea2a4,
0x00ce1810,
0xa6082000,
0x00a71800,
0x8c081808,
0xf3251000,
0x270000cc,
- 0xda9dce0b,
+ 0x3fa5ce0b,
0x8308006f,
0xf8260100,
- 0x9dbd248d,
- 0x90fb2040,
- 0xde20900a,
+ 0xa4bd248d,
+ 0x90fb20a5,
+ 0xde24900e,
0x02de3c00,
0x3c04de3c,
0x9f3c06de,
0xfc02ed02,
0x00ed0090,
0x1caa7fce,
- 0x82ce0300,
- 0x3191ccda,
+ 0xce5f0300,
+ 0x00e78485,
+ 0xe78385ce,
+ 0x8585ce00,
+ 0x82ce00e7,
+ 0x6b91ccd6,
+ 0x82ce00ed,
+ 0x8491ccda,
+ 0x82ce00ed,
+ 0x039cccdc,
+ 0x82ce00ed,
+ 0xe19bccde,
+ 0x82ce00ed,
+ 0x6492cce2,
+ 0x82ce00ed,
+ 0x6295cce4,
+ 0x82ce00ed,
+ 0xc3a2cce6,
0x82ce00ed,
- 0x5d91cce2,
+ 0x7696cce8,
0x82ce00ed,
- 0x5b94cce4,
+ 0x6291ccea,
0x82ce00ed,
- 0x699bcce6,
+ 0xce00edec,
+ 0x00edee82,
+ 0xedf082ce,
+ 0xf282ce00,
0x82ce00ed,
- 0x2891cce8,
+ 0xa494ccf4,
0x82ce00ed,
- 0xce00edea,
- 0x00edec82,
- 0xedee82ce,
- 0xf082ce00,
+ 0x96a1ccf6,
0x82ce00ed,
- 0xce00edf2,
- 0x93ccf482,
- 0xce00ed9d,
- 0x9accf682,
- 0xce00ed3c,
- 0x91ccf882,
- 0xce00edb5,
- 0x91ccfa82,
- 0xbd00edf8,
- 0x82ce349b,
- 0x6698cc9a,
- 0xce0e00ed,
+ 0xbc92ccf8,
+ 0x82ce00ed,
+ 0xff92ccfa,
+ 0xa2bd00ed,
+ 0x9a82ce8e,
+ 0xed609fcc,
+ 0xce180e00,
0x01c6ed84,
- 0x02c600e7,
- 0x9dcc00e7,
- 0x659dfd44,
- 0xcfa09dfd,
- 0x00defd20,
- 0x3c02de3c,
- 0xde3c04de,
- 0x069f3c06,
- 0x3806df38,
- 0xdf3804df,
- 0x00df3802,
- 0x3c00de3b,
- 0xde3c02de,
- 0x06de3c04,
- 0x38069f3c,
- 0xdf3806df,
- 0x02df3804,
- 0x3b00df38,
+ 0xce00e718,
+ 0x00cc00bf,
+ 0xc600ed33,
+ 0x00e71802,
+ 0xfda9a4cc,
+ 0xa5fdcaa4,
+ 0xfd20cf05,
+ 0xde3c00de,
+ 0x04de3c02,
+ 0x3c06de3c,
+ 0xdf38069f,
+ 0x04df3806,
+ 0x3802df38,
+ 0xde3b00df,
+ 0x02de3c00,
+ 0x3c04de3c,
0x9f3c06de,
0x06df3806,
- 0x3c06de39,
- 0x7ece069f,
- 0xe7dfc601,
- 0x647ece00,
- 0xed02ffcc,
- 0x627ece00,
- 0xed0086cc,
- 0x017ece00,
- 0x20c400e6,
- 0x95bdf727,
- 0x06df3801,
- 0x3c06de39,
- 0x85ce069f,
- 0xce00e607,
- 0x8c4f0000,
+ 0x3804df38,
+ 0xdf3802df,
+ 0x06de3b00,
+ 0x38069f3c,
+ 0xde3906df,
+ 0x069f3c06,
+ 0xe60086ce,
+ 0x220bc100,
+ 0xce408d07,
+ 0x00adc8cc,
+ 0x3906df38,
+ 0x9f3c06de,
+ 0x0086ce06,
+ 0x0bc100e6,
+ 0x278d2522,
+ 0xc6017ece,
+ 0xce00e7df,
+ 0xffcc647e,
+ 0xce00ed02,
+ 0x86cc627e,
+ 0xce00ed00,
+ 0x00e6017e,
+ 0xf72720c4,
+ 0x38259cbd,
+ 0xde3906df,
+ 0x069f3c06,
+ 0xde3c08de,
+ 0x86ce3c0a,
+ 0xdd5f4f08,
+ 0xdf08dd0a,
+ 0x1d02de02,
+ 0xdf183f00,
+ 0x02de1804,
+ 0x00c38f18,
+ 0xdc8f1807,
+ 0xc308de0a,
+ 0x01240100,
+ 0xdf0add08,
+ 0x02df1808,
+ 0x8c04de18,
0x06260000,
- 0x0100831a,
- 0x008c2d27,
- 0x2b362e00,
- 0x00831a34,
- 0x8c0b2201,
- 0x29260000,
- 0x0f2700dd,
- 0x008c2320,
- 0x1a1e2600,
- 0x27020083,
- 0xcc162012,
- 0x95bd0885,
- 0xcc0e2029,
- 0x95bd3085,
- 0xcc062029,
- 0x95bd5885,
- 0x06df3829,
- 0x3c06de39,
- 0x08de069f,
- 0x3c0ade3c,
- 0x1daa7fce,
- 0x7fce0100,
- 0x10001c8f,
- 0x6b8d1bc6,
- 0x36377f84,
- 0x92bd1bc6,
- 0x8d04c6f7,
- 0x8f7fce5e,
- 0xce10001d,
- 0x001daa7f,
- 0x01001c01,
- 0xdf383131,
+ 0x0a00831a,
+ 0x04dfcf23,
+ 0x4f0486ce,
+ 0xdd0add5f,
+ 0xde02df08,
+ 0xdf02de04,
+ 0x00de1800,
+ 0x04df0818,
+ 0x0700c38f,
+ 0x00ec188f,
+ 0x02dff084,
+ 0x831a04de,
+ 0x1426fe00,
+ 0x18fe00cc,
+ 0x001d00ed,
+ 0xc400e680,
+ 0x2620c1f0,
+ 0x0e001d03,
+ 0x08de0adc,
+ 0x240100c3,
+ 0x0add0801,
+ 0x062608df,
+ 0x0a00831a,
+ 0xdf38b723,
0x08df380a,
0x3906df38,
0x9f3c06de,
+ 0x0785ce06,
+ 0x00ce00e6,
+ 0x008c4f00,
+ 0x1a062600,
+ 0x27010083,
+ 0x00008c2d,
+ 0x342b362e,
+ 0x0100831a,
+ 0x008c0b22,
+ 0xdd292600,
+ 0x200f2700,
+ 0x00008c23,
+ 0x831a1e26,
+ 0x12270200,
+ 0x85cc1620,
+ 0x4d9cbd08,
+ 0x85cc0e20,
+ 0x4d9cbd30,
+ 0x85cc0620,
+ 0x4d9cbd58,
+ 0x3906df38,
+ 0x9f3c06de,
0x3c08de06,
0xce3c0ade,
0x001daa7f,
0x8f7fce01,
0xc610001c,
- 0x8a288d1b,
- 0xc6363780,
- 0xf792bd1b,
- 0x1b8d04c6,
+ 0x846b8d1b,
+ 0xc636377f,
+ 0xfe93bd1b,
+ 0x5e8d04c6,
0x1d8f7fce,
0x7fce1000,
0x01001daa,
0xde3906df,
0x069f3c06,
0xde3c08de,
- 0x0cde3c0a,
- 0x3c0ede3c,
- 0x00cc0dd7,
- 0x4f36374d,
+ 0x7fce3c0a,
+ 0x01001daa,
+ 0x1c8f7fce,
+ 0x1bc61000,
+ 0x808a288d,
+ 0x1bc63637,
+ 0xc6fe93bd,
+ 0xce1b8d04,
+ 0x001d8f7f,
+ 0xaa7fce10,
+ 0x1c01001d,
+ 0x31310100,
+ 0x380adf38,
+ 0xdf3808df,
+ 0x06de3906,
+ 0xde069f3c,
+ 0x0ade3c08,
+ 0x3c0cde3c,
+ 0xd73c0ede,
+ 0x4d00cc0d,
+ 0x5f4f3637,
+ 0x00cc3637,
+ 0x0002ce60,
+ 0xcc5a9ebd,
+ 0x02ce6400,
+ 0x389ebd00,
+ 0x00cc08df,
+ 0x4f3637cd,
0xcc36375f,
0x02ce6000,
- 0x3697bd00,
+ 0x5a9ebd00,
+ 0x0dd68f18,
+ 0xdf188f18,
+ 0x0e007f0e,
+ 0x0cdd0edc,
+ 0x7f0f007f,
+ 0x38180e00,
+ 0x38183818,
+ 0x08dc3818,
+ 0x08260185,
+ 0x8a8f0cde,
+ 0x0cdf8f01,
+ 0x36370edc,
+ 0x36370cdc,
0xce6400cc,
- 0x97bd0002,
- 0xcc08df14,
- 0x3637cd00,
- 0x36375f4f,
- 0xce6000cc,
- 0x97bd0002,
- 0xd68f1836,
- 0x188f180d,
- 0x007f0edf,
- 0xdd0edc0e,
- 0x0f007f0c,
- 0x180e007f,
+ 0x9ebd0002,
+ 0x4e00cc5a,
+ 0x5f4f3637,
+ 0x00cc3637,
+ 0x0002ce60,
+ 0xcc5a9ebd,
+ 0x02ce6400,
+ 0x389ebd00,
+ 0x38183818,
+ 0x38183818,
+ 0xdf183818,
+ 0x1838180e,
+ 0x38180cdf,
+ 0x180adf18,
+ 0x08df1838,
+ 0xdf183818,
+ 0x06de3906,
+ 0xde069f3c,
+ 0x0ade3c08,
+ 0x3c0cde3c,
+ 0xd73c0ede,
+ 0x4d00cc0d,
+ 0x5f4f3637,
+ 0x00cc3637,
+ 0x0002ce60,
+ 0xcc5a9ebd,
+ 0x02ce6400,
+ 0x389ebd00,
+ 0x00cc08df,
+ 0x4f3637cd,
+ 0xcc36375f,
+ 0x02ce6000,
+ 0x5a9ebd00,
+ 0x0dd68f18,
+ 0xdf188f18,
+ 0x0e007f0e,
+ 0x7f0d007f,
+ 0x5f4f0c00,
+ 0x8f0002ce,
+ 0x0fda0e9a,
+ 0xdf0edd8f,
+ 0xec06de0c,
+ 0xda0e9a05,
+ 0xdd0cde0f,
+ 0x1838180e,
0x18381838,
- 0xdc381838,
- 0x26018508,
- 0x8f0cde08,
+ 0x8508dc38,
+ 0x8f062601,
0xdf8f018a,
0x370edc0c,
0x370cdc36,
0x6400cc36,
0xbd0002ce,
- 0x00cc3697,
- 0x4f36374e,
- 0xcc36375f,
- 0x02ce6000,
- 0x3697bd00,
- 0xce6400cc,
- 0x97bd0002,
- 0x18381814,
- 0x18381838,
- 0x18381838,
- 0x38180edf,
- 0x180cdf18,
- 0x0adf1838,
- 0xdf183818,
- 0x18381808,
- 0xde3906df,
- 0x069f3c06,
- 0xde3c08de,
- 0x0cde3c0a,
- 0x3c0ede3c,
- 0x00cc0dd7,
- 0x4f36374d,
- 0xcc36375f,
- 0x02ce6000,
- 0x3697bd00,
- 0xce6400cc,
- 0x97bd0002,
- 0xcc08df14,
- 0x3637cd00,
- 0x36375f4f,
- 0xce6000cc,
- 0x97bd0002,
- 0xd68f1836,
- 0x188f180d,
- 0x007f0edf,
- 0x0d007f0e,
- 0x4f0c007f,
- 0x0002ce5f,
- 0xda0e9a8f,
- 0x0edd8f0f,
- 0x06de0cdf,
- 0x0e9a05ec,
- 0x0cde0fda,
- 0x38180edd,
- 0x38183818,
- 0x08dc3818,
- 0x06260185,
- 0x8f018a8f,
- 0x0edc0cdf,
- 0x0cdc3637,
- 0x00cc3637,
- 0x0002ce64,
- 0x383697bd,
- 0x0edf3838,
- 0x380cdf38,
- 0xdf380adf,
- 0x06df3808,
- 0x3c06de39,
- 0x08de069f,
- 0x3c0ade3c,
- 0xde3c0cde,
- 0x85ce3c0e,
- 0xdd02ec90,
- 0xdd00ec0e,
- 0x5f0edc0c,
- 0x04caf084,
- 0x0edd0e8a,
- 0x1daa7fce,
- 0x0cde0100,
- 0xdd7196bd,
- 0xce08df0a,
- 0x00e69785,
- 0x0adc0626,
- 0x0420118a,
- 0xef840adc,
- 0x36370add,
- 0x363708dc,
- 0x0cde0edc,
- 0xcebc96bd,
- 0x001caa7f,
- 0x38383801,
- 0xdf380edf,
- 0x0adf380c,
- 0x3808df38,
- 0xde3906df,
- 0x069f3c06,
- 0x80ce8f18,
- 0x2600e6ff,
- 0xe704c60c,
- 0x207ece00,
- 0x2001001c,
- 0x04001c03,
- 0xc6007ece,
- 0xce00e7ef,
- 0x00ec217e,
- 0xd300df18,
- 0x277ece00,
- 0x7ece00ed,
- 0xc400e600,
- 0xcef72710,
- 0x001dff80,
- 0x2600e604,
- 0x207ece06,
- 0x3801001d,
- 0xde3906df,
- 0x069f3c06,
- 0xe68385ce,
- 0x2701c400,
- 0xb885ce74,
+ 0x38385a9e,
+ 0x380edf38,
+ 0xdf380cdf,
+ 0x08df380a,
+ 0x3906df38,
+ 0x9f3c06de,
+ 0x3c08de06,
+ 0xde3c0ade,
+ 0x0ede3c0c,
+ 0x9085ce3c,
+ 0x0edd02ec,
+ 0x0cdd00ec,
+ 0x845f0edc,
+ 0x8a04caf0,
+ 0xce0edd0e,
+ 0x001daa7f,
+ 0xbd0cde01,
+ 0x0add959d,
+ 0x85ce08df,
+ 0x2600e697,
+ 0x8a0adc06,
+ 0xdc042011,
+ 0xddef840a,
+ 0xdc36370a,
+ 0xdc363708,
+ 0xbd0cde0e,
+ 0x7fcee09d,
+ 0x01001caa,
+ 0xdf383838,
+ 0x0cdf380e,
+ 0x380adf38,
+ 0xdf3808df,
+ 0x06de3906,
+ 0x18069f3c,
+ 0xff80ce8f,
+ 0x0c2600e6,
+ 0x00e704c6,
+ 0x1c207ece,
+ 0x03200100,
+ 0xce04001c,
+ 0xefc6007e,
+ 0x7ece00e7,
+ 0x1800ec21,
+ 0x00d300df,
+ 0xed277ece,
+ 0x007ece00,
+ 0x10c400e6,
+ 0x80cef727,
+ 0x04001dff,
+ 0x062600e6,
+ 0x1d207ece,
+ 0xdf380100,
+ 0x06de3906,
+ 0xde069f3c,
+ 0x85ce3c08,
+ 0xce00e683,
+ 0x8f188485,
+ 0x09d700e6,
+ 0x09d18f18,
+ 0x967e0326,
+ 0x8385ce65,
+ 0x01c400e6,
+ 0x967e0326,
+ 0xb885ce3b,
0x02ed5f4f,
0x85ce00ed,
0xed02edbc,
0x02edc885,
0x85ce00ed,
0xed02edcc,
- 0x8285ce00,
- 0x08c400e6,
- 0x97bd0326,
- 0xff80ceaa,
- 0xce08001c,
- 0x00e68285,
- 0x7ecef0c4,
- 0xe701ca20,
- 0x217ece00,
- 0xce00ee1a,
- 0x00ec8085,
- 0x8f1800dd,
- 0x8f1800d3,
- 0x1a297ece,
- 0x7ece00ef,
- 0xe7dfc600,
- 0x027ece00,
- 0x2020001c,
- 0xff80ce20,
+ 0x85ce1800,
+ 0x00e61882,
+ 0x032608c4,
+ 0xcece9ebd,
+ 0x02cc0883,
+ 0xce00ed00,
+ 0x5f4f1483,
+ 0x00ed02ed,
+ 0xed1083ce,
+ 0x1800ed02,
+ 0x188385ce,
+ 0xce5400e6,
+ 0x00e71283,
+ 0xe68585ce,
+ 0x5d02df00,
+ 0x80ce3a26,
+ 0x08001cff,
+ 0xe68285ce,
+ 0xcef0c400,
+ 0x01ca207e,
+ 0x7ece00e7,
+ 0x00ee1a21,
+ 0xec8085ce,
+ 0x1800dd00,
+ 0x1800d38f,
+ 0x297ece8f,
+ 0xce00ef1a,
+ 0xdfc6007e,
+ 0x7ece00e7,
+ 0x20001c02,
+ 0x02de04df,
+ 0xde01001c,
+ 0xce2a2004,
+ 0x001d8585,
+ 0x2600e601,
+ 0xff80ce1d,
0xe608001d,
0xce062600,
0x001d207e,
0x007ece01,
0x00e7dfc6,
0x1d027ece,
- 0x99bd2000,
- 0x06df38c1,
+ 0xa1bd2000,
+ 0x8385ce1b,
+ 0x85ce00e6,
+ 0x3800e784,
+ 0xdf3808df,
+ 0x06de3906,
+ 0x8d069f3c,
+ 0x8585ce1c,
+ 0x032600e6,
+ 0xce7d97bd,
+ 0x001c8585,
+ 0x9a82ce02,
+ 0xedcd97cc,
+ 0x06df3800,
+ 0x3c06de39,
+ 0x08de069f,
+ 0x3c0ade3c,
+ 0xec4485ce,
+ 0x10c44f00,
+ 0x02ec2027,
+ 0x00ec0add,
+ 0x0adc08dd,
+ 0x4f8f08de,
+ 0xbd8f0fc4,
+ 0xce1897a4,
+ 0xed18d085,
+ 0x00efcd02,
+ 0x02ec1c20,
+ 0x00ec0add,
+ 0x0adc08dd,
+ 0x4f8f08de,
+ 0xdf8f0fc4,
+ 0xd085ce08,
+ 0x08dc02ed,
+ 0x85ce00ed,
+ 0x4f00ec48,
+ 0x202710c4,
+ 0x0add02ec,
+ 0x08dd00ec,
+ 0x08de0adc,
+ 0x0fc44f8f,
+ 0x97a4bd8f,
+ 0xd485ce18,
+ 0xcd02ed18,
+ 0x1c2000ef,
+ 0x0add02ec,
+ 0x08dd00ec,
+ 0x08de0adc,
+ 0x0fc44f8f,
+ 0xce08df8f,
+ 0x02edd485,
+ 0x00ed08dc,
+ 0xcc5884ce,
+ 0x00ed0091,
+ 0xcc5a84ce,
+ 0x00ed0cc4,
+ 0xad0490fe,
+ 0x85ce1800,
+ 0x5e84ced8,
+ 0x0f8400ec,
+ 0x1800ed18,
+ 0x85ce00ec,
+ 0x4f00edda,
+ 0x1285ce5f,
+ 0x85ce00ed,
+ 0xce00ed10,
+ 0x00e7977f,
+ 0xc60b85ce,
+ 0x3800e701,
+ 0xdf380adf,
+ 0x06df3808,
+ 0x3c06de39,
+ 0xce069f34,
+ 0x001cff80,
+ 0x0e85ce08,
+ 0x06de00ec,
+ 0x011d01e7,
+ 0x217ece0f,
+ 0xce00ee1a,
+ 0x00ec0c85,
+ 0x8f1800dd,
+ 0x8f1800d3,
+ 0x1a297ece,
+ 0x7ece00ef,
+ 0x06de1820,
+ 0xca01e618,
+ 0xce00e701,
+ 0xdfc6007e,
+ 0x7ece00e7,
+ 0x20001c02,
+ 0x06df3831,
+ 0x3c06de39,
+ 0x069f3c3c,
+ 0xde3c08de,
+ 0x0cde3c0a,
+ 0x3c0ede3c,
+ 0xce779abd,
+ 0x00e6de85,
+ 0x997e0327,
+ 0x5884ce21,
+ 0xed0090cc,
+ 0x5a84ce00,
+ 0x50c7ce18,
+ 0xfe00ef1a,
+ 0x00ad0490,
+ 0xec5c84ce,
+ 0x10c44f00,
+ 0x02ec2027,
+ 0x00ec0add,
+ 0x0adc08dd,
+ 0x4f8f08de,
+ 0xbd8f0fc4,
+ 0xce1897a4,
+ 0xed18e085,
+ 0x00efcd02,
+ 0x02ec1c20,
+ 0x00ec0add,
+ 0x0adc08dd,
+ 0x4f8f08de,
+ 0xdf8f0fc4,
+ 0xe085ce08,
+ 0x08dc02ed,
+ 0x85ce00ed,
+ 0xc400e60b,
+ 0x18452601,
+ 0x18977fce,
+ 0x01c400e6,
+ 0x85ce3a26,
+ 0xdd02ece0,
+ 0xdd00ec0e,
+ 0xd085ce0c,
+ 0x0add02ec,
+ 0x08dd00ec,
+ 0x089c0cde,
+ 0x072e1e2d,
+ 0x931a0edc,
+ 0xc615230a,
+ 0x00e71801,
+ 0x1c1285ce,
+ 0x85ce0101,
+ 0x6f016f10,
+ 0x21997e00,
+ 0x4f06de18,
+ 0x03ed185f,
+ 0xce01ed18,
+ 0x00e60b85,
+ 0x262601c4,
+ 0xece085ce,
+ 0xec0edd02,
+ 0xce0cdd00,
+ 0x02ecd485,
+ 0x00ec0add,
+ 0xde1808dd,
+ 0x089c180c,
+ 0x142e082d,
+ 0x0a9c0ede,
+ 0xde180e24,
+ 0x0100cc06,
+ 0x4f03ed18,
+ 0x01ed185f,
+ 0x0add5f4f,
+ 0x7fce08dd,
+ 0xc100e684,
+ 0xcc072607,
+ 0x0add0100,
+ 0xde185f4f,
+ 0x03ec1806,
+ 0x9401eecd,
+ 0x8f0bd40a,
+ 0x09d40894,
+ 0x00008c8f,
+ 0x00dd0426,
+ 0x7fce0f27,
+ 0xe702c697,
+ 0x1285ce00,
+ 0x011d006f,
+ 0x847fce01,
+ 0x07c100e6,
+ 0x85ce1226,
+ 0x02011c12,
+ 0xec1085ce,
+ 0x0100c300,
+ 0x082000ed,
+ 0x6f1285ce,
+ 0x02011d00,
+ 0xe60b85ce,
+ 0x2602c400,
+ 0x239a7e03,
+ 0xe6847fce,
+ 0x2607c100,
+ 0x85ce1860,
+ 0x00ec1812,
+ 0x2604c44f,
+ 0x0090cc54,
+ 0xed5884ce,
+ 0x68c3ce00,
+ 0x5a84ce18,
+ 0xfe00efcd,
+ 0x00ad0490,
+ 0x5c84ce18,
+ 0xdd02ec18,
+ 0x00ec180a,
+ 0x0adc08dd,
+ 0xed1820ca,
+ 0x1808dc02,
+ 0x80ce00ed,
+ 0x84ce1800,
+ 0x00efcd58,
+ 0x1868c3ce,
+ 0xcd5a84ce,
+ 0x90fe00ef,
+ 0x1800ad06,
+ 0x181285ce,
+ 0x2004011c,
+ 0x847fce6a,
+ 0x07c100e6,
+ 0x85ce6127,
+ 0x4f00ec12,
+ 0x572704c4,
+ 0x180090ce,
+ 0xcd5884ce,
+ 0xc3ce00ef,
+ 0x84ce1868,
+ 0x00efcd5a,
+ 0xad0490fe,
+ 0x84ce1800,
+ 0x02ec185c,
+ 0xec180add,
+ 0xdc08dd00,
+ 0x18dfc40a,
+ 0x08dc02ed,
+ 0xce00ed18,
+ 0xce180080,
+ 0xefcd5884,
+ 0x68c3ce00,
+ 0x5a84ce18,
+ 0xfe00efcd,
+ 0x00ad0690,
+ 0x1285ce18,
+ 0x18006f18,
+ 0xce04011d,
+ 0x00e68385,
+ 0x188485ce,
+ 0xd700e68f,
+ 0xd18f1809,
+ 0xbd032709,
+ 0x85ce6295,
+ 0xc400e683,
+ 0xbd032701,
+ 0x7ece609f,
+ 0x00ee1a21,
+ 0xec0c85ce,
+ 0x1800dd00,
+ 0x1800d38f,
+ 0x297ece8f,
+ 0xce00ef1a,
+ 0x001d007e,
+ 0x0edf3820,
+ 0x380cdf38,
+ 0xdf380adf,
+ 0x38383808,
+ 0xde3906df,
+ 0x069f3c06,
+ 0xce3c08de,
+ 0x01c6687e,
+ 0xce1800e7,
+ 0xfecc647e,
+ 0x00ed1870,
+ 0xcc667ece,
+ 0x00ed0200,
+ 0xce00e618,
+ 0x00e6677e,
+ 0xf72701c4,
+ 0xe6637ece,
+ 0x5404c400,
+ 0xdc85ce54,
+ 0xce1800e7,
+ 0xfecc647e,
+ 0x00ed1880,
+ 0xcc667ece,
+ 0x00ed0200,
+ 0xce00e618,
+ 0x00e6677e,
+ 0xf72701c4,
+ 0xe6637ece,
+ 0x5404c400,
+ 0xdd85ce54,
+ 0xce1800e7,
+ 0xfecc647e,
+ 0x00ed1860,
+ 0xcc667ece,
+ 0x00ed0200,
+ 0xce00e618,
+ 0x00e6677e,
+ 0xf72701c4,
+ 0xe6637ece,
+ 0x5404c400,
+ 0xde85ce54,
+ 0xce1800e7,
+ 0x85cedf85,
+ 0xce00e6dc,
+ 0x04dddd85,
+ 0x09d700e6,
+ 0x09d404dc,
+ 0x1800e718,
+ 0xce1804df,
+ 0x85ce0088,
+ 0xce00ecd8,
+ 0x00ee4285,
+ 0x00d300df,
+ 0x1800ed18,
+ 0xde1802df,
+ 0x00e61804,
+ 0x052601c1,
+ 0x202285ce,
+ 0x847fce1d,
+ 0x07c100e6,
+ 0x85ce0526,
+ 0xe60f201e,
+ 0x0000ce00,
+ 0x598f054f,
+ 0x85c38f49,
+ 0x00ec8f14,
+ 0x08dd0f84,
+ 0x00ec02de,
+ 0x00ed0893,
+ 0xda85ce18,
+ 0x1804df18,
+ 0xcd0088ce,
+ 0xdf1800ee,
+ 0x04de1802,
+ 0xdd00ec18,
+ 0x27009c00,
+ 0xec02de45,
+ 0x00ed1800,
+ 0xce0091cc,
+ 0x00ed5884,
+ 0x180cc4ce,
+ 0xcd5a84ce,
+ 0x90fe00ef,
+ 0xce00ad04,
+ 0x00ec0088,
+ 0xed5e84ce,
+ 0x0081cc00,
+ 0xed5884ce,
+ 0x0cc4ce00,
+ 0x1804df18,
+ 0xcd5a84ce,
+ 0xde1800ef,
+ 0x0690fe04,
+ 0xdf3800ad,
+ 0x06df3808,
+ 0x3c06de39,
+ 0x84ce069f,
+ 0xc400ecf2,
+ 0x7e831af0,
+ 0xec072660,
+ 0x5000c300,
+ 0xcdce00ed,
+ 0x3800ad83,
+ 0xde3906df,
+ 0x069f3c06,
+ 0xecfc84ce,
+ 0x1af0c400,
+ 0x2600fe83,
+ 0xc300ec07,
+ 0x00ed5000,
+ 0xad29cece,
+ 0x06df3800,
0x3c08de39,
0xb65086ce,
0x19270086,
0x1803a718,
0xfd8602e7,
0x7e04a718,
- 0xde188b96,
+ 0xde18af9d,
0x9f3c1806,
0x7fce1806,
0x01a71880,
0x03a718fc,
0x8602e718,
0x04a718fd,
- 0xeddb967e,
+ 0xedff9d7e,
0x8407a602,
0x39fa2701,
0x018407a6,
0xecef2e4a,
0xfecc3902,
0xfc84fd00,
- 0xfdf370cc,
+ 0xfd4470cc,
0x00ccfe84,
0xfa84fd03,
- 0x8de0d6bd,
- 0xa085f775,
+ 0x8d29cebd,
+ 0xa085f75b,
0x8fa185b7,
0x86a285b7,
- 0xff84b7f6,
- 0x8de0d6bd,
- 0xa385f761,
+ 0xff84b747,
+ 0x8d29cebd,
+ 0xa385f747,
0x8fa685b7,
0x86a785b7,
- 0xff84b7f9,
- 0x8de0d6bd,
- 0xae85fd4d,
+ 0xff84b74a,
+ 0x8d29cebd,
+ 0xae85fd33,
0xad85b78f,
- 0x84b7fc86,
- 0xe0d6bdff,
- 0x85fd3c8d,
+ 0x84b74d86,
+ 0x29cebdff,
+ 0x85fd228d,
0x85b78faa,
- 0xb7ff86a9,
- 0xd6bdff84,
- 0xf72b8de0,
+ 0xb75086a9,
+ 0xcebdff84,
+ 0xf7118d29,
0x85b7a485,
0x85b78fa5,
- 0x0a71cca8,
- 0xbdfe84fd,
- 0x85cee0d6,
- 0x02ee1a00,
- 0x185401e6,
- 0x1856468f,
- 0x8f18548f,
- 0x84fd5646,
- 0x08de39be,
- 0x0085ce3c,
- 0x03a600e6,
- 0x01e608dd,
- 0x007902a6,
- 0x79495909,
- 0x00790800,
- 0x79495909,
- 0x00790800,
- 0x79495909,
- 0x08de0800,
- 0xdf183818,
- 0x08de3908,
- 0x0090cc3c,
- 0xcc5884fd,
- 0x84fde4c6,
- 0xc3e4bd5a,
- 0xb60000ce,
- 0xc4165f84,
- 0x04163a01,
- 0x3a01c404,
- 0xc4040416,
- 0x04163a01,
- 0x3a01c404,
- 0x04cb508f,
- 0xce4f08d7,
- 0x9abdb885,
- 0x4f08d60a,
+ 0x0000cca8,
+ 0x39be84fd,
+ 0xce3c08de,
+ 0x03e60085,
+ 0x08dd02a6,
+ 0x01a600e6,
+ 0x76090076,
+ 0x56460800,
+ 0x381808de,
+ 0x3908df18,
+ 0xde3c08de,
+ 0x7ece3c0a,
+ 0xa7038660,
+ 0x60fecc08,
+ 0x00cc04ed,
+ 0xa606ed02,
+ 0x8407a604,
+ 0x4ffa2701,
+ 0x03a60b97,
+ 0x0a970184,
+ 0xa62e274d,
+ 0x97048403,
+ 0x25274d0a,
+ 0xec1083ce,
+ 0x110f2702,
+ 0x97048407,
+ 0x04274d0b,
+ 0x0220036f,
+ 0x83f6036c,
+ 0x1a08d708,
+ 0x081806ee,
+ 0x2006ef1a,
+ 0x1083ce2d,
+ 0x90cc036f,
+ 0x5884fd00,
+ 0xfde4c6cc,
+ 0xd6bd5a84,
+ 0x0000ce99,
+ 0x165f84b6,
+ 0x163a01c4,
+ 0x01c40404,
+ 0xcb508f3a,
+ 0xf708d702,
+ 0xce4f0883,
+ 0xa1bdb885,
+ 0x4f08d664,
0xbdc085ce,
- 0x85f60a9a,
+ 0x85f664a1,
0x1809d7a6,
0xbdb885ce,
- 0x85f6ee99,
+ 0x85f648a1,
0x1809d7a7,
0xbdc085ce,
- 0x8086ee99,
+ 0x808648a1,
0x85b60897,
0x27048482,
0x607ece5b,
0x03a6fa27,
0x44440484,
0xce5f0188,
- 0x9abdc885,
- 0xa585f60a,
+ 0xa1bdc885,
+ 0xa585f664,
0xce1809d7,
- 0x99bdc885,
- 0xcc85ceee,
+ 0xa1bdc885,
+ 0xcc85ce48,
0x0000ce18,
0x142600ec,
0x102602a6,
0x85b103a6,
- 0x18092ca4,
+ 0x180924a4,
0xb6be84fe,
0x0897a885,
0xab7fff18,
0xad7fb74f,
0xf6ac85ce,
- 0xfe18a085,
- 0x2026bc85,
+ 0xfe18a285,
+ 0x1226bc85,
0x26be85b6,
- 0xbf85b61b,
+ 0xbf85b60d,
0xa1a385f6,
- 0xf6112d03,
- 0x02a1a285,
- 0x85f60a2d,
- 0x2d01a1a1,
- 0xa085f603,
- 0x85ce09d7,
- 0xa085f6a8,
- 0xc485fe18,
- 0x85b61d26,
- 0xb61826c6,
- 0x01a1c785,
- 0x85f6112e,
- 0x2e02a1a1,
- 0xa285f60a,
- 0x032e03a1,
+ 0xf6032503,
+ 0x09d7a285,
+ 0xf6a885ce,
+ 0xfe18a285,
+ 0x0f26c485,
+ 0x26c685b6,
+ 0xc785b60a,
+ 0x032203a1,
0xd1a385f6,
- 0xd7022e09,
+ 0xd7022209,
0x4f08d609,
0xd68f1805,
- 0xeabd4f09,
- 0xcc09d740,
+ 0xdcbd4f09,
+ 0x9609d706,
+ 0xcc1c260a,
0x84fd0091,
0x0cc4cc58,
0xbd5a84fd,
- 0x09d6c3e4,
+ 0x09d699d6,
0xc65d84f7,
0x5884f781,
- 0xfc92e4bd,
- 0x7ef38085,
- 0x297efd21,
- 0x7eb7df86,
- 0x08df3800,
- 0x0091cc39,
- 0xcc5884fd,
- 0x84fd0cc4,
- 0xc3e4bd5a,
- 0xf7a085f6,
- 0x81c65d84,
- 0xbd5884f7,
- 0x85b692e4,
- 0x27048482,
- 0xfd4f5f08,
- 0x7fb7ab7f,
- 0xec1839ad,
- 0x02eecd00,
- 0x2709007d,
- 0x468f040a,
- 0x007a8f56,
- 0x18f62609,
- 0xefcd04ed,
- 0x58583906,
- 0x02e35858,
- 0x00ec02ed,
- 0x008900c9,
- 0x04ec00ed,
- 0x8f184353,
- 0x435306ec,
- 0x180100c3,
- 0x8900c98f,
- 0xe38f1800,
- 0x1802ed02,
- 0xa901e98f,
- 0x3900ed00,
- 0xde3c06de,
- 0x069f3c08,
- 0x1daa7fce,
- 0x7fce0100,
- 0x10001c8f,
+ 0xce68d6bd,
+ 0x04ec1083,
+ 0xed0100c3,
+ 0x0000c304,
+ 0x8f180a26,
+ 0x00ed06ec,
+ 0x06ed8f18,
+ 0x848585b6,
+ 0x96112602,
+ 0x85f35f0b,
+ 0x217ef380,
+ 0x86297efd,
+ 0x007eb7df,
+ 0x380adf38,
+ 0xcc3908df,
+ 0x84fd0091,
+ 0x0cc4cc58,
+ 0xbd5a84fd,
+ 0x85f699d6,
+ 0x5d84f7a0,
+ 0x84f781c6,
+ 0x68d6bd58,
+ 0x848285b6,
+ 0x5f082704,
+ 0xab7ffd4f,
+ 0x39ad7fb7,
+ 0xcd00ec18,
+ 0x007d02ee,
+ 0x040a2709,
+ 0x8f56468f,
+ 0x2609007a,
+ 0x04ed18f6,
+ 0x3906efcd,
+ 0x58585858,
+ 0x02ed02e3,
+ 0x00c900ec,
+ 0x00ed0089,
+ 0x435304ec,
+ 0x06ec8f18,
+ 0x00c34353,
+ 0xc98f1801,
+ 0x18008900,
+ 0xed02e38f,
+ 0xe98f1802,
+ 0xed00a901,
+ 0x06de3900,
+ 0x3c08de3c,
+ 0x7fce069f,
+ 0x01001daa,
+ 0x1c8f7fce,
+ 0x0ccc1000,
+ 0x0000ced6,
+ 0xd7499dbd,
+ 0x37c8c608,
+ 0xd60ccc34,
+ 0xbd0000ce,
+ 0x0cccf19c,
+ 0x0000ced7,
+ 0xca499dbd,
+ 0xcc343720,
+ 0x00ced70c,
+ 0xf19cbd00,
+ 0x3437d8c6,
0xced60ccc,
- 0x96bd0000,
- 0xc608d725,
- 0xcc3437c8,
- 0x00ced60c,
- 0xcd95bd00,
- 0xced70ccc,
- 0x96bd0000,
- 0x3720ca25,
+ 0x9cbd0000,
+ 0x371fc6f1,
0xd70ccc34,
0xbd0000ce,
- 0xd8c6cd95,
+ 0xd9c6f19c,
0x0ccc3437,
0x0000ced6,
- 0xc6cd95bd,
- 0xcc34371f,
+ 0xccf19cbd,
0x00ced70c,
- 0xcd95bd00,
- 0x3437d9c6,
- 0xced60ccc,
- 0x95bd0000,
- 0xd70ccccd,
+ 0x499dbd00,
+ 0x00c38f30,
+ 0xc4358f0a,
+ 0x8d022620,
+ 0x3708d644,
+ 0xd60ccc34,
0xbd0000ce,
- 0x8f302596,
- 0x8f0a00c3,
- 0x2620c435,
- 0xd6448d02,
- 0xcc343708,
- 0x00ced60c,
- 0xcd95bd00,
- 0x00a0cc38,
- 0xbd0002ce,
- 0x20ca2596,
- 0x022722c1,
- 0xa0cc258d,
- 0x0002ce01,
- 0xc12596bd,
- 0x8d022710,
- 0x8f7fce16,
- 0xce10001d,
- 0x001daa7f,
- 0x01001c01,
- 0x3808df38,
- 0xce3906df,
- 0x0386607e,
- 0xffcc08a7,
- 0xcc04ed30,
- 0x06ede701,
- 0x00ed5f4f,
- 0x02ed7fc6,
- 0x018407a6,
- 0x01ccfa27,
- 0x5f06ede9,
- 0xed00ed4f,
- 0x8407a602,
- 0x01fa2701,
- 0x39fd20cf,
- 0xcc607ece,
- 0x04ed30ff,
- 0xed3d26cc,
+ 0xcc38f19c,
+ 0x02ce00a0,
+ 0x499dbd00,
+ 0x22c120ca,
+ 0x258d0227,
+ 0xce01a0cc,
+ 0x9dbd0002,
+ 0x2710c149,
+ 0xce168d02,
+ 0x001d8f7f,
+ 0xaa7fce10,
+ 0x1c01001d,
+ 0xdf380100,
+ 0x06df3808,
+ 0x607ece39,
+ 0x08a70386,
+ 0xed30ffcc,
+ 0xe701cc04,
+ 0x5f4f06ed,
+ 0x7fc600ed,
+ 0x07a602ed,
+ 0xfa270184,
+ 0xede901cc,
+ 0xed4f5f06,
+ 0xa602ed00,
+ 0x27018407,
+ 0x20cf01fa,
+ 0x7ece39fd,
+ 0x30ffcc60,
+ 0x26cc04ed,
+ 0xcc06ed3d,
+ 0x00edfe00,
+ 0x839ebd5f,
+ 0xede20fcc,
0xfe00cc06,
0xbd5f00ed,
- 0x0fcc5f97,
- 0xcc06ede2,
- 0x00edfe00,
- 0x5f97bd5f,
- 0xed5422cc,
- 0xfcffcc06,
- 0xfccc00ed,
- 0x5f97bd00,
- 0x3c08de39,
- 0xde3c0ade,
- 0x0ede3c0c,
- 0xb7df863c,
- 0x7ece017e,
- 0x02ffcc60,
- 0x9dcc04ed,
- 0xb602ed64,
- 0x2084017e,
- 0x01ccf927,
- 0xcc08dd01,
- 0x0add1100,
- 0xdd0000cc,
- 0x0f00cc0c,
- 0x9cbd0edd,
- 0x3001cca9,
- 0x80cc08dd,
- 0xcc0add62,
- 0x0cddffff,
- 0xddfff7cc,
- 0xdb9cbd0e,
- 0xdd0200cc,
- 0xffffcc0a,
- 0xffcc0cdd,
- 0xbd0eddfb,
- 0x80ccdb9c,
- 0xcc0add63,
- 0x0cdd0101,
- 0xdd0080cc,
- 0xa99cbd0e,
+ 0x22cc839e,
+ 0xcc06ed54,
+ 0x00edfcff,
+ 0xbd00fccc,
+ 0xde39839e,
+ 0x0ade3c08,
+ 0x3c0cde3c,
+ 0x863c0ede,
+ 0x017eb7df,
+ 0xcc607ece,
+ 0x04ed02ff,
+ 0xedc9a4cc,
+ 0x017eb602,
+ 0xf9272084,
+ 0xdd0101cc,
+ 0x1100cc08,
+ 0x00cc0add,
+ 0xcc0cdd00,
+ 0x0edd0f00,
+ 0xcc03a4bd,
+ 0x08dd3001,
0xdd6280cc,
+ 0xffffcc0a,
+ 0xf7cc0cdd,
+ 0xbd0eddff,
+ 0x00cc35a4,
+ 0xcc0add02,
+ 0x0cddffff,
+ 0xddfbffcc,
+ 0x35a4bd0e,
+ 0xdd6380cc,
+ 0x0101cc0a,
+ 0x80cc0cdd,
+ 0xbd0edd00,
+ 0x80cc03a4,
+ 0xcc0add62,
+ 0x0cdd0000,
+ 0xdd0100cc,
+ 0x03a4bd0e,
+ 0xdd6080cc,
0x0000cc0a,
0x00cc0cdd,
0xbd0edd01,
- 0x80cca99c,
+ 0xce1803a4,
+ 0x7ef60200,
+ 0x54545420,
+ 0x939ebd54,
+ 0xcc1295bd,
+ 0x08dd1001,
+ 0xdd1000cc,
+ 0x0000cc0a,
+ 0x00cc0cdd,
+ 0x8d0edd01,
+ 0x3001cc7e,
+ 0x80cc08dd,
0xcc0add60,
- 0x0cdd0000,
- 0xdd0100cc,
- 0xa99cbd0e,
- 0x0200ce18,
- 0x54207ef6,
- 0xbd545454,
- 0x94bd6f97,
- 0x1001cc0b,
- 0x00cc08dd,
- 0xcc0add10,
- 0x0cdd0000,
- 0xdd0100cc,
- 0xcc7e8d0e,
+ 0x0cdd0301,
+ 0xcc67a4bd,
0x08dd3001,
- 0xdd6080cc,
- 0x0301cc0a,
- 0x9dbd0cdd,
- 0x3001cc0d,
- 0x80cc08dd,
- 0xcc0add62,
- 0x0cddffff,
- 0xddfeffcc,
- 0xdb9cbd0e,
- 0xdd0000cc,
- 0x0008cc0c,
- 0x498d0edd,
- 0xdd6380cc,
- 0xfefecc0a,
- 0x7fcc0cdd,
- 0x8d0eddff,
- 0x2001cc6a,
- 0x44cc08dd,
- 0xcc0add50,
- 0x0cdd0203,
- 0x860d9dbd,
- 0x017eb7df,
- 0xcc607ece,
- 0x04ed02ff,
- 0xed9f9dcc,
- 0x017eb602,
- 0xf9272084,
- 0x380edf38,
- 0xdf380cdf,
- 0x08df380a,
- 0x607ece39,
- 0xed30ffcc,
- 0x2800cc04,
- 0x08dc06ed,
- 0x0adc00ed,
- 0xcc5f97bd,
- 0x06ed2900,
- 0x97bd04a6,
- 0x9a00ec68,
- 0xed0dda0c,
- 0x9a02ec00,
- 0xbd0fda0e,
- 0xce395f97,
+ 0xdd6280cc,
+ 0xffffcc0a,
+ 0xffcc0cdd,
+ 0xbd0eddfe,
+ 0x00cc35a4,
+ 0xcc0cdd00,
+ 0x0edd0008,
+ 0x80cc498d,
+ 0xcc0add63,
+ 0x0cddfefe,
+ 0xddff7fcc,
+ 0xcc6a8d0e,
+ 0x08dd2001,
+ 0xdd5044cc,
+ 0x0203cc0a,
+ 0xa4bd0cdd,
+ 0xb7df8667,
+ 0x7ece017e,
+ 0x02ffcc60,
+ 0xa5cc04ed,
+ 0xb602ed04,
+ 0x2084017e,
+ 0xdf38f927,
+ 0x0cdf380e,
+ 0x380adf38,
+ 0xce3908df,
0xffcc607e,
0xcc04ed30,
0x06ed2800,
0x00ed08dc,
- 0x97bd0adc,
- 0x2900cc5f,
+ 0x9ebd0adc,
+ 0x2900cc83,
0x04a606ed,
- 0xec6897bd,
- 0xd40c9400,
+ 0xec8c9ebd,
+ 0xda0c9a00,
0xec00ed0d,
- 0xd40e9402,
- 0x5f97bd0f,
+ 0xda0e9a02,
+ 0x839ebd0f,
0x607ece39,
- 0x607ece18,
- 0x3a180dd6,
0xed30ffcc,
0x2800cc04,
0x08dc06ed,
0x0adc00ed,
- 0xcc5f97bd,
+ 0xcc839ebd,
0x06ed2900,
- 0x97bd04a6,
- 0x00e61868,
- 0xf4260cd4,
- 0x39064f39,
- 0xfc203e0e,
- 0x28202001,
- 0x00000000,
- 0x20202001,
- 0x00000000,
- 0x24202001,
- 0x00000000,
- 0x2c202001,
- 0x00000000,
- 0x28000008,
+ 0x9ebd04a6,
+ 0x9400ec8c,
+ 0xed0dd40c,
+ 0x9402ec00,
+ 0xbd0fd40e,
+ 0xce39839e,
+ 0xce18607e,
+ 0x0dd6607e,
+ 0xffcc3a18,
+ 0xcc04ed30,
+ 0x06ed2800,
+ 0x00ed08dc,
+ 0x9ebd0adc,
+ 0x2900cc83,
+ 0x04a606ed,
+ 0x188c9ebd,
+ 0x0cd400e6,
+ 0x5339f426,
+ 0x43538f43,
+ 0x01268f08,
+ 0x064f3908,
+ 0x203e0e39,
+ 0x202001fc,
+ 0x00000028,
+ 0x20200100,
+ 0x00000020,
+ 0x20200100,
+ 0x00000024,
+ 0x20200100,
+ 0x0000002c,
+ 0x00000800,
+ 0xff300028,
+ 0x2901c004,
0x04ff3000,
- 0x002901c0,
+ 0x002800c0,
0xc004ff30,
- 0x30002800,
- 0x01c004ff,
- 0xff300029,
- 0x2800c004,
+ 0x30002901,
+ 0x00c004ff,
+ 0xff300028,
+ 0x2901c004,
0x04ff3000,
- 0x002901c0,
+ 0x002800c0,
0xc004ff30,
- 0x30002800,
- 0x01c004ff,
- 0xff300029,
- 0x0800c004,
- 0x00280000,
+ 0x30002901,
+ 0x00c004ff,
+ 0x28000008,
+ 0x04ff3000,
+ 0x002909c0,
0xc004ff30,
- 0x30002909,
+ 0x30002809,
0x09c004ff,
- 0xff300028,
- 0x2909c004,
+ 0xff300029,
+ 0x2809c004,
0x04ff3000,
- 0x002809c0,
+ 0x002909c0,
0xc004ff30,
- 0x30002909,
+ 0x30002809,
0x09c004ff,
- 0xff300028,
- 0x2909c004,
- 0x04ff3000,
- 0x000001c0
+ 0xff300029,
+ 0x0001c004
};
UINT32 DataBlock1[] = {
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x96d53b90,
- 0x3b90aed5,
- 0x04900490,
- 0x04900490
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x3f903f90,
+ 0x96d53f90,
+ 0x3f90aed5,
+ 0x08900890,
+ 0x08900890
};
SMU_FIRMWARE_BLOCK FmBlockArray[] = {
{
0x9000,
- 0x377,
+ 0x550,
&DataBlock0[0]
},
{
SMU_FIRMWARE_HEADER Fm = {
{
- 0x1, 0x200
+ 0x1, 0x601
},
2,
&FmBlockArray[0]
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $
+ * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $
*
*/
/*
POWER_GATE_DATA Uvd; ///< Uvd Power gating Data
} NB_POWERGATE_CONFIG;
+VOID
+NbFmNbClockGating (
+ IN OUT VOID *NbClkGatingCtrl,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
VOID
NbFmClumpUnitID (
IN PCI_ADDR NbPciAddress,
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 48498 $ @e \$Date: 2011-03-09 12:44:53 -0700 (Wed, 09 Mar 2011) $
*
*/
/*
);
for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) {
FUSE_REGISTER_ENTRY RegisterEntry;
+ UINT8 *FuseArrayPtr;
+ UINT32 FuseArrauValue;
RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex];
- *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) &
- ((1 << RegisterEntry.FieldWidth) - 1));
+ FuseArrayPtr = (UINT8*) PpFuseArray + RegisterEntry.FuseOffset;
+ FuseArrauValue = (FuseValue >> RegisterEntry.FieldOffset) & ((1 << RegisterEntry.FieldWidth) - 1);
+ if (RegisterEntry.FieldWidth > 16) {
+ *((UINT32 *) FuseArrayPtr) = FuseArrauValue;
+ } else if (RegisterEntry.FieldWidth > 8) {
+ *((UINT16 *) FuseArrayPtr) = (UINT16) FuseArrauValue;
+ } else {
+ *((UINT8 *) FuseArrayPtr) = (UINT8) FuseArrauValue;
+ }
}
}
}
FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100;
if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) {
IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n");
+ IDS_HDT_CONSOLE (NB_MISC, " Actual main Freq %d \n", EffectiveMainPllFreq10KHz);
+ IDS_HDT_CONSOLE (NB_MISC, " Fused main Freq %d \n", FusedMainPllFreq10KHz);
for (Index = 0; Index < 5; Index++) {
if (PpFuseArray->SclkDpmDid[Index] != 0) {
TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz);
(PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0
);
}
- for (Index = 0; Index < 5; Index++) {
+ for (Index = 0; Index < 6; Index++) {
IDS_HDT_CONSOLE (
NB_MISC,
" SCLK DID[%d] - 0x%02x (%dMHz)\n",
PpFuseArray->SclkDpmDid[Index],
(PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0
);
+ IDS_HDT_CONSOLE (
+ NB_MISC,
+ " SCLK TDP[%d] - 0x%x \n",
+ Index,
+ PpFuseArray->SclkDpmTdpLimit[Index]
+ );
IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]);
}
for (Index = 0; Index < 6; Index++) {
}
IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid);
IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId);
+ IDS_HDT_CONSOLE (NB_MISC, " GpuBoostCap - %x\n", PpFuseArray->GpuBoostCap);
+ IDS_HDT_CONSOLE (NB_MISC, " SclkDpmBoostMargin - %x\n", PpFuseArray->SclkDpmBoostMargin);
+ IDS_HDT_CONSOLE (NB_MISC, " SclkDpmThrottleMargin - %x\n", PpFuseArray->SclkDpmThrottleMargin);
+ IDS_HDT_CONSOLE (NB_MISC, " SclkDpmTdpLimitPG - %x\n", PpFuseArray->SclkDpmTdpLimitPG);
+ IDS_HDT_CONSOLE (
+ NB_MISC, " SclkThermDid - %x(%dMHz)\n",
+ PpFuseArray->SclkThermDid,
+ (PpFuseArray->SclkThermDid != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkThermDid, EffectiveMainPllFreq10KHz) / 100) : 0
+ );
IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n");
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 41506 $ @e \$Date: 2010-11-05 22:31:30 +0800 (Fri, 05 Nov 2010) $
+ * @e \$Revision: 48955 $ @e \$Date: 2011-03-14 18:31:17 -0600 (Mon, 14 Mar 2011) $
*
*/
/*
#include "GfxLib.h"
#include "NbSmuLib.h"
#include "NbConfigData.h"
+#include "NbInit.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_NB_NBINIT_FILECODE
},
{
D0F0x4C_ADDRESS,
- ~(0x3ull << D0F0x4C_CfgRdTime_OFFSET),
+ ~(UINT32)(0x3 << D0F0x4C_CfgRdTime_OFFSET),
0x2 << D0F0x4C_CfgRdTime_OFFSET
},
{
D0F0x84_ADDRESS,
- ~(0x1ull << D0F0x84_Ev6Mode_OFFSET),
+ ~(UINT32)(0x1 << D0F0x84_Ev6Mode_OFFSET),
0x1 << D0F0x84_Ev6Mode_OFFSET
}
};
CONST NB_REGISTER_ENTRY NbMiscInitTable [] = {
{
D0F0x64_x46_ADDRESS,
- ~(0x3ull << D0F0x64_x46_P2PMode_OFFSET),
+ ~(UINT32)(0x3 << D0F0x64_x46_P2PMode_OFFSET),
1 << D0F0x64_x46_Msi64bitEn_OFFSET
}
};
},
{
D0F0x98_x08_ADDRESS,
- ~(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET),
+ ~(UINT32)(0xff << D0F0x98_x08_NpWrrLenC_OFFSET),
1 << D0F0x98_x08_NpWrrLenC_OFFSET
},
{
D0F0x98_x09_ADDRESS,
- ~(0xffull << D0F0x98_x09_PWrrLenD_OFFSET),
+ ~(UINT32)(0xff << D0F0x98_x09_PWrrLenD_OFFSET),
1 << D0F0x98_x09_PWrrLenD_OFFSET
},
{
{
UINTN Index;
FCRxFF30_0398_STRUCT FCRxFF30_0398;
+ UINT32 Value;
+
// Init NBCONFIG
for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
GnbLibPciRMW (
NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader);
}
+ Value = 0;
+ for (Index = 0x8400; Index <= 0x85AC; Index = Index + 4) {
+ NbSmuRcuRegisterWrite (
+ (UINT16) Index,
+ &Value,
+ 1,
+ FALSE,
+ Gnb->StdHeader
+ );
+ }
+
+ NbSmuRcuRegisterWrite (
+ 0x9000,
+ &Value,
+ 1,
+ FALSE,
+ Gnb->StdHeader
+ );
+
+ NbSmuRcuRegisterWrite (
+ 0x9004,
+ &Value,
+ 1,
+ FALSE,
+ Gnb->StdHeader
+ );
+
return AGESA_SUCCESS;
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 47490 $ @e \$Date: 2011-02-22 08:34:28 -0700 (Tue, 22 Feb 2011) $
*
*/
/*
#include "amdlib.h"
#include "Ids.h"
#include "Gnb.h"
+#include "GnbFuseTable.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include "NbConfigData.h"
#include "NbSmuLib.h"
+#include "NbFamilyServices.h"
#include "NbPowerMgmt.h"
#include "OptionGnb.h"
#include "GfxLib.h"
//FCRxFF30_01F5[CgDcCgttDispclkOverride]
NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);
- FCRxFF30_01F5.Field.CgDcCgttDispClkOverride = 0;
+ FCRxFF30_01F5.Field.CgDcCgttDispclkOverride = 0;
NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader);
}
NbClkGatingCtrl.Dce_Sclk_Gating = TRUE;
NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE;
+ NbFmNbClockGating (&NbClkGatingCtrl, Gnb->StdHeader);
+
IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader);
#define _NBPOWERMGMT_H_
-AGESA_STATUS
-NbInitPowerManagement (
- IN GNB_PLATFORM_CONFIG *Gnb
- );
-
///Control structure for clock gating feature
typedef struct {
BOOLEAN Smu_Sclk_Gating; ///<Control Smu SClk gating 1 Enable 0 Disable
BOOLEAN Dce_Dispclk_Gating; ///<Control DCE dispaly gating 1 Enable 0 Disable
} NB_CLK_GATING_CTRL;
+AGESA_STATUS
+NbInitPowerManagement (
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitSmuClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitOrbClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitIocClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitBifClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitGmcClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitDceSclkClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
+VOID
+NbInitDceDisplayClockGating (
+ IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
+ IN GNB_PLATFORM_CONFIG *Gnb
+ );
+
#endif
*----------------------------------------------------------------------------------------
*/
-
/*----------------------------------------------------------------------------------------*/
/**
* SMU indirect register read
IN AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+NbSmuIndirectWriteEx (
+ IN UINT8 Address,
+ IN ACCESS_WIDTH Width,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
VOID
NbSmuIndirectWrite (
IN UINT8 Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
+VOID
+NbSmuIndirectWriteS3Script (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINT16 ContextLength,
+ IN VOID* Context
+ );
+
VOID
NbSmuRcuRegisterWrite (
IN UINT16 Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
+UINT32
+NbSmuReadEfuseField (
+ IN UINT8 Chain,
+ IN UINT16 Offset,
+ IN UINT8 Length,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
VOID
NbSmuFirmwareDownload (
IN SMU_FIRMWARE_HEADER *Firmware,
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 46946 $ @e \$Date: 2011-02-11 11:53:30 -0700 (Fri, 11 Feb 2011) $
*
*/
/*
*/
#include "AGESA.h"
#include "Ids.h"
+#include "heapManager.h"
+#include "Gnb.h"
+//#include "GnbPcieFamServices.h"
+#include "GnbFuseTable.h"
+#include "GnbRegistersON.h"
+#include "cpuLateInit.h"
+#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include "F14PcieAlibSsdt.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+PcieFmAlibBuildAcpiTable (
+ IN VOID *AlibSsdtPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Build ALIB ACPI table
+ *
+ *
+ *
+ * @param[in,out] AlibSsdtPtr Pointer to ALIB SSDT table
+ * @param[in] StdHeader Standard Configuration Header
+ * @retval AGESA_SUCCESS
+ * @retval AGESA_FATAL
+ */
+
+AGESA_STATUS
+PcieFmAlibBuildAcpiTable (
+ IN VOID *AlibSsdtPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ AGESA_STATUS AgesaStatus;
+ D18F4x15C_STRUCT D18F4x15C;
+ PP_FUSE_ARRAY *PpFuseArray;
+ UINT32 AmlObjName;
+ VOID *AmlObjPtr;
+
+ IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n");
+ AgesaStatus = AGESA_SUCCESS;
+ // Set voltage configuration
+ PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
+ ASSERT (PpFuseArray != NULL);
+ if (PpFuseArray != NULL) {
+ GnbLibPciRead (
+ MAKE_SBDFO (0, 0, 0x18, 0x4, D18F4x15C_ADDRESS),
+ AccessWidth32,
+ &D18F4x15C.Value,
+ StdHeader
+ );
+ if (D18F4x15C.Field.BoostSrc != 0 || PpFuseArray->GpuBoostCap != 0) {
+// AmlObjName = 'B0DA';
+ AmlObjName = Int32FromChar ('B', '0', 'D', 'A');
+ AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
+ ASSERT (AmlObjPtr != NULL);
+ if (AmlObjPtr != NULL) {
+ *(UINT8*)((UINT8*) AmlObjPtr + 5) = 1;
+ } else {
+ AgesaStatus = AGESA_FATAL;
+ }
+ }
+ } else {
+ AgesaStatus = AGESA_FATAL;
+ }
+
+ IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus);
+ return AgesaStatus;
+}
}
}
+#ifdef PCIE_PHY_LANE_POWER_GATE_SUPPORT
/*----------------------------------------------------------------------------------------*/
/**
* Power gate PCIe phy lanes (hotplug support)
Method (procPcieLanePowerControl, 3, NotSerialized) {
// stub function
}
-
+#endif
/*----------------------------------------------------------------------------------------*/
/**
- * Read RCU register
+ * Adjust PLL settings stub
*
* Arg0 - 1 - GEN1 2 - GEN2
*
Method (procPcieAdjustPll, 1, NotSerialized) {
//stub function
}
-
+ Name (AD0B, 0)
+ /*----------------------------------------------------------------------------------------*/
+ /**
+ * APM/PDM stub
+ *
+ * Arg0 - 0 (AC) 1 (DC)
+ *
+ */
+ Method (procApmPdmActivate, 1, NotSerialized) {
+ if (LEqual (AD0B, 1)) {
+ Store (Or(ShiftLeft (0x18, 3), 4), Local1)
+ Store (procPciDwordRead (Local1, 0x15C), Local2)
+ if (LEqual (Arg0, DEF_PSPP_STATE_AC)) {
+ Or (Local2, 0x01, Local2)
+ } else {
+ And (Local2, 0xfffffffc, Local2)
+ }
+ procPciDwordWrite (Local1, 0x15C, Local2)
+ }
+ }
} //End of Scope(\_SB)
} //End of DefinitionBlock
*
*/
/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of Advanced Micro Devices, Inc. nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+****************************************************************************
+*
+*/
#ifndef _F14PCIEALIBSSDT_H_
#define _F14PCIEALIBSSDT_H_
UINT8 AlibSsdt[] = {
- 0x53, 0x53, 0x44, 0x54, 0xFA, 0x12, 0x00, 0x00,
- 0x02, 0xC9, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
+ 0x53, 0x53, 0x44, 0x54, 0x8E, 0x16, 0x00, 0x00,
+ 0x02, 0x11, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
- 0x00, 0x00, 0x00, 0x04, 0x10, 0x85, 0x2D, 0x01,
+ 0x00, 0x00, 0x00, 0x04, 0x10, 0x89, 0x66, 0x01,
0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30,
0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30,
0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41,
- 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x31, 0x08,
- 0x41, 0x44, 0x30, 0x37, 0x12, 0x45, 0x06, 0x07,
+ 0x44, 0x30, 0x31, 0x41, 0x30, 0x38, 0x36, 0x08,
+ 0x41, 0x44, 0x30, 0x37, 0x12, 0x43, 0x07, 0x08,
0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D,
0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x06, 0x41, 0x44, 0x30, 0x37, 0x41,
- 0x30, 0x39, 0x32, 0x14, 0x41, 0x05, 0x41, 0x4C,
+ 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, 0x30, 0x38,
+ 0x37, 0x08, 0x41, 0x30, 0x38, 0x38, 0x11, 0x04,
+ 0x0B, 0x00, 0x01, 0x14, 0x41, 0x05, 0x41, 0x4C,
0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A,
- 0x01, 0xA4, 0x41, 0x30, 0x31, 0x38, 0x69, 0xA0,
+ 0x01, 0xA4, 0x41, 0x30, 0x32, 0x36, 0x69, 0xA0,
0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30,
- 0x32, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A,
- 0x03, 0xA4, 0x41, 0x30, 0x33, 0x32, 0x69, 0xA0,
+ 0x33, 0x30, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A,
+ 0x03, 0xA4, 0x41, 0x30, 0x34, 0x31, 0x69, 0xA0,
0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30,
- 0x36, 0x33, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A,
- 0x05, 0xA4, 0x41, 0x30, 0x39, 0x33, 0xA0, 0x0B,
+ 0x36, 0x36, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A,
+ 0x05, 0xA4, 0x41, 0x30, 0x38, 0x39, 0xA0, 0x0B,
0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x36,
- 0x36, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41,
- 0x30, 0x39, 0x33, 0x08, 0xA4, 0x0A, 0x00, 0x14,
- 0x31, 0x41, 0x30, 0x33, 0x31, 0x02, 0x72, 0x41,
- 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, 0x0C, 0x00,
+ 0x39, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41,
+ 0x30, 0x38, 0x39, 0x08, 0xA4, 0x0A, 0x00, 0x14,
+ 0x31, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x72, 0x41,
+ 0x30, 0x38, 0x36, 0x79, 0x68, 0x0A, 0x0C, 0x00,
0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41,
- 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B,
- 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, 0x03, 0x41,
- 0x30, 0x39, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x39,
- 0x35, 0x14, 0x32, 0x41, 0x30, 0x35, 0x39, 0x03,
- 0x72, 0x41, 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A,
+ 0x30, 0x39, 0x30, 0x00, 0x60, 0x0A, 0x04, 0x5B,
+ 0x81, 0x0B, 0x41, 0x30, 0x39, 0x30, 0x03, 0x41,
+ 0x30, 0x39, 0x31, 0x20, 0xA4, 0x41, 0x30, 0x39,
+ 0x31, 0x14, 0x32, 0x41, 0x30, 0x30, 0x38, 0x0B,
+ 0x72, 0x41, 0x30, 0x38, 0x36, 0x79, 0x68, 0x0A,
0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B,
- 0x80, 0x41, 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A,
- 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34,
- 0x03, 0x41, 0x30, 0x39, 0x35, 0x20, 0x70, 0x6A,
- 0x41, 0x30, 0x39, 0x35, 0x14, 0x1C, 0x41, 0x30,
- 0x35, 0x35, 0x04, 0x70, 0x41, 0x30, 0x33, 0x31,
+ 0x80, 0x41, 0x30, 0x39, 0x30, 0x00, 0x60, 0x0A,
+ 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x30,
+ 0x03, 0x41, 0x30, 0x39, 0x31, 0x20, 0x70, 0x6A,
+ 0x41, 0x30, 0x39, 0x31, 0x14, 0x1C, 0x41, 0x30,
+ 0x35, 0x32, 0x0C, 0x70, 0x41, 0x30, 0x30, 0x37,
0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00,
- 0x6B, 0x60, 0x41, 0x30, 0x35, 0x39, 0x68, 0x69,
- 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x36, 0x00,
- 0x14, 0x32, 0x41, 0x30, 0x35, 0x38, 0x02, 0x5B,
- 0x23, 0x41, 0x30, 0x39, 0x36, 0xFF, 0xFF, 0x70,
+ 0x6B, 0x60, 0x41, 0x30, 0x30, 0x38, 0x68, 0x69,
+ 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x32, 0x00,
+ 0x14, 0x32, 0x41, 0x30, 0x35, 0x33, 0x02, 0x5B,
+ 0x23, 0x41, 0x30, 0x39, 0x32, 0xFF, 0xFF, 0x70,
0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03,
- 0x00, 0x60, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A,
- 0xE0, 0x69, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60,
+ 0x00, 0x60, 0x41, 0x30, 0x30, 0x38, 0x60, 0x0A,
+ 0xE0, 0x69, 0x70, 0x41, 0x30, 0x30, 0x37, 0x60,
0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39,
- 0x36, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39,
- 0x37, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x36,
+ 0x32, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39,
+ 0x33, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x32,
0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02,
- 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35,
- 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x35,
- 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41,
- 0x30, 0x39, 0x36, 0x14, 0x1C, 0x41, 0x30, 0x35,
- 0x34, 0x04, 0x70, 0x41, 0x30, 0x35, 0x38, 0x68,
+ 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x30,
+ 0x38, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x30,
+ 0x38, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41,
+ 0x30, 0x39, 0x32, 0x14, 0x1C, 0x41, 0x30, 0x35,
+ 0x30, 0x04, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68,
0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B,
- 0x60, 0x41, 0x30, 0x39, 0x37, 0x68, 0x69, 0x60,
- 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, 0x14,
- 0x29, 0x41, 0x30, 0x36, 0x31, 0x03, 0x5B, 0x23,
- 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x41, 0x30,
- 0x35, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30,
- 0x33, 0x31, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00,
- 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, 0xA4,
- 0x60, 0x14, 0x26, 0x41, 0x30, 0x36, 0x32, 0x04,
- 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF,
- 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, 0x6A, 0x41,
- 0x30, 0x35, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04,
- 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38,
- 0x14, 0x1E, 0x41, 0x30, 0x35, 0x33, 0x05, 0x70,
- 0x41, 0x30, 0x36, 0x31, 0x68, 0x69, 0x6A, 0x60,
+ 0x60, 0x41, 0x30, 0x39, 0x33, 0x68, 0x69, 0x60,
+ 0x5B, 0x01, 0x41, 0x30, 0x39, 0x34, 0x00, 0x14,
+ 0x29, 0x41, 0x30, 0x34, 0x32, 0x03, 0x5B, 0x23,
+ 0x41, 0x30, 0x39, 0x34, 0xFF, 0xFF, 0x41, 0x30,
+ 0x30, 0x38, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30,
+ 0x30, 0x37, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00,
+ 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x34, 0xA4,
+ 0x60, 0x14, 0x26, 0x41, 0x30, 0x34, 0x33, 0x04,
+ 0x5B, 0x23, 0x41, 0x30, 0x39, 0x34, 0xFF, 0xFF,
+ 0x41, 0x30, 0x30, 0x38, 0x68, 0x69, 0x6A, 0x41,
+ 0x30, 0x30, 0x38, 0x68, 0x72, 0x69, 0x0A, 0x04,
+ 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x34,
+ 0x14, 0x1E, 0x41, 0x30, 0x32, 0x38, 0x05, 0x70,
+ 0x41, 0x30, 0x34, 0x32, 0x68, 0x69, 0x6A, 0x60,
0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41,
- 0x30, 0x36, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14,
+ 0x30, 0x34, 0x33, 0x68, 0x69, 0x6A, 0x60, 0x14,
0x0F, 0x41, 0x30, 0x37, 0x33, 0x01, 0xA4, 0x83,
- 0x88, 0x41, 0x30, 0x39, 0x32, 0x68, 0x00, 0x14,
- 0x42, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, 0x70,
+ 0x88, 0x41, 0x30, 0x38, 0x37, 0x68, 0x00, 0x14,
+ 0x42, 0x05, 0x41, 0x30, 0x35, 0x39, 0x02, 0x70,
0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30,
- 0x33, 0x31, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF,
+ 0x30, 0x37, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF,
0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01,
0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70,
- 0x7B, 0x41, 0x30, 0x33, 0x31, 0x68, 0x61, 0x0A,
- 0xFF, 0x00, 0x61, 0xA0, 0x1C, 0x92, 0x93, 0x61,
- 0x0A, 0x00, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30,
- 0x33, 0x31, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69,
+ 0x7B, 0x41, 0x30, 0x30, 0x37, 0x68, 0x61, 0x0A,
+ 0xFF, 0x00, 0x61, 0xA0, 0x06, 0x93, 0x61, 0x0A,
+ 0x00, 0xA5, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30,
+ 0x30, 0x37, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69,
0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61,
0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x35,
- 0x37, 0x02, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F,
+ 0x38, 0x0A, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F,
0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81,
0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D,
0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08,
0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF,
0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42,
0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38,
- 0x36, 0x01, 0x70, 0x41, 0x30, 0x36, 0x31, 0x0A,
+ 0x31, 0x01, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A,
0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68,
0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE,
0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00,
0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF,
0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10,
- 0x00, 0x60, 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00,
+ 0x00, 0x60, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00,
0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30,
- 0x36, 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE,
+ 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE,
0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30,
- 0x38, 0x37, 0x03, 0x70, 0x41, 0x30, 0x36, 0x31,
+ 0x38, 0x32, 0x03, 0x70, 0x41, 0x30, 0x34, 0x32,
0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70,
0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D,
0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00,
0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00,
0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00,
0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02,
- 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x36,
- 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60,
+ 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x34,
+ 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60,
0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70,
0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B,
0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B,
0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00,
0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00,
0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60,
- 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x0A, 0x60,
+ 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A, 0x60,
0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30,
- 0x38, 0x38, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03,
- 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x37,
+ 0x38, 0x33, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03,
+ 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x32,
0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90,
0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B,
- 0x41, 0x30, 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x02,
+ 0x41, 0x30, 0x38, 0x31, 0x0A, 0x03, 0x0A, 0x02,
0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A,
0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30,
- 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A,
- 0x04, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x03, 0x0A,
- 0x00, 0x0A, 0x00, 0x14, 0x18, 0x41, 0x30, 0x30,
- 0x34, 0x02, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x0B,
- 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x37, 0x0A,
+ 0x38, 0x31, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A,
+ 0x04, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x03, 0x0A,
+ 0x00, 0x0A, 0x01, 0x14, 0x18, 0x41, 0x30, 0x30,
+ 0x34, 0x02, 0x41, 0x30, 0x38, 0x32, 0x0A, 0x0B,
+ 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x32, 0x0A,
0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30,
- 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x37, 0x0A,
+ 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x32, 0x0A,
0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38,
- 0x36, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49,
- 0x07, 0x41, 0x30, 0x38, 0x39, 0x01, 0x70, 0x7D,
+ 0x31, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49,
+ 0x07, 0x41, 0x30, 0x38, 0x34, 0x01, 0x70, 0x7D,
0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50,
0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68,
0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04,
0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08,
0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A,
0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x38,
- 0x38, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93,
+ 0x33, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93,
0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE,
- 0x41, 0x30, 0x38, 0x38, 0x0A, 0x0B, 0x0A, 0x03,
+ 0x41, 0x30, 0x38, 0x33, 0x0A, 0x0B, 0x0A, 0x03,
0xA4, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x50, 0x86,
- 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x30, 0x02,
+ 0x14, 0x44, 0x06, 0x41, 0x30, 0x38, 0x35, 0x02,
0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C,
0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D,
0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00,
0x34, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x30,
0x34, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x30,
0x34, 0x0B, 0x50, 0x86, 0x69, 0x41, 0x30, 0x38,
- 0x38, 0x0A, 0x0B, 0x0A, 0x03, 0x08, 0x41, 0x44,
+ 0x33, 0x0A, 0x0B, 0x0A, 0x03, 0x08, 0x41, 0x44,
0x30, 0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x32, 0x41, 0x30, 0x30, 0x37, 0x08, 0x41, 0x44,
+ 0x32, 0x41, 0x30, 0x30, 0x39, 0x08, 0x41, 0x44,
0x30, 0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x33, 0x41, 0x30, 0x30, 0x38, 0x08, 0x41, 0x44,
+ 0x33, 0x41, 0x30, 0x31, 0x30, 0x08, 0x41, 0x44,
0x30, 0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x34, 0x41, 0x30, 0x30, 0x39, 0x08, 0x41, 0x44,
+ 0x34, 0x41, 0x30, 0x31, 0x31, 0x08, 0x41, 0x44,
0x30, 0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x35, 0x41, 0x30, 0x31, 0x30, 0x08, 0x41, 0x44,
- 0x30, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00, 0x0A,
+ 0x35, 0x41, 0x30, 0x31, 0x32, 0x08, 0x41, 0x44,
+ 0x30, 0x36, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A,
0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
- 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x36,
- 0x41, 0x30, 0x31, 0x31, 0x08, 0x41, 0x30, 0x31,
- 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x33,
- 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x34, 0x12,
- 0x10, 0x07, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44,
+ 0x30, 0x36, 0x41, 0x30, 0x31, 0x33, 0x08, 0x41,
+ 0x44, 0x30, 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00,
0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
- 0x08, 0x41, 0x30, 0x31, 0x35, 0x12, 0x10, 0x07,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41,
- 0x30, 0x31, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41,
+ 0x44, 0x30, 0x38, 0x41, 0x30, 0x31, 0x34, 0x08,
+ 0x41, 0x30, 0x31, 0x35, 0x0A, 0x00, 0x08, 0x41,
+ 0x30, 0x31, 0x36, 0x0A, 0x00, 0x08, 0x41, 0x30,
+ 0x31, 0x37, 0x0A, 0x01, 0x08, 0x41, 0x30, 0x31,
+ 0x38, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31,
- 0x37, 0x12, 0x10, 0x07, 0x0A, 0x02, 0x0A, 0x02,
- 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02,
- 0x0A, 0x02, 0x14, 0x42, 0x06, 0x41, 0x30, 0x31,
- 0x38, 0x09, 0x8C, 0x68, 0x0A, 0x02, 0x41, 0x30,
- 0x31, 0x39, 0xA0, 0x0D, 0x93, 0x41, 0x30, 0x31,
- 0x39, 0x41, 0x30, 0x31, 0x33, 0xA4, 0x0A, 0x00,
- 0x70, 0x41, 0x30, 0x31, 0x39, 0x41, 0x30, 0x31,
- 0x33, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x30, 0x37,
+ 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x32,
+ 0x30, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x44, 0x30,
+ 0x39, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
+ 0x39, 0x41, 0x30, 0x32, 0x31, 0x08, 0x41, 0x30,
+ 0x32, 0x32, 0x12, 0x12, 0x08, 0x0A, 0x01, 0x0A,
+ 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x0A,
+ 0x01, 0x0A, 0x01, 0x0A, 0x01, 0x08, 0x41, 0x30,
+ 0x32, 0x33, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A,
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30,
+ 0x32, 0x35, 0x0A, 0x00, 0x14, 0x48, 0x09, 0x41,
+ 0x30, 0x32, 0x36, 0x09, 0x70, 0x83, 0x88, 0x68,
+ 0x0A, 0x02, 0x00, 0x61, 0x70, 0x41, 0x30, 0x32,
+ 0x37, 0x60, 0x70, 0x61, 0x41, 0x30, 0x31, 0x36,
+ 0x7D, 0x79, 0x0A, 0x01, 0x0A, 0x05, 0x00, 0x79,
+ 0x0A, 0x01, 0x0A, 0x06, 0x00, 0x62, 0x7D, 0x79,
+ 0x41, 0x30, 0x31, 0x36, 0x0A, 0x05, 0x00, 0x79,
+ 0x41, 0x30, 0x31, 0x37, 0x0A, 0x06, 0x00, 0x63,
+ 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A, 0x60,
+ 0x0A, 0xF4, 0x80, 0x62, 0x00, 0x7B, 0x62, 0x63,
+ 0x00, 0xA0, 0x07, 0x93, 0x61, 0x60, 0xA4, 0x0A,
+ 0x00, 0x41, 0x30, 0x30, 0x36, 0x41, 0x30, 0x31,
+ 0x36, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x30, 0x39,
0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01,
- 0x41, 0x30, 0x31, 0x33, 0xA0, 0x15, 0x91, 0x92,
- 0x94, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x01, 0x92,
- 0x95, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x04, 0xA4,
+ 0x41, 0x30, 0x32, 0x37, 0xA0, 0x15, 0x91, 0x92,
+ 0x94, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x01, 0x92,
+ 0x95, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04, 0xA4,
0x0A, 0x00, 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x31,
- 0x32, 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0x41, 0x30,
- 0x32, 0x30, 0xA4, 0x0A, 0x00, 0x14, 0x42, 0x18,
- 0x41, 0x30, 0x32, 0x31, 0x01, 0x08, 0x41, 0x30,
- 0x32, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x32,
- 0x33, 0x0A, 0x00, 0x70, 0x11, 0x04, 0x0B, 0x00,
- 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30,
- 0x32, 0x34, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x32,
- 0x34, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x32,
- 0x35, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x32, 0x35,
- 0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, 0x30,
- 0x37, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x30,
- 0x37, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, 0x93,
- 0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0xA4, 0x67,
- 0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x32, 0x36,
- 0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x37,
- 0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x32, 0x38,
- 0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x32, 0x39,
- 0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x33, 0x30,
- 0x7B, 0x7A, 0x41, 0x30, 0x32, 0x36, 0x0A, 0x08,
- 0x00, 0x0A, 0xFF, 0x41, 0x30, 0x32, 0x32, 0xA2,
- 0x4E, 0x0E, 0x92, 0x94, 0x41, 0x30, 0x32, 0x33,
- 0x41, 0x30, 0x30, 0x31, 0xA0, 0x15, 0x93, 0x83,
- 0x88, 0x41, 0x30, 0x31, 0x31, 0x41, 0x30, 0x32,
- 0x33, 0x00, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x32,
- 0x33, 0x9F, 0x70, 0x41, 0x30, 0x33, 0x31, 0x79,
- 0x72, 0x41, 0x30, 0x32, 0x33, 0x0A, 0x02, 0x00,
- 0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, 0x7A,
- 0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, 0x7B,
- 0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x61,
- 0xA0, 0x14, 0x90, 0x95, 0x41, 0x30, 0x32, 0x32,
- 0x61, 0x94, 0x41, 0x30, 0x32, 0x32, 0x62, 0x75,
- 0x41, 0x30, 0x32, 0x33, 0x9F, 0xA0, 0x1E, 0x93,
- 0x83, 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30,
- 0x32, 0x33, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30,
- 0x32, 0x36, 0x88, 0x41, 0x30, 0x31, 0x34, 0x41,
- 0x30, 0x32, 0x33, 0x00, 0xA1, 0x16, 0xA0, 0x14,
- 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, 0x34,
- 0x41, 0x30, 0x32, 0x33, 0x00, 0x41, 0x30, 0x32,
- 0x36, 0xA4, 0x67, 0xA0, 0x15, 0x93, 0x41, 0x30,
- 0x33, 0x30, 0x0A, 0x00, 0x70, 0x0A, 0x00, 0x88,
- 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, 0x32, 0x33,
- 0x00, 0xA1, 0x37, 0xA0, 0x24, 0x93, 0x7B, 0x41,
- 0x30, 0x32, 0x37, 0x41, 0x30, 0x32, 0x38, 0x00,
+ 0x35, 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0x41, 0x30,
+ 0x32, 0x39, 0xA4, 0x0A, 0x00, 0x14, 0x24, 0x41,
+ 0x30, 0x33, 0x30, 0x01, 0x70, 0x41, 0x30, 0x33,
+ 0x31, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A,
+ 0x02, 0x00, 0x60, 0xA0, 0x08, 0x92, 0x93, 0x60,
+ 0x0A, 0x02, 0xA4, 0x67, 0x41, 0x30, 0x32, 0x39,
+ 0xA4, 0x67, 0x14, 0x4E, 0x1B, 0x41, 0x30, 0x33,
+ 0x31, 0x01, 0x08, 0x41, 0x30, 0x33, 0x32, 0x0A,
+ 0x00, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35,
+ 0x70, 0x11, 0x03, 0x0A, 0x0A, 0x67, 0x8B, 0x67,
+ 0x0A, 0x00, 0x41, 0x30, 0x33, 0x33, 0x70, 0x0A,
+ 0x03, 0x41, 0x30, 0x33, 0x33, 0x8C, 0x67, 0x0A,
+ 0x02, 0x41, 0x30, 0x33, 0x34, 0x70, 0x0A, 0x01,
+ 0x41, 0x30, 0x33, 0x34, 0xA0, 0x14, 0x91, 0x92,
+ 0x94, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x01, 0x92,
+ 0x95, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04, 0xA4,
+ 0x67, 0xA0, 0x0A, 0x93, 0x41, 0x30, 0x31, 0x35,
+ 0x0A, 0x00, 0xA4, 0x67, 0x8B, 0x68, 0x0A, 0x02,
+ 0x41, 0x30, 0x33, 0x35, 0x8B, 0x68, 0x0A, 0x04,
+ 0x41, 0x30, 0x33, 0x36, 0x8B, 0x68, 0x0A, 0x06,
+ 0x41, 0x30, 0x33, 0x37, 0x8C, 0x68, 0x0A, 0x08,
+ 0x41, 0x30, 0x33, 0x38, 0x8C, 0x68, 0x0A, 0x09,
+ 0x41, 0x30, 0x33, 0x39, 0x7B, 0x7A, 0x41, 0x30,
+ 0x33, 0x35, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x41,
+ 0x30, 0x33, 0x32, 0xA2, 0x47, 0x05, 0x92, 0x94,
+ 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x30, 0x31,
+ 0xA0, 0x45, 0x04, 0x93, 0x41, 0x30, 0x34, 0x30,
+ 0x41, 0x30, 0x32, 0x35, 0x0A, 0x01, 0x70, 0x41,
+ 0x30, 0x30, 0x37, 0x79, 0x72, 0x41, 0x30, 0x32,
+ 0x35, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x0A,
+ 0x18, 0x61, 0x7B, 0x7A, 0x61, 0x0A, 0x10, 0x00,
+ 0x0A, 0xFF, 0x62, 0x7B, 0x7A, 0x61, 0x0A, 0x08,
+ 0x00, 0x0A, 0xFF, 0x61, 0xA0, 0x11, 0x90, 0x92,
+ 0x95, 0x41, 0x30, 0x33, 0x32, 0x61, 0x92, 0x94,
+ 0x41, 0x30, 0x33, 0x32, 0x62, 0xA5, 0x75, 0x41,
+ 0x30, 0x32, 0x35, 0xA0, 0x0C, 0x94, 0x41, 0x30,
+ 0x32, 0x35, 0x41, 0x30, 0x30, 0x31, 0xA4, 0x67,
+ 0xA0, 0x1E, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31,
+ 0x38, 0x41, 0x30, 0x32, 0x35, 0x00, 0x0A, 0x00,
+ 0x70, 0x41, 0x30, 0x33, 0x35, 0x88, 0x41, 0x30,
+ 0x31, 0x38, 0x41, 0x30, 0x32, 0x35, 0x00, 0xA1,
+ 0x16, 0xA0, 0x14, 0x92, 0x93, 0x83, 0x88, 0x41,
+ 0x30, 0x31, 0x38, 0x41, 0x30, 0x32, 0x35, 0x00,
+ 0x41, 0x30, 0x33, 0x35, 0xA4, 0x67, 0x70, 0x0A,
+ 0x00, 0x88, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30,
+ 0x32, 0x35, 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30,
+ 0x33, 0x39, 0x0A, 0x00, 0x70, 0x0A, 0x00, 0x88,
+ 0x41, 0x30, 0x31, 0x38, 0x41, 0x30, 0x32, 0x35,
+ 0x00, 0xA0, 0x15, 0x93, 0x41, 0x30, 0x33, 0x39,
+ 0x0A, 0x01, 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30,
+ 0x32, 0x33, 0x41, 0x30, 0x32, 0x35, 0x00, 0xA0,
+ 0x15, 0x93, 0x41, 0x30, 0x33, 0x39, 0x0A, 0x02,
+ 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30, 0x32, 0x30,
+ 0x41, 0x30, 0x32, 0x35, 0x00, 0xA0, 0x15, 0x93,
+ 0x41, 0x30, 0x33, 0x39, 0x0A, 0x03, 0x70, 0x0A,
+ 0x02, 0x88, 0x41, 0x30, 0x32, 0x30, 0x41, 0x30,
+ 0x32, 0x35, 0x00, 0xA0, 0x24, 0x93, 0x7B, 0x41,
+ 0x30, 0x33, 0x36, 0x41, 0x30, 0x33, 0x37, 0x00,
0x0A, 0x01, 0x70, 0x83, 0x88, 0x41, 0x30, 0x31,
- 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, 0x88, 0x41,
- 0x30, 0x31, 0x35, 0x41, 0x30, 0x32, 0x33, 0x00,
- 0xA1, 0x10, 0x70, 0x41, 0x30, 0x33, 0x30, 0x88,
- 0x41, 0x30, 0x31, 0x35, 0x41, 0x30, 0x32, 0x33,
- 0x00, 0x41, 0x30, 0x32, 0x30, 0x70, 0x0A, 0x02,
- 0x41, 0x30, 0x32, 0x35, 0xA4, 0x67, 0xA4, 0x67,
- 0x14, 0x41, 0x0C, 0x41, 0x30, 0x33, 0x32, 0x09,
- 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B,
- 0x67, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x34, 0x70,
- 0x0A, 0x03, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67,
- 0x0A, 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x68,
- 0x0A, 0x02, 0x41, 0x30, 0x33, 0x33, 0x70, 0x41,
- 0x30, 0x33, 0x33, 0x41, 0x30, 0x31, 0x32, 0xA0,
- 0x12, 0x93, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x04,
- 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, 0x41, 0x30,
- 0x31, 0x33, 0xA0, 0x47, 0x06, 0x90, 0x94, 0x41,
- 0x30, 0x30, 0x37, 0x0A, 0x01, 0x95, 0x41, 0x30,
- 0x30, 0x37, 0x0A, 0x04, 0xA0, 0x16, 0x93, 0x41,
- 0x30, 0x30, 0x37, 0x0A, 0x02, 0x41, 0x30, 0x33,
- 0x34, 0x71, 0x41, 0x30, 0x31, 0x31, 0x71, 0x41,
- 0x30, 0x31, 0x36, 0xA1, 0x0F, 0x41, 0x30, 0x33,
- 0x34, 0x71, 0x41, 0x30, 0x31, 0x37, 0x71, 0x41,
- 0x30, 0x31, 0x36, 0xA0, 0x2A, 0x93, 0x41, 0x30,
- 0x31, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33,
- 0x35, 0x12, 0x0E, 0x06, 0x0A, 0x00, 0x0A, 0x00,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
- 0x41, 0x30, 0x33, 0x34, 0x71, 0x41, 0x30, 0x33,
- 0x35, 0x71, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30,
- 0x32, 0x30, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x32,
- 0x34, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35,
- 0xA4, 0x67, 0x14, 0x4A, 0x13, 0x41, 0x30, 0x32,
- 0x30, 0x08, 0x08, 0x41, 0x30, 0x32, 0x33, 0x0A,
- 0x00, 0x08, 0x41, 0x30, 0x33, 0x36, 0x0A, 0x00,
- 0x08, 0x41, 0x30, 0x33, 0x37, 0x12, 0x10, 0x07,
- 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02,
- 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x70, 0x0A,
- 0x00, 0x41, 0x30, 0x32, 0x33, 0xA2, 0x34, 0x92,
- 0x94, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, 0x30,
- 0x31, 0xA0, 0x23, 0x92, 0x93, 0x83, 0x88, 0x41,
- 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, 0x33, 0x00,
- 0x0A, 0x00, 0x70, 0x41, 0x30, 0x33, 0x38, 0x41,
- 0x30, 0x32, 0x33, 0x88, 0x41, 0x30, 0x33, 0x37,
- 0x41, 0x30, 0x32, 0x33, 0x00, 0x75, 0x41, 0x30,
- 0x32, 0x33, 0xA0, 0x1F, 0x92, 0x93, 0x89, 0x41,
- 0x30, 0x33, 0x37, 0x01, 0x0A, 0x01, 0x00, 0x0A,
- 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x33, 0x34,
- 0x71, 0x41, 0x30, 0x31, 0x37, 0x71, 0x41, 0x30,
- 0x33, 0x37, 0xA0, 0x2B, 0x92, 0x93, 0x89, 0x41,
- 0x30, 0x33, 0x37, 0x01, 0x0A, 0x03, 0x00, 0x0A,
- 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x33, 0x39,
- 0x41, 0x30, 0x30, 0x38, 0x0A, 0x01, 0x41, 0x30,
- 0x30, 0x36, 0x0A, 0x02, 0x41, 0x30, 0x30, 0x32,
- 0x0A, 0x02, 0x41, 0x30, 0x31, 0x33, 0x70, 0x0A,
- 0x00, 0x41, 0x30, 0x32, 0x33, 0xA2, 0x44, 0x05,
- 0x92, 0x94, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30,
- 0x30, 0x31, 0xA0, 0x15, 0x93, 0x83, 0x88, 0x41,
- 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, 0x33, 0x00,
- 0x0A, 0x00, 0x75, 0x41, 0x30, 0x32, 0x33, 0x9F,
- 0x70, 0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x32,
- 0x33, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, 0x33,
- 0x37, 0x41, 0x30, 0x32, 0x33, 0x00, 0x62, 0xA0,
- 0x0A, 0x93, 0x60, 0x62, 0x75, 0x41, 0x30, 0x32,
- 0x33, 0x9F, 0x41, 0x30, 0x34, 0x31, 0x41, 0x30,
- 0x32, 0x33, 0x62, 0x0A, 0x00, 0x75, 0x41, 0x30,
- 0x32, 0x33, 0xA0, 0x2A, 0x93, 0x89, 0x41, 0x30,
- 0x33, 0x37, 0x01, 0x0A, 0x03, 0x00, 0x0A, 0x00,
- 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x30, 0x32, 0x0A,
- 0x01, 0x41, 0x30, 0x31, 0x33, 0x41, 0x30, 0x30,
- 0x36, 0x0A, 0x01, 0x41, 0x30, 0x33, 0x39, 0x41,
- 0x30, 0x30, 0x39, 0x0A, 0x00, 0x14, 0x3A, 0x41,
- 0x30, 0x33, 0x38, 0x01, 0x70, 0x0A, 0x03, 0x60,
- 0xA0, 0x21, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31,
- 0x34, 0x68, 0x00, 0x0A, 0x00, 0xA0, 0x14, 0x91,
- 0x93, 0x41, 0x30, 0x31, 0x33, 0x0A, 0x01, 0x93,
- 0x41, 0x30, 0x30, 0x37, 0x0A, 0x03, 0x70, 0x0A,
- 0x02, 0x60, 0xA1, 0x0B, 0x70, 0x83, 0x88, 0x41,
- 0x30, 0x31, 0x35, 0x68, 0x00, 0x60, 0xA4, 0x60,
- 0x14, 0x0F, 0x41, 0x30, 0x34, 0x30, 0x01, 0xA4,
- 0x83, 0x88, 0x41, 0x30, 0x31, 0x36, 0x68, 0x00,
- 0x14, 0x4C, 0x2E, 0x41, 0x30, 0x34, 0x31, 0x03,
- 0xA0, 0x44, 0x2E, 0x91, 0x93, 0x69, 0x0A, 0x02,
- 0x93, 0x69, 0x0A, 0x03, 0x08, 0x41, 0x30, 0x34,
- 0x32, 0x0C, 0x01, 0x00, 0x00, 0x20, 0x08, 0x41,
- 0x30, 0x34, 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30,
- 0x34, 0x34, 0x0A, 0x02, 0x08, 0x41, 0x30, 0x34,
- 0x35, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x36,
- 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x37, 0x0A,
- 0x00, 0x08, 0x41, 0x30, 0x34, 0x38, 0x0A, 0x00,
- 0x08, 0x41, 0x30, 0x34, 0x39, 0x0A, 0x00, 0x08,
- 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x08, 0x41,
- 0x30, 0x35, 0x31, 0x0A, 0x00, 0x08, 0x41, 0x30,
- 0x35, 0x32, 0x12, 0x14, 0x09, 0x0A, 0x00, 0x0A,
+ 0x33, 0x41, 0x30, 0x32, 0x35, 0x00, 0x88, 0x41,
+ 0x30, 0x32, 0x30, 0x41, 0x30, 0x32, 0x35, 0x00,
+ 0x70, 0x0A, 0x02, 0x41, 0x30, 0x33, 0x34, 0xA4,
+ 0x67, 0x14, 0x19, 0x41, 0x30, 0x34, 0x30, 0x09,
+ 0xA0, 0x0F, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31,
+ 0x33, 0x68, 0x00, 0x0A, 0x00, 0xA4, 0x0A, 0x00,
+ 0xA4, 0x0A, 0x01, 0x14, 0x41, 0x13, 0x41, 0x30,
+ 0x34, 0x31, 0x09, 0x70, 0x11, 0x04, 0x0B, 0x00,
+ 0x01, 0x67, 0x70, 0x0A, 0x03, 0x88, 0x67, 0x0A,
+ 0x00, 0x00, 0x70, 0x0A, 0x00, 0x88, 0x67, 0x0A,
+ 0x01, 0x00, 0x70, 0x0A, 0x00, 0x88, 0x67, 0x0A,
+ 0x02, 0x00, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x02,
+ 0x00, 0x41, 0x30, 0x31, 0x35, 0x70, 0x41, 0x30,
+ 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xF4,
+ 0x60, 0xA0, 0x19, 0x93, 0x41, 0x30, 0x31, 0x35,
+ 0x0A, 0x01, 0xA0, 0x0B, 0x93, 0x7B, 0x60, 0x0A,
+ 0x01, 0x00, 0x0A, 0x01, 0xA4, 0x67, 0x7D, 0x60,
+ 0x0A, 0x01, 0x60, 0xA0, 0x1B, 0x93, 0x41, 0x30,
+ 0x31, 0x35, 0x0A, 0x00, 0xA0, 0x0B, 0x93, 0x7B,
+ 0x60, 0x0A, 0x01, 0x00, 0x0A, 0x00, 0xA4, 0x67,
+ 0x7B, 0x60, 0x80, 0x0A, 0x01, 0x00, 0x60, 0x7D,
+ 0x60, 0x79, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x01,
+ 0x00, 0x60, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00,
+ 0x0A, 0x60, 0x0A, 0xF4, 0x60, 0x41, 0x30, 0x34,
+ 0x34, 0x71, 0x41, 0x30, 0x31, 0x39, 0x71, 0x41,
+ 0x30, 0x31, 0x38, 0x41, 0x30, 0x30, 0x36, 0x41,
+ 0x30, 0x31, 0x36, 0xA0, 0x12, 0x93, 0x41, 0x30,
+ 0x30, 0x39, 0x0A, 0x04, 0x41, 0x30, 0x30, 0x32,
+ 0x0A, 0x01, 0x41, 0x30, 0x32, 0x37, 0xA0, 0x4C,
+ 0x07, 0x90, 0x94, 0x41, 0x30, 0x30, 0x39, 0x0A,
+ 0x01, 0x95, 0x41, 0x30, 0x30, 0x39, 0x0A, 0x04,
+ 0xA0, 0x46, 0x05, 0x93, 0x41, 0x30, 0x30, 0x39,
+ 0x0A, 0x02, 0x41, 0x30, 0x34, 0x34, 0x71, 0x41,
+ 0x30, 0x31, 0x33, 0x71, 0x41, 0x30, 0x32, 0x31,
+ 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0xA2,
+ 0x37, 0x92, 0x94, 0x41, 0x30, 0x32, 0x35, 0x41,
+ 0x30, 0x30, 0x31, 0xA0, 0x26, 0x92, 0x93, 0x83,
+ 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, 0x32,
+ 0x35, 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41,
+ 0x30, 0x31, 0x34, 0x41, 0x30, 0x32, 0x35, 0x00,
+ 0x88, 0x41, 0x30, 0x32, 0x31, 0x41, 0x30, 0x32,
+ 0x35, 0x00, 0x75, 0x41, 0x30, 0x32, 0x35, 0xA1,
+ 0x0F, 0x41, 0x30, 0x34, 0x34, 0x71, 0x41, 0x30,
+ 0x32, 0x32, 0x71, 0x41, 0x30, 0x32, 0x31, 0x41,
+ 0x30, 0x32, 0x39, 0xA4, 0x67, 0x08, 0x41, 0x30,
+ 0x34, 0x35, 0x12, 0x12, 0x08, 0x0A, 0x00, 0x0A,
0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
- 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xA0,
- 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35,
- 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80,
- 0x0A, 0x40, 0x00, 0x0A, 0x40, 0x70, 0x69, 0x88,
- 0x41, 0x30, 0x31, 0x36, 0x68, 0x00, 0xA0, 0x13,
- 0x93, 0x69, 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x41,
- 0x30, 0x34, 0x32, 0x70, 0x0A, 0x21, 0x41, 0x30,
- 0x34, 0x34, 0xA0, 0x1B, 0x92, 0x93, 0x83, 0x88,
- 0x41, 0x30, 0x31, 0x34, 0x68, 0x00, 0x0A, 0x00,
- 0x41, 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA1, 0x80,
- 0x0B, 0x00, 0x10, 0x00, 0x0A, 0x00, 0xA1, 0x10,
- 0x41, 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA1, 0x80,
- 0x0B, 0x00, 0x10, 0x00, 0x0B, 0x00, 0x10, 0x41,
- 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA4, 0x80, 0x0C,
- 0x01, 0x00, 0x00, 0x20, 0x00, 0x41, 0x30, 0x34,
- 0x32, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00,
- 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35, 0x35,
- 0x60, 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x41,
- 0x30, 0x34, 0x34, 0x70, 0x79, 0x72, 0x68, 0x0A,
- 0x02, 0x00, 0x0A, 0x03, 0x00, 0x60, 0x7B, 0x41,
- 0x30, 0x33, 0x31, 0x60, 0x0A, 0x70, 0x0C, 0x00,
- 0x00, 0x40, 0x00, 0x41, 0x30, 0x34, 0x33, 0xA0,
- 0x45, 0x1B, 0x92, 0x93, 0x41, 0x30, 0x34, 0x33,
- 0x0A, 0x00, 0xA0, 0x4D, 0x0C, 0x92, 0x93, 0x68,
- 0x0A, 0x06, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60,
- 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A,
- 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x41, 0x30, 0x34,
- 0x37, 0x70, 0x79, 0x41, 0x30, 0x34, 0x37, 0x0A,
- 0x08, 0x00, 0x63, 0x70, 0x41, 0x30, 0x33, 0x31,
- 0x63, 0x0A, 0x0C, 0x63, 0x70, 0x7B, 0x7A, 0x63,
- 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x00, 0x41, 0x30,
- 0x34, 0x38, 0xA0, 0x14, 0x92, 0x93, 0x7B, 0x41,
- 0x30, 0x34, 0x38, 0x0A, 0x80, 0x00, 0x0A, 0x00,
- 0x70, 0x0A, 0x07, 0x41, 0x30, 0x34, 0x39, 0x70,
- 0x79, 0x41, 0x30, 0x34, 0x37, 0x0A, 0x08, 0x00,
- 0x63, 0x70, 0x0A, 0x00, 0x62, 0xA2, 0x4A, 0x06,
- 0x92, 0x94, 0x62, 0x41, 0x30, 0x34, 0x39, 0x70,
- 0x41, 0x30, 0x35, 0x36, 0x63, 0x0A, 0x10, 0x41,
- 0x30, 0x35, 0x30, 0xA0, 0x40, 0x05, 0x92, 0x93,
- 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x72, 0x41,
- 0x30, 0x35, 0x30, 0x0A, 0x10, 0x41, 0x30, 0x35,
- 0x30, 0x70, 0x41, 0x30, 0x33, 0x31, 0x63, 0x41,
- 0x30, 0x35, 0x30, 0x41, 0x30, 0x35, 0x31, 0x70,
- 0x7B, 0x41, 0x30, 0x35, 0x31, 0x0A, 0x03, 0x00,
- 0x88, 0x41, 0x30, 0x35, 0x32, 0x62, 0x00, 0xA0,
- 0x1C, 0x92, 0x93, 0x7B, 0x41, 0x30, 0x35, 0x31,
- 0x0A, 0x03, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x35,
- 0x35, 0x63, 0x41, 0x30, 0x35, 0x30, 0x80, 0x0A,
- 0x03, 0x00, 0x0A, 0x00, 0x75, 0x62, 0x75, 0x63,
- 0xA1, 0x25, 0x70, 0x41, 0x30, 0x35, 0x37, 0x0A,
- 0x00, 0x0A, 0x00, 0x41, 0x30, 0x34, 0x35, 0x7B,
- 0x41, 0x30, 0x34, 0x35, 0x0A, 0x03, 0x61, 0xA0,
- 0x0E, 0x92, 0x93, 0x61, 0x0A, 0x00, 0x41, 0x30,
- 0x35, 0x37, 0x0A, 0x00, 0x0A, 0x01, 0x70, 0x0A,
- 0x01, 0x62, 0xA2, 0x41, 0x05, 0x62, 0x41, 0x30,
- 0x35, 0x35, 0x60, 0x0A, 0x68, 0x80, 0x0A, 0x00,
- 0x00, 0x0A, 0x20, 0x5B, 0x22, 0x0A, 0x1E, 0xA2,
- 0x13, 0x7B, 0x41, 0x30, 0x33, 0x31, 0x60, 0x0A,
- 0x68, 0x0C, 0x00, 0x00, 0x00, 0x08, 0x00, 0x5B,
- 0x22, 0x0A, 0x0A, 0x70, 0x0A, 0x00, 0x62, 0xA0,
- 0x24, 0x93, 0x69, 0x0A, 0x02, 0x70, 0x41, 0x30,
- 0x35, 0x38, 0x68, 0x0A, 0xA4, 0x41, 0x30, 0x34,
- 0x36, 0xA0, 0x12, 0x92, 0x93, 0x7B, 0x41, 0x30,
- 0x34, 0x36, 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00,
- 0x70, 0x0A, 0x01, 0x62, 0xA0, 0x44, 0x05, 0x92,
- 0x93, 0x68, 0x0A, 0x06, 0x70, 0x79, 0x41, 0x30,
- 0x34, 0x37, 0x0A, 0x08, 0x00, 0x63, 0x70, 0x0A,
- 0x00, 0x62, 0xA2, 0x3E, 0x92, 0x94, 0x62, 0x41,
- 0x30, 0x34, 0x39, 0x70, 0x41, 0x30, 0x35, 0x36,
- 0x63, 0x0A, 0x10, 0x41, 0x30, 0x35, 0x30, 0xA0,
- 0x25, 0x92, 0x93, 0x41, 0x30, 0x35, 0x30, 0x0A,
- 0x00, 0x72, 0x41, 0x30, 0x35, 0x30, 0x0A, 0x10,
- 0x41, 0x30, 0x35, 0x30, 0x41, 0x30, 0x35, 0x39,
- 0x63, 0x41, 0x30, 0x35, 0x30, 0x83, 0x88, 0x41,
- 0x30, 0x35, 0x32, 0x62, 0x00, 0x75, 0x62, 0x75,
- 0x63, 0xA1, 0x0B, 0x41, 0x30, 0x35, 0x37, 0x41,
- 0x30, 0x34, 0x35, 0x0A, 0x01, 0xA1, 0x01, 0xA0,
- 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35,
- 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80,
- 0x0A, 0x40, 0x00, 0x0A, 0x00, 0x5B, 0x01, 0x41,
- 0x30, 0x36, 0x30, 0x00, 0x14, 0x4F, 0x07, 0x41,
- 0x30, 0x33, 0x39, 0x02, 0x5B, 0x23, 0x41, 0x30,
- 0x36, 0x30, 0xFF, 0xFF, 0x70, 0x41, 0x30, 0x36,
- 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61,
- 0x7D, 0x61, 0x0A, 0x02, 0x61, 0x41, 0x30, 0x36,
- 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61,
- 0x7B, 0x61, 0x80, 0x79, 0x0A, 0x03, 0x0A, 0x03,
- 0x00, 0x00, 0x61, 0x7D, 0x61, 0x79, 0x68, 0x0A,
- 0x03, 0x00, 0x61, 0x7B, 0x80, 0x61, 0x00, 0x0A,
- 0x04, 0x62, 0x7D, 0x7B, 0x61, 0x80, 0x0A, 0x04,
- 0x00, 0x00, 0x62, 0x61, 0x41, 0x30, 0x36, 0x32,
- 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0xA0,
- 0x1E, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2, 0x17,
- 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00, 0x62,
- 0x7B, 0x41, 0x30, 0x36, 0x31, 0x0A, 0x00, 0x0A,
- 0x60, 0x0A, 0xEB, 0x0A, 0x01, 0x61, 0x5B, 0x27,
- 0x41, 0x30, 0x36, 0x30, 0x14, 0x21, 0x41, 0x30,
- 0x33, 0x34, 0x02, 0x70, 0x87, 0x68, 0x61, 0x70,
- 0x0A, 0x00, 0x60, 0xA2, 0x12, 0x95, 0x60, 0x61,
- 0x70, 0x83, 0x88, 0x83, 0x68, 0x60, 0x00, 0x88,
- 0x83, 0x69, 0x60, 0x00, 0x75, 0x60, 0x14, 0x37,
- 0x41, 0x30, 0x36, 0x33, 0x09, 0x70, 0x11, 0x04,
- 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00,
- 0x41, 0x30, 0x32, 0x34, 0x8B, 0x67, 0x0A, 0x02,
- 0x41, 0x30, 0x36, 0x34, 0x8C, 0x68, 0x0A, 0x02,
- 0x41, 0x30, 0x36, 0x35, 0x70, 0x0A, 0x03, 0x41,
- 0x30, 0x32, 0x34, 0x70, 0x41, 0x30, 0x36, 0x35,
- 0x41, 0x30, 0x36, 0x34, 0xA4, 0x67, 0x14, 0x4A,
- 0x07, 0x41, 0x30, 0x36, 0x36, 0x09, 0x70, 0x11,
- 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A,
- 0x00, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67, 0x0A,
- 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x67, 0x0A,
- 0x03, 0x41, 0x30, 0x36, 0x37, 0x8B, 0x68, 0x0A,
- 0x02, 0x41, 0x30, 0x36, 0x38, 0x8C, 0x68, 0x0A,
- 0x04, 0x41, 0x30, 0x36, 0x39, 0x74, 0x7A, 0x41,
- 0x30, 0x36, 0x38, 0x0A, 0x03, 0x00, 0x0A, 0x02,
- 0x61, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x36, 0x39,
- 0x0A, 0x01, 0x70, 0x41, 0x30, 0x37, 0x30, 0x61,
- 0x41, 0x30, 0x36, 0x39, 0xA1, 0x0B, 0x70, 0x41,
- 0x30, 0x37, 0x31, 0x61, 0x41, 0x30, 0x36, 0x39,
- 0x70, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x34, 0x70,
- 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0x70, 0x41,
- 0x30, 0x36, 0x39, 0x41, 0x30, 0x36, 0x37, 0xA4,
- 0x67, 0x14, 0x49, 0x11, 0x41, 0x30, 0x37, 0x30,
- 0x01, 0x08, 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00,
- 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C,
- 0x67, 0x0A, 0x07, 0x41, 0x30, 0x37, 0x34, 0xA0,
- 0x0C, 0x92, 0x93, 0x41, 0x30, 0x37, 0x34, 0x0A,
- 0x01, 0xA4, 0x0A, 0x01, 0x8C, 0x67, 0x0A, 0x00,
- 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01,
- 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30, 0x35,
- 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36,
- 0x0A, 0x00, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30,
- 0x37, 0x37, 0x8C, 0x67, 0x0A, 0x03, 0x41, 0x30,
- 0x37, 0x38, 0x41, 0x30, 0x37, 0x39, 0x68, 0x41,
- 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x0A,
- 0x00, 0x41, 0x30, 0x38, 0x30, 0x68, 0x0A, 0x00,
- 0x70, 0x41, 0x30, 0x38, 0x31, 0x68, 0x61, 0xA0,
- 0x4B, 0x09, 0x93, 0x61, 0x0A, 0x01, 0x70, 0x41,
- 0x30, 0x38, 0x32, 0x68, 0x41, 0x30, 0x37, 0x32,
- 0x74, 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x01,
- 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x00, 0x62,
- 0xA0, 0x47, 0x07, 0x92, 0x93, 0x62, 0x0A, 0x00,
- 0xA0, 0x16, 0x92, 0x93, 0x41, 0x30, 0x37, 0x32,
- 0x0A, 0x00, 0x72, 0x41, 0x30, 0x37, 0x37, 0x62,
- 0x63, 0x70, 0x41, 0x30, 0x37, 0x38, 0x64, 0xA1,
- 0x0E, 0x74, 0x41, 0x30, 0x37, 0x38, 0x62, 0x64,
- 0x70, 0x41, 0x30, 0x37, 0x37, 0x63, 0x41, 0x30,
- 0x37, 0x39, 0x68, 0x63, 0x64, 0x0A, 0x01, 0xA0,
- 0x16, 0x94, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30,
- 0x37, 0x36, 0x70, 0x41, 0x30, 0x37, 0x36, 0x63,
- 0x70, 0x41, 0x30, 0x37, 0x35, 0x64, 0xA1, 0x0D,
- 0x70, 0x41, 0x30, 0x37, 0x36, 0x64, 0x70, 0x41,
- 0x30, 0x37, 0x35, 0x63, 0xA0, 0x0D, 0x92, 0x93,
- 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, 0x72, 0x63,
- 0x62, 0x63, 0xA1, 0x05, 0x74, 0x64, 0x62, 0x64,
- 0x41, 0x30, 0x30, 0x35, 0x63, 0x64, 0x0A, 0x01,
- 0xA4, 0x0A, 0x01, 0x41, 0x30, 0x37, 0x31, 0x68,
- 0xA4, 0x0A, 0x00, 0x14, 0x4A, 0x06, 0x41, 0x30,
- 0x37, 0x31, 0x01, 0x70, 0x41, 0x30, 0x37, 0x33,
- 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x07, 0x41, 0x30,
- 0x37, 0x34, 0xA0, 0x0C, 0x92, 0x93, 0x41, 0x30,
- 0x37, 0x34, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x41,
- 0x30, 0x38, 0x30, 0x68, 0x0A, 0x01, 0x8C, 0x67,
- 0x0A, 0x02, 0x41, 0x30, 0x37, 0x37, 0x8C, 0x67,
- 0x0A, 0x03, 0x41, 0x30, 0x37, 0x38, 0x41, 0x30,
- 0x37, 0x39, 0x68, 0x41, 0x30, 0x37, 0x37, 0x41,
- 0x30, 0x37, 0x38, 0x0A, 0x01, 0x8C, 0x67, 0x0A,
- 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A,
- 0x01, 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30,
- 0x35, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37,
- 0x36, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, 0x41,
- 0x04, 0x41, 0x30, 0x38, 0x32, 0x01, 0x70, 0x41,
- 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A,
- 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A,
- 0x01, 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x00,
- 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x37, 0x35,
- 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x01, 0x60,
- 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68, 0x0A, 0x50,
- 0x0A, 0x01, 0x61, 0xA4, 0x7F, 0x60, 0x61, 0x00,
- 0x14, 0x43, 0x04, 0x41, 0x30, 0x38, 0x30, 0x02,
- 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C,
- 0x67, 0x0A, 0x04, 0x41, 0x30, 0x38, 0x34, 0x8B,
- 0x67, 0x0A, 0x05, 0x41, 0x30, 0x38, 0x35, 0x41,
- 0x30, 0x35, 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D,
- 0x79, 0x41, 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00,
- 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, 0x00, 0x01,
- 0x41, 0x30, 0x38, 0x34, 0x00, 0x00, 0x00, 0x80,
- 0x0A, 0x01, 0x00, 0x69, 0x14, 0x38, 0x41, 0x30,
- 0x38, 0x31, 0x01, 0x70, 0x0A, 0x00, 0x60, 0x70,
- 0x0A, 0x00, 0x67, 0xA2, 0x27, 0x95, 0x60, 0x0B,
- 0x40, 0x01, 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68,
- 0x0A, 0xA5, 0x0A, 0x3F, 0x61, 0xA0, 0x0F, 0x93,
- 0x61, 0x0A, 0x10, 0x70, 0x0A, 0x01, 0x67, 0x70,
- 0x0B, 0x40, 0x01, 0x60, 0xA5, 0x5B, 0x21, 0x0A,
- 0xFA, 0x75, 0x60, 0xA4, 0x67, 0x14, 0x4B, 0x06,
- 0x41, 0x30, 0x38, 0x33, 0x02, 0xA0, 0x25, 0x93,
- 0x68, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, 0x35,
- 0x38, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, 0x0A,
- 0x07, 0x60, 0x70, 0x83, 0x88, 0x11, 0x0A, 0x0A,
- 0x07, 0x00, 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10,
- 0x60, 0x00, 0x61, 0xA1, 0x3B, 0x70, 0x41, 0x30,
- 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x00,
- 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01,
- 0x41, 0x30, 0x37, 0x36, 0xA0, 0x14, 0x94, 0x41,
- 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x74,
- 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36,
- 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x37, 0x36,
- 0x41, 0x30, 0x37, 0x35, 0x61, 0x75, 0x61, 0xA4,
- 0x61, 0x14, 0x4E, 0x0A, 0x41, 0x30, 0x37, 0x39,
- 0x04, 0x08, 0x41, 0x30, 0x37, 0x37, 0x0A, 0x00,
- 0x08, 0x41, 0x30, 0x37, 0x38, 0x0A, 0x00, 0x70,
- 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, 0x69,
- 0x41, 0x30, 0x37, 0x37, 0x70, 0x6A, 0x41, 0x30,
- 0x37, 0x38, 0x8B, 0x67, 0x0A, 0x05, 0x41, 0x30,
- 0x38, 0x35, 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x37,
- 0x37, 0x41, 0x30, 0x37, 0x38, 0x74, 0x41, 0x30,
- 0x37, 0x37, 0x41, 0x30, 0x37, 0x38, 0x61, 0x70,
- 0x41, 0x30, 0x37, 0x38, 0x62, 0xA1, 0x11, 0x74,
- 0x41, 0x30, 0x37, 0x38, 0x41, 0x30, 0x37, 0x37,
- 0x61, 0x70, 0x41, 0x30, 0x37, 0x37, 0x62, 0x79,
- 0x74, 0x79, 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01,
- 0x00, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x61, 0xA0,
- 0x20, 0x93, 0x6B, 0x0A, 0x00, 0x41, 0x30, 0x35,
- 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41,
- 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00, 0x0B, 0x23,
- 0x80, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x61,
- 0xA1, 0x1B, 0x41, 0x30, 0x35, 0x33, 0x0A, 0x00,
- 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x38, 0x35,
- 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, 0x00, 0x80,
- 0x61, 0x00, 0x0A, 0x00, 0x5B, 0x21, 0x0A, 0x0A,
- 0x14, 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02,
- 0x70, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84,
- 0x60, 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60,
- 0x0A, 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93,
- 0x68, 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF,
- 0xFF, 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60,
- 0xA1, 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00,
- 0x7B, 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60,
- 0x7D, 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B,
- 0x60, 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D,
- 0x60, 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34,
- 0x0B, 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30,
- 0x30, 0x35, 0x03, 0x14, 0x06, 0x41, 0x30, 0x30,
- 0x36, 0x01
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x14, 0x4A, 0x12,
+ 0x41, 0x30, 0x32, 0x39, 0x08, 0x70, 0x0A, 0x00,
+ 0x41, 0x30, 0x32, 0x35, 0x41, 0x30, 0x34, 0x34,
+ 0x71, 0x41, 0x30, 0x32, 0x32, 0x71, 0x41, 0x30,
+ 0x34, 0x35, 0xA2, 0x30, 0x92, 0x94, 0x41, 0x30,
+ 0x32, 0x35, 0x41, 0x30, 0x30, 0x31, 0xA0, 0x1F,
+ 0x93, 0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x32,
+ 0x35, 0x0A, 0x01, 0x70, 0x41, 0x30, 0x34, 0x36,
+ 0x41, 0x30, 0x32, 0x35, 0x88, 0x41, 0x30, 0x34,
+ 0x35, 0x41, 0x30, 0x32, 0x35, 0x00, 0x75, 0x41,
+ 0x30, 0x32, 0x35, 0xA0, 0x1F, 0x92, 0x93, 0x89,
+ 0x41, 0x30, 0x32, 0x33, 0x01, 0x0A, 0x01, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x34,
+ 0x34, 0x71, 0x41, 0x30, 0x32, 0x32, 0x71, 0x41,
+ 0x30, 0x34, 0x35, 0xA0, 0x2B, 0x92, 0x93, 0x89,
+ 0x41, 0x30, 0x34, 0x35, 0x01, 0x0A, 0x02, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x34,
+ 0x37, 0x41, 0x30, 0x31, 0x30, 0x0A, 0x01, 0x41,
+ 0x30, 0x30, 0x35, 0x0A, 0x02, 0x41, 0x30, 0x30,
+ 0x32, 0x0A, 0x02, 0x41, 0x30, 0x32, 0x37, 0x70,
+ 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0xA2, 0x4E,
+ 0x05, 0x92, 0x94, 0x41, 0x30, 0x32, 0x35, 0x41,
+ 0x30, 0x30, 0x31, 0xA0, 0x12, 0x93, 0x41, 0x30,
+ 0x34, 0x30, 0x41, 0x30, 0x32, 0x35, 0x0A, 0x00,
+ 0x75, 0x41, 0x30, 0x32, 0x35, 0x9F, 0x70, 0x83,
+ 0x88, 0x41, 0x30, 0x32, 0x31, 0x41, 0x30, 0x32,
+ 0x35, 0x00, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30,
+ 0x34, 0x35, 0x41, 0x30, 0x32, 0x35, 0x00, 0x62,
+ 0xA0, 0x0A, 0x93, 0x60, 0x62, 0x75, 0x41, 0x30,
+ 0x32, 0x35, 0x9F, 0x70, 0x62, 0x88, 0x41, 0x30,
+ 0x32, 0x31, 0x41, 0x30, 0x32, 0x35, 0x00, 0x41,
+ 0x30, 0x34, 0x38, 0x41, 0x30, 0x32, 0x35, 0x62,
+ 0x75, 0x41, 0x30, 0x32, 0x35, 0xA0, 0x2A, 0x93,
+ 0x89, 0x41, 0x30, 0x34, 0x35, 0x01, 0x0A, 0x02,
+ 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30,
+ 0x30, 0x32, 0x0A, 0x01, 0x41, 0x30, 0x32, 0x37,
+ 0x41, 0x30, 0x30, 0x35, 0x0A, 0x01, 0x41, 0x30,
+ 0x34, 0x37, 0x41, 0x30, 0x31, 0x31, 0x0A, 0x00,
+ 0x14, 0x43, 0x05, 0x41, 0x30, 0x34, 0x36, 0x01,
+ 0x70, 0x0A, 0x02, 0x60, 0xA0, 0x39, 0x93, 0x83,
+ 0x88, 0x41, 0x30, 0x31, 0x38, 0x68, 0x00, 0x0A,
+ 0x00, 0xA0, 0x14, 0x91, 0x93, 0x41, 0x30, 0x32,
+ 0x37, 0x0A, 0x01, 0x93, 0x41, 0x30, 0x30, 0x39,
+ 0x0A, 0x03, 0x70, 0x0A, 0x01, 0x60, 0xA0, 0x17,
+ 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, 0x34,
+ 0x68, 0x00, 0x0A, 0x00, 0x70, 0x83, 0x88, 0x41,
+ 0x30, 0x31, 0x34, 0x68, 0x00, 0x60, 0xA1, 0x0B,
+ 0x70, 0x83, 0x88, 0x41, 0x30, 0x32, 0x30, 0x68,
+ 0x00, 0x60, 0xA4, 0x60, 0x14, 0x43, 0x0E, 0x41,
+ 0x30, 0x34, 0x38, 0x02, 0xA0, 0x15, 0x93, 0x68,
+ 0x0A, 0x06, 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00,
+ 0x0A, 0x60, 0x0A, 0x80, 0x80, 0x0A, 0x40, 0x00,
+ 0x0A, 0x40, 0x41, 0x30, 0x34, 0x39, 0x68, 0x69,
+ 0xA0, 0x1B, 0x92, 0x93, 0x83, 0x88, 0x41, 0x30,
+ 0x31, 0x38, 0x68, 0x00, 0x0A, 0x00, 0x41, 0x30,
+ 0x35, 0x30, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00,
+ 0x10, 0x00, 0x0A, 0x00, 0xA1, 0x10, 0x41, 0x30,
+ 0x35, 0x30, 0x68, 0x0A, 0xA1, 0x80, 0x0B, 0x00,
+ 0x10, 0x00, 0x0B, 0x00, 0x10, 0x70, 0x79, 0x72,
+ 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61,
+ 0x7B, 0x41, 0x30, 0x30, 0x37, 0x61, 0x0A, 0x70,
+ 0x0C, 0x00, 0x00, 0x40, 0x00, 0x63, 0xA0, 0x41,
+ 0x06, 0x92, 0x93, 0x63, 0x0A, 0x00, 0x41, 0x30,
+ 0x35, 0x31, 0x68, 0x70, 0x0A, 0x01, 0x62, 0xA2,
+ 0x4B, 0x04, 0x62, 0x41, 0x30, 0x35, 0x32, 0x61,
+ 0x0A, 0x68, 0x80, 0x0A, 0x00, 0x00, 0x0A, 0x20,
+ 0x5B, 0x22, 0x0A, 0x1E, 0xA2, 0x13, 0x7B, 0x41,
+ 0x30, 0x30, 0x37, 0x61, 0x0A, 0x68, 0x0C, 0x00,
+ 0x00, 0x00, 0x08, 0x00, 0x5B, 0x22, 0x0A, 0x0A,
+ 0x70, 0x0A, 0x00, 0x62, 0xA0, 0x1E, 0x93, 0x69,
+ 0x0A, 0x01, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68,
+ 0x0A, 0xA4, 0x64, 0xA0, 0x0F, 0x92, 0x93, 0x7B,
+ 0x64, 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00, 0x70,
+ 0x0A, 0x01, 0x62, 0x41, 0x30, 0x35, 0x34, 0x68,
+ 0xA1, 0x01, 0xA0, 0x15, 0x93, 0x68, 0x0A, 0x06,
+ 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A, 0x60,
+ 0x0A, 0x80, 0x80, 0x0A, 0x40, 0x00, 0x0A, 0x00,
+ 0x08, 0x41, 0x30, 0x35, 0x35, 0x12, 0x14, 0x09,
+ 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
+ 0x0A, 0x00, 0x08, 0x41, 0x30, 0x35, 0x36, 0x0A,
+ 0x00, 0x08, 0x41, 0x30, 0x35, 0x37, 0x0A, 0x00,
+ 0x14, 0x4C, 0x0E, 0x41, 0x30, 0x35, 0x31, 0x09,
+ 0x70, 0x0A, 0x00, 0x41, 0x30, 0x35, 0x36, 0x70,
+ 0x0A, 0x00, 0x41, 0x30, 0x35, 0x37, 0x70, 0x79,
+ 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, 0x00,
+ 0x61, 0xA0, 0x21, 0x93, 0x68, 0x0A, 0x06, 0x70,
+ 0x41, 0x30, 0x35, 0x38, 0x0A, 0x00, 0x0A, 0x00,
+ 0x88, 0x41, 0x30, 0x35, 0x35, 0x0A, 0x00, 0x00,
+ 0x41, 0x30, 0x35, 0x38, 0x0A, 0x00, 0x0A, 0x01,
+ 0xA4, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x30, 0x37,
+ 0x61, 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63,
+ 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x63, 0x70,
+ 0x79, 0x63, 0x0A, 0x08, 0x00, 0x62, 0x70, 0x41,
+ 0x30, 0x30, 0x37, 0x62, 0x0A, 0x0C, 0x63, 0x70,
+ 0x7B, 0x7A, 0x63, 0x0A, 0x10, 0x00, 0x0A, 0xFF,
+ 0x00, 0x63, 0xA0, 0x0E, 0x92, 0x93, 0x7B, 0x63,
+ 0x0A, 0x80, 0x00, 0x0A, 0x00, 0x70, 0x0A, 0x07,
+ 0x60, 0xA1, 0x05, 0x70, 0x0A, 0x00, 0x60, 0x70,
+ 0x0A, 0x00, 0x64, 0xA2, 0x41, 0x06, 0x92, 0x94,
+ 0x64, 0x60, 0x70, 0x41, 0x30, 0x35, 0x39, 0x72,
+ 0x62, 0x64, 0x00, 0x0A, 0x10, 0x41, 0x30, 0x35,
+ 0x36, 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x35, 0x36,
+ 0x0A, 0x00, 0x75, 0x64, 0x9F, 0x72, 0x41, 0x30,
+ 0x35, 0x36, 0x0A, 0x10, 0x41, 0x30, 0x35, 0x36,
+ 0x70, 0x41, 0x30, 0x30, 0x37, 0x72, 0x62, 0x64,
+ 0x00, 0x41, 0x30, 0x35, 0x36, 0x41, 0x30, 0x35,
+ 0x37, 0x70, 0x7B, 0x41, 0x30, 0x35, 0x37, 0x0A,
+ 0x03, 0x00, 0x88, 0x41, 0x30, 0x35, 0x35, 0x64,
+ 0x00, 0x41, 0x30, 0x35, 0x32, 0x72, 0x62, 0x64,
+ 0x00, 0x41, 0x30, 0x35, 0x36, 0x80, 0x0A, 0x03,
+ 0x00, 0x0A, 0x00, 0x75, 0x64, 0x14, 0x43, 0x0C,
+ 0x41, 0x30, 0x35, 0x34, 0x09, 0x70, 0x0A, 0x00,
+ 0x41, 0x30, 0x35, 0x36, 0x70, 0x0A, 0x00, 0x41,
+ 0x30, 0x35, 0x37, 0xA0, 0x17, 0x93, 0x68, 0x0A,
+ 0x06, 0x41, 0x30, 0x35, 0x38, 0x83, 0x88, 0x41,
+ 0x30, 0x35, 0x35, 0x0A, 0x00, 0x00, 0x0A, 0x01,
+ 0xA4, 0x0A, 0x00, 0x70, 0x79, 0x72, 0x68, 0x0A,
+ 0x02, 0x00, 0x0A, 0x03, 0x00, 0x61, 0x70, 0x41,
+ 0x30, 0x30, 0x37, 0x61, 0x0A, 0x18, 0x63, 0x70,
+ 0x7B, 0x7A, 0x63, 0x0A, 0x08, 0x00, 0x0A, 0xFF,
+ 0x00, 0x63, 0x70, 0x79, 0x63, 0x0A, 0x08, 0x00,
+ 0x62, 0x70, 0x41, 0x30, 0x30, 0x37, 0x62, 0x0A,
+ 0x0C, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, 0x10,
+ 0x00, 0x0A, 0xFF, 0x00, 0x63, 0xA0, 0x0E, 0x92,
+ 0x93, 0x7B, 0x63, 0x0A, 0x80, 0x00, 0x0A, 0x00,
+ 0x70, 0x0A, 0x07, 0x60, 0xA1, 0x05, 0x70, 0x0A,
+ 0x00, 0x60, 0x70, 0x0A, 0x00, 0x64, 0xA2, 0x42,
+ 0x04, 0x92, 0x94, 0x64, 0x60, 0x70, 0x41, 0x30,
+ 0x35, 0x39, 0x72, 0x62, 0x64, 0x00, 0x0A, 0x10,
+ 0x41, 0x30, 0x35, 0x36, 0xA0, 0x0B, 0x93, 0x41,
+ 0x30, 0x35, 0x36, 0x0A, 0x00, 0x75, 0x64, 0x9F,
+ 0x72, 0x41, 0x30, 0x35, 0x36, 0x0A, 0x10, 0x41,
+ 0x30, 0x35, 0x36, 0x41, 0x30, 0x30, 0x38, 0x72,
+ 0x62, 0x64, 0x00, 0x41, 0x30, 0x35, 0x36, 0x83,
+ 0x88, 0x41, 0x30, 0x35, 0x35, 0x64, 0x00, 0x75,
+ 0x64, 0x14, 0x47, 0x05, 0x41, 0x30, 0x34, 0x39,
+ 0x02, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00,
+ 0x0A, 0x03, 0x00, 0x60, 0xA0, 0x22, 0x93, 0x69,
+ 0x0A, 0x01, 0x41, 0x30, 0x35, 0x32, 0x60, 0x0A,
+ 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x0A, 0x21, 0x41,
+ 0x30, 0x35, 0x30, 0x68, 0x0A, 0xA4, 0x80, 0x0C,
+ 0x01, 0x00, 0x00, 0x20, 0x00, 0x0A, 0x00, 0xA1,
+ 0x21, 0x41, 0x30, 0x35, 0x30, 0x68, 0x0A, 0xA4,
+ 0x80, 0x0C, 0x01, 0x00, 0x00, 0x20, 0x00, 0x0C,
+ 0x01, 0x00, 0x00, 0x20, 0x41, 0x30, 0x35, 0x32,
+ 0x60, 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x0A,
+ 0x02, 0x14, 0x41, 0x07, 0x41, 0x30, 0x34, 0x37,
+ 0x0A, 0x70, 0x41, 0x30, 0x34, 0x32, 0x0A, 0x00,
+ 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0x7D, 0x61, 0x0A,
+ 0x02, 0x61, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00,
+ 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0x7B, 0x61, 0x80,
+ 0x79, 0x0A, 0x03, 0x0A, 0x03, 0x00, 0x00, 0x61,
+ 0x7D, 0x61, 0x79, 0x68, 0x0A, 0x03, 0x00, 0x61,
+ 0x7B, 0x80, 0x61, 0x00, 0x0A, 0x04, 0x62, 0x7D,
+ 0x7B, 0x61, 0x80, 0x0A, 0x04, 0x00, 0x00, 0x62,
+ 0x61, 0x41, 0x30, 0x34, 0x33, 0x0A, 0x00, 0x0A,
+ 0x60, 0x0A, 0xEA, 0x61, 0xA0, 0x1E, 0x92, 0x93,
+ 0x69, 0x0A, 0x00, 0xA2, 0x17, 0x92, 0x93, 0x79,
+ 0x61, 0x0A, 0x02, 0x00, 0x62, 0x7B, 0x41, 0x30,
+ 0x34, 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEB,
+ 0x0A, 0x01, 0x61, 0x14, 0x21, 0x41, 0x30, 0x34,
+ 0x34, 0x02, 0x70, 0x87, 0x68, 0x61, 0x70, 0x0A,
+ 0x00, 0x60, 0xA2, 0x12, 0x95, 0x60, 0x61, 0x70,
+ 0x83, 0x88, 0x83, 0x68, 0x60, 0x00, 0x88, 0x83,
+ 0x69, 0x60, 0x00, 0x75, 0x60, 0x14, 0x11, 0x41,
+ 0x30, 0x32, 0x37, 0x00, 0xA4, 0x7B, 0x41, 0x30,
+ 0x31, 0x36, 0x41, 0x30, 0x31, 0x37, 0x00, 0x08,
+ 0x41, 0x30, 0x36, 0x30, 0x0A, 0x00, 0x08, 0x41,
+ 0x30, 0x36, 0x31, 0x0A, 0x00, 0x08, 0x41, 0x30,
+ 0x36, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36,
+ 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x34,
+ 0x0A, 0x00, 0x08, 0x41, 0x30, 0x36, 0x35, 0x0A,
+ 0x00, 0x14, 0x37, 0x41, 0x30, 0x36, 0x36, 0x01,
+ 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B,
+ 0x67, 0x0A, 0x00, 0x41, 0x30, 0x33, 0x33, 0x8B,
+ 0x67, 0x0A, 0x02, 0x41, 0x30, 0x36, 0x37, 0x8C,
+ 0x68, 0x0A, 0x02, 0x41, 0x30, 0x36, 0x38, 0x70,
+ 0x0A, 0x03, 0x41, 0x30, 0x33, 0x33, 0x70, 0x41,
+ 0x30, 0x36, 0x38, 0x41, 0x30, 0x36, 0x37, 0xA4,
+ 0x67, 0x14, 0x4C, 0x06, 0x41, 0x30, 0x36, 0x39,
+ 0x09, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x04, 0x00,
+ 0x60, 0x70, 0x83, 0x88, 0x68, 0x0A, 0x02, 0x00,
+ 0x61, 0x74, 0x7A, 0x61, 0x0A, 0x03, 0x00, 0x0A,
+ 0x02, 0x61, 0xA0, 0x09, 0x93, 0x60, 0x0A, 0x01,
+ 0x70, 0x0A, 0x06, 0x62, 0xA1, 0x05, 0x70, 0x0A,
+ 0x04, 0x62, 0x70, 0x41, 0x30, 0x37, 0x30, 0x61,
+ 0x62, 0x60, 0x70, 0x11, 0x03, 0x0A, 0x0A, 0x67,
+ 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30, 0x33, 0x33,
+ 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x33, 0x34,
+ 0x8C, 0x67, 0x0A, 0x03, 0x41, 0x30, 0x37, 0x31,
+ 0x70, 0x0A, 0x04, 0x41, 0x30, 0x33, 0x33, 0x70,
+ 0x0A, 0x00, 0x41, 0x30, 0x33, 0x34, 0x70, 0x60,
+ 0x41, 0x30, 0x37, 0x31, 0xA4, 0x67, 0x08, 0x41,
+ 0x30, 0x37, 0x32, 0x11, 0x0D, 0x0A, 0x0A, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x14, 0x47, 0x1A, 0x41, 0x30, 0x37, 0x30,
+ 0x0A, 0x70, 0x0A, 0x00, 0x64, 0x70, 0x41, 0x30,
+ 0x37, 0x33, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67,
+ 0x0A, 0x07, 0x00, 0x61, 0xA0, 0x08, 0x92, 0x93,
+ 0x61, 0x0A, 0x01, 0xA4, 0x64, 0x70, 0x69, 0x62,
+ 0xA2, 0x4E, 0x17, 0x92, 0x93, 0x62, 0x0A, 0x08,
+ 0xA0, 0x3E, 0x93, 0x62, 0x0A, 0x06, 0x70, 0x0A,
+ 0x00, 0x88, 0x41, 0x30, 0x31, 0x34, 0x68, 0x00,
+ 0x41, 0x30, 0x35, 0x30, 0x68, 0x0A, 0xA2, 0x80,
+ 0x0B, 0x00, 0x20, 0x00, 0x0A, 0x00, 0x70, 0x0A,
+ 0x00, 0x41, 0x30, 0x31, 0x37, 0x41, 0x30, 0x32,
+ 0x39, 0x41, 0x30, 0x37, 0x34, 0x68, 0x0A, 0x01,
+ 0x41, 0x30, 0x37, 0x35, 0x68, 0x0A, 0x00, 0x70,
+ 0x0A, 0x01, 0x62, 0x70, 0x0A, 0x00, 0x63, 0xA0,
+ 0x31, 0x93, 0x62, 0x0A, 0x01, 0x7B, 0x41, 0x30,
+ 0x35, 0x33, 0x68, 0x0A, 0xA5, 0x0A, 0x3F, 0x61,
+ 0xA0, 0x0E, 0x94, 0x61, 0x0A, 0x04, 0x70, 0x0A,
+ 0x02, 0x62, 0x70, 0x0A, 0x00, 0x63, 0x9F, 0xA0,
+ 0x0B, 0x95, 0x63, 0x0A, 0x50, 0x5B, 0x22, 0x0A,
+ 0x01, 0x75, 0x63, 0xA1, 0x05, 0x70, 0x0A, 0x04,
+ 0x62, 0xA0, 0x4C, 0x06, 0x93, 0x62, 0x0A, 0x02,
+ 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, 0x0A, 0xA5,
+ 0x61, 0x7B, 0x61, 0x0A, 0x3F, 0x61, 0xA0, 0x0A,
+ 0x93, 0x61, 0x0A, 0x10, 0x70, 0x0A, 0x05, 0x62,
+ 0x9F, 0xA0, 0x0C, 0x95, 0x63, 0x0A, 0x50, 0x5B,
+ 0x22, 0x0A, 0x01, 0x75, 0x63, 0x9F, 0x70, 0x0A,
+ 0x04, 0x62, 0xA0, 0x0D, 0x93, 0x83, 0x88, 0x41,
+ 0x30, 0x31, 0x34, 0x68, 0x00, 0x0A, 0x01, 0x9F,
+ 0xA0, 0x2D, 0x93, 0x41, 0x30, 0x37, 0x36, 0x68,
+ 0x0A, 0x01, 0x41, 0x30, 0x35, 0x30, 0x68, 0x0A,
+ 0xA2, 0x80, 0x0B, 0x00, 0x20, 0x00, 0x0B, 0x00,
+ 0x20, 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30, 0x31,
+ 0x34, 0x68, 0x00, 0x41, 0x30, 0x34, 0x39, 0x68,
+ 0x0A, 0x01, 0x70, 0x0A, 0x07, 0x62, 0xA0, 0x21,
+ 0x93, 0x62, 0x0A, 0x04, 0x41, 0x30, 0x37, 0x35,
+ 0x68, 0x0A, 0x01, 0x41, 0x30, 0x37, 0x34, 0x68,
+ 0x0A, 0x00, 0x70, 0x0A, 0x01, 0x88, 0x41, 0x30,
+ 0x31, 0x34, 0x68, 0x00, 0x70, 0x0A, 0x00, 0x62,
+ 0xA0, 0x4C, 0x04, 0x93, 0x62, 0x0A, 0x07, 0xA0,
+ 0x41, 0x04, 0x5B, 0x12, 0x5C, 0x2E, 0x5F, 0x53,
+ 0x42, 0x5F, 0x41, 0x4C, 0x49, 0x43, 0x66, 0x70,
+ 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03,
+ 0x00, 0x61, 0x5C, 0x2E, 0x5F, 0x53, 0x42, 0x5F,
+ 0x41, 0x4C, 0x49, 0x43, 0x61, 0x0A, 0x00, 0x5B,
+ 0x22, 0x0A, 0x02, 0x5C, 0x2E, 0x5F, 0x53, 0x42,
+ 0x5F, 0x41, 0x4C, 0x49, 0x43, 0x61, 0x0A, 0x01,
+ 0x70, 0x0A, 0x00, 0x63, 0x70, 0x0A, 0x01, 0x62,
+ 0x9F, 0x70, 0x0A, 0x04, 0x62, 0xA0, 0x14, 0x93,
+ 0x62, 0x0A, 0x05, 0x70, 0x0A, 0x01, 0x64, 0x70,
+ 0x0A, 0x00, 0x62, 0x41, 0x30, 0x37, 0x34, 0x68,
+ 0x0A, 0x02, 0xA0, 0x14, 0x93, 0x62, 0x0A, 0x00,
+ 0x70, 0x0A, 0x01, 0x41, 0x30, 0x31, 0x37, 0x41,
+ 0x30, 0x32, 0x39, 0x70, 0x0A, 0x08, 0x62, 0xA4,
+ 0x64, 0x14, 0x45, 0x0A, 0x41, 0x30, 0x37, 0x34,
+ 0x0A, 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67,
+ 0x70, 0x83, 0x88, 0x67, 0x0A, 0x02, 0x00, 0x41,
+ 0x30, 0x36, 0x32, 0x70, 0x83, 0x88, 0x67, 0x0A,
+ 0x03, 0x00, 0x41, 0x30, 0x36, 0x33, 0xA0, 0x14,
+ 0x93, 0x69, 0x0A, 0x00, 0x41, 0x30, 0x37, 0x37,
+ 0x68, 0x41, 0x30, 0x36, 0x32, 0x41, 0x30, 0x36,
+ 0x33, 0x0A, 0x01, 0xA0, 0x14, 0x93, 0x69, 0x0A,
+ 0x01, 0x41, 0x30, 0x37, 0x37, 0x68, 0x41, 0x30,
+ 0x36, 0x32, 0x41, 0x30, 0x36, 0x33, 0x0A, 0x00,
+ 0xA0, 0x09, 0x92, 0x93, 0x69, 0x0A, 0x02, 0xA4,
+ 0x0A, 0x00, 0x70, 0x41, 0x30, 0x37, 0x38, 0x68,
+ 0x0A, 0x00, 0x62, 0xA0, 0x0E, 0x92, 0x94, 0x41,
+ 0x30, 0x37, 0x38, 0x68, 0x0A, 0x01, 0x62, 0xA4,
+ 0x0A, 0x00, 0x70, 0x41, 0x30, 0x37, 0x39, 0x68,
+ 0x61, 0xA0, 0x12, 0x93, 0x61, 0x0A, 0x00, 0x72,
+ 0x41, 0x30, 0x36, 0x32, 0x62, 0x63, 0x70, 0x41,
+ 0x30, 0x36, 0x33, 0x64, 0xA1, 0x0E, 0x74, 0x41,
+ 0x30, 0x36, 0x33, 0x62, 0x64, 0x70, 0x41, 0x30,
+ 0x36, 0x32, 0x63, 0x41, 0x30, 0x37, 0x37, 0x68,
+ 0x63, 0x64, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14,
+ 0x40, 0x09, 0x41, 0x30, 0x37, 0x36, 0x01, 0x70,
+ 0x11, 0x03, 0x0A, 0x10, 0x61, 0x70, 0x0A, 0x00,
+ 0x60, 0xA2, 0x45, 0x05, 0x92, 0x94, 0x60, 0x0A,
+ 0x03, 0x70, 0x41, 0x30, 0x35, 0x33, 0x68, 0x72,
+ 0x60, 0x0A, 0xA5, 0x00, 0x62, 0x70, 0x62, 0x88,
+ 0x61, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x00, 0x70,
+ 0x7A, 0x62, 0x0A, 0x08, 0x00, 0x88, 0x61, 0x72,
+ 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A, 0x01, 0x00,
+ 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x10, 0x00, 0x88,
+ 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04, 0x00, 0x0A,
+ 0x02, 0x00, 0x00, 0x70, 0x7A, 0x62, 0x0A, 0x18,
+ 0x00, 0x88, 0x61, 0x72, 0x77, 0x60, 0x0A, 0x04,
+ 0x00, 0x0A, 0x03, 0x00, 0x00, 0x75, 0x60, 0x70,
+ 0x0A, 0x00, 0x60, 0xA2, 0x21, 0x95, 0x60, 0x0A,
+ 0x0F, 0xA0, 0x19, 0x90, 0x93, 0x83, 0x88, 0x61,
+ 0x60, 0x00, 0x0A, 0x2A, 0x93, 0x83, 0x88, 0x61,
+ 0x72, 0x60, 0x0A, 0x01, 0x00, 0x00, 0x0A, 0x09,
+ 0xA4, 0x0A, 0x01, 0x75, 0x60, 0xA4, 0x0A, 0x00,
+ 0x14, 0x4B, 0x04, 0x41, 0x30, 0x37, 0x39, 0x09,
+ 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70,
+ 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30,
+ 0x36, 0x30, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01,
+ 0x00, 0x41, 0x30, 0x36, 0x31, 0x70, 0x0A, 0x00,
+ 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x36, 0x30,
+ 0x41, 0x30, 0x36, 0x31, 0x70, 0x0A, 0x01, 0x60,
+ 0x7B, 0x41, 0x30, 0x35, 0x33, 0x68, 0x0A, 0x50,
+ 0x0A, 0x01, 0x61, 0xA4, 0x7B, 0x7F, 0x60, 0x61,
+ 0x00, 0x0A, 0x01, 0x00, 0x14, 0x49, 0x05, 0x41,
+ 0x30, 0x37, 0x35, 0x02, 0x70, 0x41, 0x30, 0x37,
+ 0x33, 0x68, 0x67, 0x70, 0x83, 0x88, 0x67, 0x0A,
+ 0x04, 0x00, 0x41, 0x30, 0x36, 0x35, 0x70, 0x7D,
+ 0x79, 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A,
+ 0x01, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88,
+ 0x67, 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x36,
+ 0x34, 0x41, 0x30, 0x32, 0x38, 0x0A, 0x00, 0x0A,
+ 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x36, 0x34, 0x0A,
+ 0x10, 0x00, 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B,
+ 0x00, 0x01, 0x41, 0x30, 0x36, 0x35, 0x00, 0x00,
+ 0x00, 0x80, 0x0A, 0x01, 0x00, 0x69, 0x08, 0x41,
+ 0x30, 0x38, 0x30, 0x11, 0x0A, 0x0A, 0x07, 0x00,
+ 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x4B,
+ 0x06, 0x41, 0x30, 0x37, 0x38, 0x02, 0xA0, 0x1E,
+ 0x93, 0x69, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30,
+ 0x35, 0x33, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00,
+ 0x0A, 0x07, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30,
+ 0x38, 0x30, 0x60, 0x00, 0x61, 0xA1, 0x42, 0x04,
+ 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70,
+ 0x83, 0x88, 0x67, 0x0A, 0x00, 0x00, 0x41, 0x30,
+ 0x36, 0x30, 0x70, 0x83, 0x88, 0x67, 0x0A, 0x01,
+ 0x00, 0x41, 0x30, 0x36, 0x31, 0xA0, 0x14, 0x94,
+ 0x41, 0x30, 0x36, 0x30, 0x41, 0x30, 0x36, 0x31,
+ 0x74, 0x41, 0x30, 0x36, 0x30, 0x41, 0x30, 0x36,
+ 0x31, 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x36,
+ 0x31, 0x41, 0x30, 0x36, 0x30, 0x61, 0x75, 0x61,
+ 0xA4, 0x61, 0x14, 0x4C, 0x09, 0x41, 0x30, 0x37,
+ 0x37, 0x0C, 0x70, 0x41, 0x30, 0x37, 0x33, 0x68,
+ 0x67, 0x70, 0x69, 0x41, 0x30, 0x36, 0x32, 0x70,
+ 0x6A, 0x41, 0x30, 0x36, 0x33, 0x70, 0x7D, 0x79,
+ 0x83, 0x88, 0x67, 0x72, 0x0A, 0x05, 0x0A, 0x01,
+ 0x00, 0x00, 0x0A, 0x08, 0x00, 0x83, 0x88, 0x67,
+ 0x0A, 0x05, 0x00, 0x00, 0x41, 0x30, 0x36, 0x34,
+ 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x36, 0x32, 0x41,
+ 0x30, 0x36, 0x33, 0x74, 0x41, 0x30, 0x36, 0x32,
+ 0x41, 0x30, 0x36, 0x33, 0x61, 0x70, 0x41, 0x30,
+ 0x36, 0x33, 0x62, 0xA1, 0x11, 0x74, 0x41, 0x30,
+ 0x36, 0x33, 0x41, 0x30, 0x36, 0x32, 0x61, 0x70,
+ 0x41, 0x30, 0x36, 0x32, 0x62, 0x79, 0x74, 0x79,
+ 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, 0x00, 0x00,
+ 0x0A, 0x01, 0x00, 0x62, 0x63, 0x70, 0x80, 0x63,
+ 0x00, 0x64, 0xA0, 0x09, 0x93, 0x6B, 0x0A, 0x01,
+ 0x70, 0x0A, 0x00, 0x63, 0x41, 0x30, 0x32, 0x38,
+ 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30,
+ 0x36, 0x34, 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80,
+ 0x00, 0x64, 0x63, 0x5B, 0x21, 0x0A, 0x0A, 0x14,
+ 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02, 0x70,
+ 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84, 0x60,
+ 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, 0x0A,
+ 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, 0x68,
+ 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, 0xFF,
+ 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, 0xA1,
+ 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00, 0x7B,
+ 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, 0x7D,
+ 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, 0x60,
+ 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, 0x60,
+ 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34, 0x0B,
+ 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30, 0x30,
+ 0x35, 0x01, 0x08, 0x41, 0x44, 0x30, 0x42, 0x0A,
+ 0x00, 0x14, 0x44, 0x04, 0x41, 0x30, 0x30, 0x36,
+ 0x01, 0xA0, 0x3C, 0x93, 0x41, 0x44, 0x30, 0x42,
+ 0x0A, 0x01, 0x70, 0x7D, 0x79, 0x0A, 0x18, 0x0A,
+ 0x03, 0x00, 0x0A, 0x04, 0x00, 0x61, 0x70, 0x41,
+ 0x30, 0x30, 0x37, 0x61, 0x0B, 0x5C, 0x01, 0x62,
+ 0xA0, 0x0A, 0x93, 0x68, 0x0A, 0x00, 0x7D, 0x62,
+ 0x0A, 0x01, 0x62, 0xA1, 0x09, 0x7B, 0x62, 0x0C,
+ 0xFC, 0xFF, 0xFF, 0xFF, 0x62, 0x41, 0x30, 0x30,
+ 0x38, 0x61, 0x0B, 0x5C, 0x01, 0x62
};
#endif
#include "amdlib.h"
#include "Gnb.h"
#include "GnbPcie.h"
+#include "GnbPcieFamServices.h"
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include "OntarioDefinitions.h"
#include "OntarioComplexData.h"
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include "OntarioDefinitions.h"
+#include "GnbPcieFamServices.h"
+#include "PcieFamilyServices.h"
#include "GnbRegistersON.h"
#include "NbSmuLib.h"
#include "Filecode.h"
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+PcieFmPhyLetPllPersonalityInit (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+PcieFmPhyChannelCharacteristic (
+ IN PCIe_ENGINE_CONFIG *Engine,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+PcieFmAvertClockPickers (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+PcieFmPhyApplyGanging (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+VOID
+PcieFmPifSetRxDetectPowerMode (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
/*----------------------------------------------------------------------------------------*/
/**
#include "GnbPcie.h"
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
+#include "PcieFamilyServices.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include "PcieMiscLib.h"
+#include "GnbPcieFamServices.h"
#include "OntarioDefinitions.h"
#include "GnbRegistersON.h"
#include "NbSmuLib.h"
IN PCIe_PLATFORM_CONFIG *Pcie
);
+AGESA_STATUS
+PcieOnGetGppConfigurationValue (
+ IN UINT64 ConfigurationSignature,
+ OUT UINT8 *ConfigurationValue
+ );
+
/*----------------------------------------------------------------------------------------
* T A B L E S
*----------------------------------------------------------------------------------------
*/
PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = {
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6440_ADDRESS),
+ D0F0xE4_PHY_6440_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6440_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6480_ADDRESS),
+ D0F0xE4_PHY_6480_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6480_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6500_ADDRESS),
+ D0F0xE4_PHY_6500_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6500_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6600_ADDRESS),
+ D0F0xE4_PHY_6600_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6600_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6840_ADDRESS),
+ D0F0xE4_PHY_6840_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6840_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6880_ADDRESS),
+ D0F0xE4_PHY_6880_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6880_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6900_ADDRESS),
+ D0F0xE4_PHY_6900_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6900_RxInCalForce_OFFSET
+ },
+ {
+ PHY_SPACE (0, 0, D0F0xE4_PHY_6A00_ADDRESS),
+ D0F0xE4_PHY_6A00_RxInCalForce_MASK,
+ 0x1 << D0F0xE4_PHY_6A00_RxInCalForce_OFFSET
+ },
{
WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
//4 5 6 7 8 (SB)
- 4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3,
- 4, 4, 5, 5, 6, 6, 7, 7, 0, 3
+ {4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
+ {4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
+ {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
+ {4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3},
+ {4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3},
+ {4, 4, 5, 5, 6, 6, 7, 7, 0, 3}
};
CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = {
//4 5 6 7 8 (SB)
- 1, 2, 3, 4, 0,
- 1, 2, 3, 4, 0,
- 1, 3, 2, 4, 0,
- 1, 2, 3, 4, 0,
- 1, 4, 2, 3, 0,
- 1, 2, 3, 4, 0
+ {1, 2, 3, 4, 0},
+ {1, 2, 3, 4, 0},
+ {1, 3, 2, 4, 0},
+ {1, 2, 3, 4, 0},
+ {1, 4, 2, 3, 0},
+ {1, 2, 3, 4, 0}
};
/*----------------------------------------------------------------------------------------*/
CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
- 0, 3, 4, 7, 8, 11
+ {0, 3, 4, 7, 8, 11}
};
/*----------------------------------------------------------------------------------------*/
LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
}
if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
- if (Pcie->PsppPolicy == PsppBalanceLow) {
+ if (Pcie->PsppPolicy == PsppBalanceLow || Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
LinkSpeedCapability = PcieGen1;
}
}
{
switch (ConfigurationValue) {
case 4:
- return "1x4, 4x1";
+ return (CONST CHAR8*)"1x4, 4x1";
case 3:
- return "1x4, 1x2, 2x1";
+ return (CONST CHAR8*)"1x4, 1x2, 2x1";
case 2:
- return "1x4, 2x2";
+ return (CONST CHAR8*)"1x4, 2x2";
case 1:
- return "1x4, 1x4";
+ return (CONST CHAR8*)"1x4, 1x4";
default:
break;
}
- return " !!! Something Wrong !!!";
+ return (CONST CHAR8*)" !!! Something Wrong !!!";
}
/*----------------------------------------------------------------------------------------*/
{
switch (Wrapper->WrapId) {
case GPP_WRAP_ID:
- return "GPPSB";
+ return (CONST CHAR8*)"GPPSB";
case DDI_WRAP_ID:
- return "Virtual DDI";
+ return (CONST CHAR8*)"Virtual DDI";
default:
break;
}
- return " !!! Something Wrong !!!";
+ return (CONST CHAR8*)" !!! Something Wrong !!!";
}
/*----------------------------------------------------------------------------------------*/
{
switch (AddressFrame) {
case 0x130:
- return "GPP WRAP";
+ return (CONST CHAR8*)"GPP WRAP";
case 0x110:
- return "GPP PIF0";
+ return (CONST CHAR8*)"GPP PIF0";
case 0x120:
- return "GPP PHY0";
+ return (CONST CHAR8*)"GPP PHY0";
case 0x101:
- return "GPP CORE";
+ return (CONST CHAR8*)"GPP CORE";
default:
break;
}
- return " !!! Something Wrong !!!";
+ return (CONST CHAR8*)" !!! Something Wrong !!!";
}
{
DESCRIPTOR_TERMINATE_LIST,
{0},
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)),
NULL
},
//Gpp Wrapper
1, //TxclkGatingPllPowerDown
1 //PllOffInL1
},
- offsetof (F14_COMPLEX_CONFIG, Port4),
- offsetof (F14_COMPLEX_CONFIG, Silicon),
- offsetof (F14_COMPLEX_CONFIG, FmGppWrapper)
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, Port4)),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, Silicon)),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, FmGppWrapper))
},
//Virtual DDI Wrapper
{
1, //TxclkGatingPllPowerDown
0 //PllOffInL1
},
- offsetof (F14_COMPLEX_CONFIG, Dpa),
- offsetof (F14_COMPLEX_CONFIG, Silicon),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, Dpa)),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, Silicon)),
NULL
},
//Port 4
{
DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)),
{ PciePortEngine, 4, 4},
0, //Initialization Status
0xFF, //Scratch
0,
GPP_CORE_ID,
1,
- 0,
+ {0},
FALSE,
LinkStateResetExit
},
//Port 5
{
DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)),
{ PciePortEngine, 5, 5},
0, //Initialization Status
0xFF, //Scratch
0,
GPP_CORE_ID,
2,
- 0,
+ {0},
FALSE,
LinkStateResetExit
},
//Port 6
{
DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)),
{ PciePortEngine, 6, 6 },
0, //Initialization Status
0xFF, //Scratch
0,
GPP_CORE_ID,
3,
- 0,
+ {0},
FALSE,
LinkStateResetExit
},
//Port 7
{
DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)),
{ PciePortEngine, 7, 7 },
0, //Initialization Status
0xFF, //Scratch
0,
GPP_CORE_ID,
4,
- 0,
+ {0},
FALSE,
LinkStateResetExit
},
//Port 8
{
DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, GppWrapper)),
{ PciePortEngine, 0, 3 },
0, //Initialization Status
0xFF, //Scratch
0,
GPP_CORE_ID,
0,
- MAKE_SBDFO (0, 0, 8, 0, 0),
+ {MAKE_SBDFO (0, 0, 8, 0, 0)},
TRUE,
LinkStateTrainingSuccess
},
//Virtual DpA
{
DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
- offsetof (F14_COMPLEX_CONFIG, DdiWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)),
{PcieDdiEngine},
0, //Initialization Status
0xFF, //Scratch
//Virtual DpB
{
DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
- offsetof (F14_COMPLEX_CONFIG, DdiWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)),
{PcieDdiEngine},
0, //Initialization Status
0xFF, //Scratch
//Virtual VGA
{
DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST,
- offsetof (F14_COMPLEX_CONFIG, DdiWrapper),
+ (VOID *)(offsetof (F14_COMPLEX_CONFIG, DdiWrapper)),
{PcieDdiEngine},
0, //Initialization Status
0xFF, //Scratch
*----------------------------------------------------------------------------------------
*/
+VOID
+PcieCommonCoreInit (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+AGESA_STATUS
+PcieInitSrbmCallback (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+AGESA_STATUS
+PcieInitCallback (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+AGESA_STATUS
+PciePostInitCallback (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
/*----------------------------------------------------------------------------------------*/
/**
*
*/
-#ifndef _PCIEINITATPOST_H_
-#define _PCIEINITATPOST_H_
+#ifndef _PCIEINITATENV_H_
+#define _PCIEINITATENV_H_
AGESA_STATUS
PcieInitAtEnv (
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
+AGESA_STATUS
+PcieInitAtPostEarly (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+PcieInitAtPost (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+PcieInitAtPostS3 (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+PcieLateRestoreS3Script (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINT16 ContextLength,
+ IN VOID* Context
+ );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init prior DRAM init
+ *
+ *
+ *
+ * @param[in] StdHeader Standard configuration header
+ * @retval AGESA_STATUS
+ */
+AGESA_STATUS
+PcieInitAtPostEarly (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ AGESA_STATUS AgesaStatus;
+ AGESA_STATUS Status;
+ PCIe_PLATFORM_CONFIG *Pcie;
+ IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Enter\n");
+ AgesaStatus = AGESA_SUCCESS;
+ Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ if (Status == AGESA_SUCCESS) {
+ PciePortsVisibilityControl (UnhidePorts, Pcie);
+
+ Status = PciePortPostEarlyInit (Pcie);
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ ASSERT (Status == AGESA_SUCCESS);
+
+ Status = PcieTraining (Pcie);
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ ASSERT (Status == AGESA_SUCCESS);
+
+ PciePortsVisibilityControl (HidePorts, Pcie);
+ }
+ IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostEarly Exit [0x%x]\n", AgesaStatus);
+ return AgesaStatus;
+}
/*----------------------------------------------------------------------------------------*/
/**
}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIe Post Init
+ *
+ *
+ *
+ * @param[in] StdHeader Standard configuration header
+ * @retval AGESA_STATUS
+ */
+AGESA_STATUS
+PcieInitAtPostS3 (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ AGESA_STATUS AgesaStatus;
+ AGESA_STATUS Status;
+ PCIe_PLATFORM_CONFIG *Pcie;
+ IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Enter\n");
+ AgesaStatus = AGESA_SUCCESS;
+ Status = PcieLocateConfigurationData (StdHeader, &Pcie);
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ if (Status == AGESA_SUCCESS) {
+ PciePortsVisibilityControl (UnhidePorts, Pcie);
+
+ Status = PciePostInit (Pcie);
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ ASSERT (Status == AGESA_SUCCESS);
+
+ if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+ Status = PciePortPostS3Init (Pcie);
+ } else {
+ Status = PciePortPostInit (Pcie);
+ }
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ ASSERT (Status == AGESA_SUCCESS);
+
+ Status = PcieTraining (Pcie);
+ AGESA_STATUS_UPDATE (Status, AgesaStatus);
+ ASSERT (Status == AGESA_SUCCESS);
+
+ PciePortsVisibilityControl (HidePorts, Pcie);
+ }
+ IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPostS3 Exit [0x%x]\n", AgesaStatus);
+ return AgesaStatus;
+}
+
/*----------------------------------------------------------------------------------------*/
/**
* PCIe S3 restore
IN VOID* Context
)
{
- PcieInitAtPost (StdHeader);
+ PcieInitAtPostS3 (StdHeader);
}
*----------------------------------------------------------------------------------------
*/
+VOID
+PciePwrPowerDownPllInL1 (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+AGESA_STATUS
+PcieLateInitCallback (
+ IN PCIe_WRAPPER_CONFIG *Wrapper,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
/*----------------------------------------------------------------------------------------*/
/**
#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
+#include "PcieMiscLib.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_PCIE_PCIEMISCLIB_FILECODE
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1)
+#include "PciePortInit.h"
#include "GnbRegistersON.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE
ASSERT (Engine->Type.Port.IsSB == FALSE);
PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
+ // Train port that forced to compliance in last stage of training
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
+ // Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
+ if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+ Pcie->TrainingExitState = LinkStateResetExit;
+ }
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PciePortInitCallback,
}
LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie);
PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
+ // Retrain only present port to Gen2
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) {
PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie);
PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
}
+ // Train ports forced to compliance
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieForceCompliance (Engine, Pcie);
PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
);
return Status;
}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Callback to init various features on all ports on S3 resume path
+ *
+ *
+ *
+ *
+ * @param[in] Engine Pointer to engine config descriptor
+ * @param[in, out] Buffer Not used
+ * @param[in] Pcie Pointer to global PCIe configuration
+ *
+ */
+
+VOID
+STATIC
+PciePortPostS3InitCallback (
+ IN PCIe_ENGINE_CONFIG *Engine,
+ IN OUT VOID *Buffer,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ )
+{
+ PCIE_LINK_SPEED_CAP LinkSpeedCapability;
+ ASSERT (Engine->EngineData.EngineType == PciePortEngine);
+ LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie);
+ PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
+ if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
+ PcieLinkSafeMode (Engine, Pcie);
+ }
+ if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
+ PcieForceCompliance (Engine, Pcie);
+ }
+ if (!Engine->Type.Port.IsSB) {
+ if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
+ ((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) ||
+ (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) {
+ PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
+ } else {
+ PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
+ }
+ PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
+ } else {
+ PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
+ }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init port on S3 resume during destributed training
+ *
+ *
+ *
+ *
+ * @param[in] Pcie Pointer to global PCIe configuration
+ * @retval AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+PciePortPostS3Init (
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ )
+{
+ AGESA_STATUS Status;
+ Status = AGESA_SUCCESS;
+ PcieConfigRunProcForAllEngines (
+ DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+ PciePortPostS3InitCallback,
+ NULL,
+ Pcie
+ );
+ return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Master procedure to init various features on all active ports
+ *
+ *
+ *
+ *
+ * @param[in] Pcie Pointer to global PCIe configuration
+ * @retval AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+PciePortPostEarlyInit (
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ )
+{
+ AGESA_STATUS Status;
+ Status = AGESA_SUCCESS;
+ // Distributed Training started at PciePortInit complete it now to get access to PCIe devices
+ if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
+ Pcie->TrainingExitState = LinkStateTrainingCompleted;
+ }
+ return Status;
+}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
IN PCIe_PLATFORM_CONFIG *Pcie
);
+AGESA_STATUS
+PciePortPostEarlyInit (
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+AGESA_STATUS
+PciePortPostS3Init (
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
#endif
*----------------------------------------------------------------------------------------
*/
+VOID
+PcieSlotPowerLimit (
+ IN PCIe_ENGINE_CONFIG *Engine,
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+AGESA_STATUS
+PciePortLateInit (
+ IN PCIe_PLATFORM_CONFIG *Pcie
+ );
+
+
PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = {
{
DxF0xE4_xA2_ADDRESS,
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
(PF_MAKE_LINK_BASE)CommonReturnZero32,
(PF_GET_MODULE_INFO)CommonVoid,
(PF_POST_MAILBOX)CommonVoid,
- //(PF_RETRIEVE_MAILBOX)CommonReturnZero32,
- Fam14RetrieveMailbox,
+ (PF_RETRIEVE_MAILBOX)CommonReturnZero32,
(PF_GET_SOCKET)CommonReturnZero8,
(PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
(PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
return (1);
}
-AP_MAIL_INFO
-Fam14RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- AP_MAIL_INFO NodeApMailBox;
- ASSERT (Nb != NULL);
- NodeApMailBox.Info = 0;
- return NodeApMailBox;
-}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 44325 $ @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
IN NORTHBRIDGE *Nb
);
-AP_MAIL_INFO
-Fam14RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
#endif // _HT_NB_UTILITIES_FAM14_H_
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
- * @e \$Revision: 35777 $ @e \$Date: 2010-07-30 17:41:05 +0800 (Fri, 30 Jul 2010) $
+ * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
IN OUT MEM_NB_BLOCK *NBPtr
);
+BOOLEAN
+MemFUndoInterleaveBanks (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
VOID
STATIC
CsIntSwap (
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Main)
- * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $
*
**/
/*
*----------------------------------------------------------------------------
*/
+BOOLEAN
+MemFDMISupport3 (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
+BOOLEAN
+MemFDMISupport2 (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
// Form Factor (offset 0Eh)
FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
- if ((FormFactor & 0x20) == 4) {
+ if ((FormFactor & 0x04) == 4) {
DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM
} else {
DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM
*----------------------------------------------------------------------------
*/
+BOOLEAN
+MemFCheckECC (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
+/*
UINT32
STATIC
MemFGetScrubAddr (
IN OUT MEM_NB_BLOCK *NBPtr
);
+*/
VOID
STATIC
* @return Scrubber Address
*/
+/*
UINT32
STATIC
MemFGetScrubAddr (
}
return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
}
-
+*/
*----------------------------------------------------------------------------
*/
BOOLEAN
+MemFInitEMP (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
+BOOLEAN
STATIC
IsPowerOfTwo (
IN UINT32 TestNumber
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Feat/EXCLUDIMM)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
*----------------------------------------------------------------------------
*/
+BOOLEAN
+MemFRASExcludeDIMM (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
IsCSIntlvEnabled = TRUE;
}
+ Flag = TRUE;
+ NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
NBPtr->SwitchDCT (NBPtr, Dct);
if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
}
}
}
+ Flag = FALSE;
+ NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
// Re-enable chip select interleaving when remapping is done.
if (IsCSIntlvEnabled) {
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Feat)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $
*
**/
/*
// NB block has already been constructed by main block.
// No need to construct it here.
NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+ mmData.NBPtr = NBPtr;
} else {
AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
ASSERT (Count <= 1000000);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader);
LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
*----------------------------------------------------------------------------
*/
+AGESA_STATUS
+MemMFlowON (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*/
#include "AGESA.h"
+#include "AdvancedApi.h"
#include "Filecode.h"
#include "mm.h"
CODE_GROUP (G1_PEICC)
*----------------------------------------------------------------------------
*/
+AGESA_STATUS
+MemMFlowDef (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
#include "AGESA.h"
#include "amdlib.h"
+#include "AdvancedApi.h"
#include "mu.h"
#include "OptionMemory.h"
#include "Ids.h"
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMEcc (
+ IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMRASExcludeDIMM (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
// Only when TOM is set can CpuMemTyping be re-run
- if (SMsr.hi == SMsr.lo == 0) {
+ if ((SMsr.hi == 0) && (SMsr.lo == 0)) {
if (RefPtr->SysLimit != 0) {
NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
}
#include "OptionMemory.h"
#include "mm.h"
#include "mn.h"
+#include "mmlvddr3.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMLvDdr3 (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMMctMemClr (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
/* -----------------------------------------------------------------------------*/
/**
*
*----------------------------------------------------------------------------
*/
+VOID
+MemMContextSave (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
BOOLEAN
STATIC
MemMRestoreDqsTimings (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr,
OUT S3_MEM_NB_BLOCK **S3NBPtr
);
+
+BOOLEAN
+MemMContextRestore (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/*-----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
DEVICE_BLOCK_HEADER *DeviceList;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 BufferSize;
- UINT64 BufferOffset;
+ VOID *BufferOffset;
MEM_NB_BLOCK *NBArray;
S3_MEM_NB_BLOCK *S3NBPtr;
DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
// Copy device list on the stack to the heap.
- BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+// BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+ BufferOffset = AllocHeapParams.BufferPtr + sizeof (DEVICE_BLOCK_HEADER);
for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
// Copy PCI device descriptor to the heap if it exists.
if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
DeviceList->NumDevices ++;
BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
}
// Copy conditional PCI device descriptor to the heap if it exists.
if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
DeviceList->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
}
// Copy MSR device descriptor to the heap if it exists.
if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ( BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
DeviceList->NumDevices ++;
BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
}
// Copy conditional MSR device descriptor to the heap if it exists.
if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+ LibAmdMemCopy ( BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
DeviceList->NumDevices ++;
BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
}
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMInterleaveNodes (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMOnlineSpare (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
*
*-----------------------------------------------------------------------------
*/
+
+BOOLEAN
+MemMParallelTraining (
+ IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
*
*-----------------------------------------------------------------------------
*/
+BOOLEAN
+MemMStandardTraining (
+ IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
+ );
/* -----------------------------------------------------------------------------*/
/**
*
*----------------------------------------------------------------------------
*/
+
+BOOLEAN
+MemMUmaAlloc (
+ IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
+ );
+
/*-----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "OptionMemory.h"
+#include "AdvancedApi.h"
#include "mm.h"
#include "mn.h"
#include "mt.h"
//----------------------------------------------------------------------------
// Get TSC rate, which will be used later in Wait10ns routine
//----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader);
//----------------------------------------------------------------------------
}
}
} else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, NULL, NULL, NULL, NULL, &MemPtr->StdHeader);
+ PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader);
//
// Assert here if unable to allocate heap for SPDs
//
#include "AGESA.h"
#include "amdlib.h"
+#include "mu.h"
#include "Filecode.h"
/*----------------------------------------------------------------------------------------
*----------------------------------------------------------------------------------------
*/
+/*
VOID
MemUWriteCachelines (
IN UINT32 Address,
AlignPointerTo16Byte (
IN OUT UINT8 **BufferPtrPtr
);
-
+*/
+
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
CACHE_INFO *CacheInfoPtr;
- GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader);
+ GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader);
return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
}
//----------------------------------------------------------------------------
// Get TSC rate of the this AP
//----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
return TRUE;
//----------------------------------------------------------------------------
// Get TSC rate of the this AP
//----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
return TRUE;
FamilySpecificServices = NULL;
DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
- GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
+ GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100; // Calculate the Nb P1 frequency (NbFreq / 2)
for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
//----------------------------------------------------------------------------
// Get TSC rate of the this AP
//----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
return TRUE;
//----------------------------------------------------------------------------
// Get TSC rate of the this AP
//----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
return TRUE;
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT DESCRIPTOR_GROUP *DescriptPtr
);
+
+BOOLEAN
+MemS3ResumeConstructNBBlockON (
+ IN OUT VOID *S3NBPtr,
+ IN OUT MEM_DATA_STRUCT *MemPtr,
+ IN UINT8 NodeID
+ );
+
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
{{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018},
// 4. Frequency Change
{{4, 3, 1}, DCT0, BFPllLockTime, 0},
+ {{1, 2, 1}, DCT0, BFDllCSRBisaTrimDByte, 0x7000},
+ {{1, 2, 1}, DCT0, BFDllCSRBisaTrimClk, 0x7000},
+ {{1, 2, 1}, DCT0, BFDllCSRBisaTrimCsOdt, 0x7000},
+ {{1, 2, 1}, DCT0, BFDllCSRBisaTrimAByte2, 0x7000},
+ {{1, 2, 1}, DCT0, BFReduceLoop, 0x6000},
{{0, 0, 0}, FUNC_2, 0x94, 0xFFD1CC1F},
// NB Pstate Related Register for Pstate 0
{{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF},
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
}
- MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1);
+ MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, (((MemNGetBitFieldNb (NBPtr, BFLowPowerDefault)) == 1) && (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife)) ? 0 : 1);
MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE);
if (Status) {
// When NB frequency change succeeds, TSC rate may have changed.
// We need to update TSC rate
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+ GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
}
return Status;
MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20);
}
return TRUE;
-}
\ No newline at end of file
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ * This function sets reduceloop and trim value for DDR-1333 for C0
+ *
+ * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
+ * @param[in,out] OptParam - Optional parameter
+ *
+ * @return TRUE
+ *
+ */
+
+BOOLEAN
+MemNBeforeMemClkFreqValON (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *OptParam
+ )
+{
+ if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) != 0)) {
+ MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimDByte, 0x7000);
+ MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimClk, 0x7000);
+ MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimCsOdt, 0x7000);
+ MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimAByte2, 0x7000);
+ MemNBrdcstSetNb (NBPtr, BFReduceLoop, 0x6000);
+ }
+ return TRUE;
+}
#include "OptionMemory.h"
#include "mm.h"
#include "mn.h"
+#include "mnon.h"
#include "mt.h"
#include "Filecode.h"
#include "GeneralServices.h"
*/
+BOOLEAN
+MemNIdentifyDimmConstructorON (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT MEM_DATA_STRUCT *MemPtr,
+ IN UINT8 NodeID
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
NBPtr->TechBlockSwitch = MemNTechBlockSwitchON;
NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW];
+ NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) memNTrainFlowControl[DDR3_TRAIN_FLOW];
NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
NBPtr->PollBitField = MemNPollBitFieldNb;
NBPtr->BrdcstCheck = MemNBrdcstCheckON;
NBPtr->IsSupported[AdjustTwr] = TRUE;
NBPtr->IsSupported[UnifiedNbFence] = TRUE;
NBPtr->IsSupported[ChannelPDMode] = TRUE; // Erratum 435
+ if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_C0) != 0) {
+ NBPtr->IsSupported[AdjustTrc] = TRUE;
+ }
NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON;
NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb;
NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb;
+ if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
+ // Do not do phase B enforcement for Rev C
NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON;
+ }
NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON;
NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON;
+ NBPtr->FamilySpecificHook[BfAfExcludeDimm] = MemNBfAfExcludeDimmClientNb;
+ NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] = MemNBeforeMemClkFreqValON;
FeatPtr->InitCPG (NBPtr);
FeatPtr->InitEarlySampleSupport (NBPtr);
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem)
- * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
IN OUT VOID *OptParam
);
+BOOLEAN
+MemNBeforeMemClkFreqValON (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *OptParam
+ );
+
BOOLEAN
MemNResetRxFifoPtrON (
IN OUT MEM_NB_BLOCK *NBPtr,
*
*-----------------------------------------------------------------------------
*/
+VOID
+MemNInitEarlySampleSupportON (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
/* -----------------------------------------------------------------------------*/
/**
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 0, BFAcpiPwrStsCtrlHi);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1FC), 2, 2, BFLowPowerDefault);
MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren);
MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15, 0, BFPhy0x0D080F0C);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00, 6, 4, BFDQOdt03);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08, 6, 4, BFDQOdt47);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1E, 14, 12, BFDllCSRBisaTrimDByte);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1E, 14, 12, BFDllCSRBisaTrimClk);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1E, 14, 12, BFDllCSRBisaTrimCsOdt);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FCF1E, 14, 12, BFDllCSRBisaTrimAByte2);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F38, 14, 13, BFReduceLoop);
+
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD);
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8;
}
+ if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) {
+ Value8 -= 5;
+ }
+
Value8 = Value8 - TmgAdjTab[j].Bias;
Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
(BitField == BFTrp ) ? (Value8 <= 9) :
(BitField == BFTrtp) ? (Value8 <= 4) :
(BitField == BFTras) ? (Value8 <= 21) :
- (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) :
+ (BitField == BFTrc ) ? (NBPtr->IsSupported[AdjustTrc] ? ((Value8 >= 4) && (Value8 <= 38)) : ((Value8 >= 9) && (Value8 <= 38))) :
(BitField == BFTrrd) ? (Value8 <= 4) :
(BitField == BFTwtr) ? (Value8 <= 4) :
(BitField == BFTwrDDR3) ? (Value8 <= 7) :
// THEN 2 ELSE 3 ENDIF (Ontario)
NBPtr->ProgramNbPsDependentRegs (NBPtr);
+ NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr);
IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
// 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
*----------------------------------------------------------------------------
*/
+VOID
+MemNInitCPGNb (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
+VOID
+MemNInitDqsTrainRcvrEnHwNb (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
+VOID
+MemNDisableDqsTrainRcvrEnHwNb (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
VOID
STATIC
MemNContWritePatternNb (
IN UINT16 ClCount
);
+VOID
+MemNInitCPGClientNb (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
+VOID
+MemNInitCPGUnb (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
+
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
//
// Issue Stream of Reads from the Target Rank
//
- NBPtr->ReadPattern (NBPtr, DummyPtr, NULL, NBPtr->TechPtr->PatternLength);
+ NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
}
/* -----------------------------------------------------------------------------*/
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB)
- * @e \$Revision: 39420 $ @e \$Date: 2010-10-12 00:52:49 +0800 (Tue, 12 Oct 2010) $
+ * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
{
CONST UINT16 DdrMaxRateTab[] = {
UNSUPPORTED_DDR_FREQUENCY,
- DDR1866_FREQUENCY,
DDR1600_FREQUENCY,
DDR1333_FREQUENCY,
DDR1066_FREQUENCY,
Mode[Dct] = ChnlTmgMod[0];
// Check if input clock value is valid or not
ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
- (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
- (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
+ ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) :
+ ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY));
MemClkFreq = ChnlTmgMod[1];
}
}
* (UINT16 * ) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate));
return TRUE;
}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ * This function performs the action before and after excluding dimms on CNB
+ *
+ * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
+ * @param[in,out] *IsBefore - If the function is called before excluding dimms
+ *
+ * @return TRUE
+ *
+ */
+
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *IsBefore
+ )
+{
+ if (*(BOOLEAN *) IsBefore == TRUE) {
+ NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1);
+ NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+ } else {
+ NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1);
+ NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+ }
+
+ return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ * LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Ps/ON)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $
*
**/
/*
return AGESA_UNSUPPORTED;
}
PsPtr->MemPDoPs = MemPDoPsSON3;
+
+ if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSON3;
+ } else {
+ // Do not force frequency limit for Rev C
+ PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+ }
+
return AGESA_SUCCESS;
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Ps/ON)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $
*
**/
/*
return AGESA_UNSUPPORTED;
}
PsPtr->MemPDoPs = MemPDoPsUON3;
+
+ if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3;
+ } else {
+ // Do not force frequency limit for Rev C
+ PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+ }
+
return AGESA_SUCCESS;
}
#include "mn.h"
#include "mu.h"
#include "mt.h"
+#include "mt3.h"
#include "mtrci3.h"
#include "merrhdl.h"
#include "Filecode.h"
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
*
**/
/*
BFSRT, ///< Bit field SRT
BFTcwl, ///< Bit field Tcwl
BFPchgPDModeSel, ///< Bit field PchgPDModeSel
+ BFLowPowerDefault, ///< Bit field LowPowerDefault
BFTwrDDR3, ///< Bit field TwrDDR3
BFTcl, ///< Bit field Tcl
BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap
+ BFDllCSRBisaTrimDByte, ///< Bit field DllCSRBisaTrimDByte
+ BFDllCSRBisaTrimClk, ///< Bit field DllCSRBisaTrimClk
+ BFDllCSRBisaTrimCsOdt, ///< Bit field DllCSRBisaTrimCsOdt
+ BFDllCSRBisaTrimAByte2, ///< Bit field DllCSRBisaTrimAByte2
+ BFReduceLoop, ///< Bit field ReduceLoop
+
// Reserved
BFReserved01, ///< Reserved 01
BFReserved02, ///< Reserved 02
IN OUT MEM_DATA_STRUCT *MemPtr
);
-VOID
-MemRecDefRet (VOID);
+//VOID
+//MemRecDefRet (VOID);
-BOOLEAN
-MemRecDefTrue (VOID);
+//BOOLEAN
+//MemRecDefTrue (VOID);
VOID
SetMemRecError (
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value
SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK
TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init.
+ AdjustTrc, ///< Check to determine if we need to adjust Trc
EnumSize ///< Size of list
} NB_SUPPORTED;
/// List for family specific functions that are supported
typedef enum {
BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training
+ BeforeMemClkFreqVal, ///< hook before setting MemClkFreqVal bit
AfterMemClkFreqVal, ///< Override PllMult and PllDiv
OverridePllMult, ///< Override PllMult
OverridePllDiv, ///< Override PllDiv
ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training
EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset.
FinalizeVDDIO, ///< Finalize VDDIO
+ BfAfExcludeDimm, ///< Workaround before and after excluding dimms
NumberOfHooks ///< Size of list
} FAMILY_SPECIFIC_FUNC_INDEX;
BOOLEAN ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
UINT8 NbFreqChgState; ///< is used as a state index in NB frequency change state machine
UINT32 NbPsCtlReg; ///< is used to save/restore NB Pstate control register
+ CONST UINT32 *RecModeDefRegArray; ///< points to an array of default register values that are set for recovery mode
///< Determines if code should be executed on a give NB
BOOLEAN IsSupported[EnumSize];
IN OUT VOID *OptParam
);
+UINT32
+MemRecNcmnGetSetTrainDlyClientNb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN UINT8 IsSet,
+ IN TRN_DLY_TYPE TrnDly,
+ IN DRBN DrbnVar,
+ IN UINT16 Field
+ );
+
VOID
MemNSetTxpNb (
IN OUT MEM_NB_BLOCK *NBPtr
IN OUT TRN_DLY_PARMS *Parms
);
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *IsBefore
+ );
+
#endif /* _MN_H_ */
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
*
*----------------------------------------------------------------------------
*/
-#define RECDEF_DRAM_CONTROL_REG 0x14042A03
-#define RECDEF_DRAM_MRSREG 0x000400A5
-#define RECDEF_DRAM_TIMING_LO 0x000A0092
-#define RECDEF_DRAM_TIMING_HI 0x001218FF
#define RECDEF_CSMASK_REG 0x00003FE0
-#define RECDEF_DRAM_CONFIG_LO_REG 0x30000000
-#define RECDEF_DRAM_CONFIG_HI_REG 0x1E000000
#define RECDEF_DRAM_BASE_REG 0x00000003
-#define RECDEF_DRAM_TIMING_0 0x0A000101
-#define RECDEF_DRAM_TIMING_1 0
#define MAX_RD_DQS_DLY 0x1F
+#define DEFAULT_WR_ODT_ON_ON 6
+#define DEFAULT_RD_ODT_ON_ON 6
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
{
UINT32 AddrTmgValue;
UINT32 DrvStrValue;
+ UINT32 RODTCSLow;
+ UINT32 WODTCSLow;
CH_DEF_STRUCT *ChannelPtr;
ChannelPtr = NBPtr->ChannelPtr;
// SODIMM
if (ChannelPtr->Dimms == 2) {
AddrTmgValue = 0x00000039;
- DrvStrValue = 0x30222323;
+ DrvStrValue = 0x20222323;
} else {
AddrTmgValue = 0;
- DrvStrValue = 0x00002222;
+ DrvStrValue = 0x00002223;
}
} else {
// UDIMM
}
MemRecNSetBitFieldNb (NBPtr, BFODCControl, DrvStrValue);
MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrTmgValue);
+ RODTCSLow = 0;
+ if (ChannelPtr->Dimms == 2) {
+ RODTCSLow = 0x01010404;
+ WODTCSLow = 0x09050605;
+ } else if (NBPtr->ChannelPtr->DimmDrPresent != 0) {
+ WODTCSLow = 0x00000201;
+ if (NBPtr->DimmToBeUsed == 1) {
+ WODTCSLow = 0x08040000;
+ }
+ } else {
+ WODTCSLow = 0x00000001;
+ if (NBPtr->DimmToBeUsed == 1) {
+ WODTCSLow = 0x00040000;
+ }
+ }
+ MemRecNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, RODTCSLow);
+ MemRecNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, WODTCSLow);
return TRUE;
}
if (OdtMode == WRITE_LEVELING_MODE) {
if (ChipSelect == TargetCS) {
+ if (Dimms >= 2) {
DramTerm = DramTermDyn;
+ }
MaxDimmsPerChannel = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, 0, NBPtr->ChannelPtr->ChannelID);
} else {
// Dimms = 1
if (TargetCS == 0) {
- WrLvOdt = 0xF;
+ WrLvOdt = 1;
} else {
// TargetCS = 2
WrLvOdt = 4;
UINT8 ChipSel;
UINT32 CSBase;
UINT32 NBClkFreq;
+ UINT8 i;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
0,
&NBClkFreq,
&(NBPtr->MemPtr->StdHeader));
- NBPtr->NBClkFreq = NBClkFreq;
MemRecNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 1);
//Prepare variables for future usage.
}
MemRecNSetBitFieldNb (NBPtr, BFDramBaseReg0, RECDEF_DRAM_BASE_REG);
MemRecNSetBitFieldNb (NBPtr, BFDramLimitReg0, 0x70000);
- MemRecNSetBitFieldNb (NBPtr, BFDramBankAddrReg, 0x00000011);
-
- // Set timing registers
- MemRecNSetBitFieldNb (NBPtr, BFDramTiming0, RECDEF_DRAM_TIMING_0);
- MemRecNSetBitFieldNb (NBPtr, BFDramTiming1, RECDEF_DRAM_TIMING_1);
- MemRecNSetBitFieldNb (NBPtr, BFDramTimingLoReg, RECDEF_DRAM_TIMING_LO);
- MemRecNSetBitFieldNb (NBPtr, BFDramTimingHiReg, RECDEF_DRAM_TIMING_HI);
- MemRecNSetBitFieldNb (NBPtr, BFDramMRSReg, RECDEF_DRAM_MRSREG);
- MemRecNSetBitFieldNb (NBPtr, BFDramControlReg, RECDEF_DRAM_CONTROL_REG);
- // Set DRAM Config Low Register
- MemRecNSetBitFieldNb (NBPtr, BFDramConfigLoReg, RECDEF_DRAM_CONFIG_LO_REG);
-
- // Set DRAM Config High Register
- MemRecNSetBitFieldNb (NBPtr, BFDramConfigHiReg, RECDEF_DRAM_CONFIG_HI_REG);
-
- // DctWrLimit = 0x1F
+
+ // Use default values for common registers
+ i = 0;
+ while (NBPtr->RecModeDefRegArray[i] != NULL) {
+ MemRecNSetBitFieldNb (NBPtr, NBPtr->RecModeDefRegArray[i], NBPtr->RecModeDefRegArray[i + 1]);
+ i += 2;
+ }
+
+ //======================================================================
+ // Build Dram Config Misc Register Value
+ //======================================================================
+ //
+ // Max out Non-SPD timings
+ MemRecNSetBitFieldNb (NBPtr, BFTwrrdSD, 0xA);
+ MemRecNSetBitFieldNb (NBPtr, BFTrdrdSD, 0x8);
+ MemRecNSetBitFieldNb (NBPtr, BFTwrwrSD, 0x9);
+
+ MemRecNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_ON_ON);
+ MemRecNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_ON_ON);
+ MemRecNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0);
+
+ MemRecNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, 6 - 5);
+ //======================================================================
+ // DRAM MRS Register, set ODT
+ //======================================================================
+ MemRecNSetBitFieldNb (NBPtr, BFBurstCtrl, 1);
+
+ //
+ // Recommended registers setting BEFORE DRAM device initialization and training
+ //
+ MemRecNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
+ MemRecNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
+ MemRecNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0);
+ MemRecNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0);
+ MemRecNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0);
+ MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1);
MemRecNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F);
- // EnCpuSerRdBehindNpIoWr = 1
MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1);
+ MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
+ MemRecNSetBitFieldNb (NBPtr, BFMaxLatency, 0x12);
+ MemRecNSetBitFieldNb (NBPtr, BFTraceModeEn, 0);
+
+ // Enable cut through mode for NB P0
+ MemRecNSetBitFieldNb (NBPtr, BFDisCutThroughMode, 0);
return TRUE;
}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ * This function overrides the seed for hardware based RcvEn training of Ontario.
+ *
+ * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
+ * @param[in,out] *SeedPtr - Pointer to the seed value.
+ *
+ * @return TRUE
+ */
+
+BOOLEAN
+MemRecNOverrideRcvEnSeedON (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *SeedPtr
+ )
+{
+ *(UINT16*) SeedPtr = 0x5B;
+ return TRUE;
+}
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
*
*----------------------------------------------------------------------------
*/
-
+VOID
+STATIC
+MemRecNFinalizeMctON (
+ IN OUT MEM_NB_BLOCK *NBPtr
+ );
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
}
}
+ MemRecNFinalizeMctON (NBPtr);
+
return Status;
}
*/
VOID
+STATIC
MemRecNFinalizeMctON (
IN OUT MEM_NB_BLOCK *NBPtr
)
//
// Recommended registers setting after DRAM device initialization and training
//
- // PrefCpuDis = 0
+ MemRecNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1);
+ MemRecNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
+ MemRecNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
+ MemRecNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0x1000);
MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- // DctWrLimit = 0x1C
MemRecNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C);
- // DramTrainPdbDis = 1
MemRecNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1);
- // EnCpuSerRdBehindNpIoWr = 0
MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets initial values in BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNInitializeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
-
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
+#include "OptionMemory.h"
#include "mrport.h"
#include "cpuFamRegisters.h"
#include "cpuRegisters.h"
#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
#define MAX_DIMMS 4 /* 4 DIMMs per channel */
+#define PHY_DIRECT_ADDRESS_MASK 0x0D000000
+
+STATIC CONST UINT8 RecInstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1};
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
-CONST MEM_FREQ_CHANGE_PARAM RecFreqChangeParamON = {0x1838, NULL, 3, 10, 2};
+CONST MEM_FREQ_CHANGE_PARAM RecFreqChangeParamON = {0x1838, NULL, 3, 10, 2, 9, NULL, 1000};
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
IN UINT32 Field
);
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
BOOLEAN
STATIC
MemRecNIsIdSupportedON (
*
*----------------------------------------------------------------------------
*/
+STATIC CONST UINT32 RecModeDefRegArrayON[] = {
+ BFDramBankAddrReg, 0x00000011,
+ BFDramTimingLoReg, 0x000A0092,
+ BFDramTiming0, 0x0A000101,
+ BFDramTiming1, 0x04100415,
+ BFDramTimingHiReg, 0x02D218FF,
+ BFDramMRSReg, 0x000400A5,
+ BFDramControlReg, 0x04802A03,
+ BFDramConfigLoReg, 0x06600000,
+ BFDramConfigHiReg, 0x1E000000,
+ BFPhyFence, 0x000056B5,
+ NULL
+};
/* -----------------------------------------------------------------------------*/
/**
*
//
// Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
//
- AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK));
+ AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + (MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES);
AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
return FALSE;
}
+ NBPtr->SPDPtr = MemPtr->SpdDataStructure;
+ NBPtr->AllNodeSPDPtr = MemPtr->SpdDataStructure;
+
MemPtr->DieCount = 1;
MCTPtr->Dct = 0;
MCTPtr->DctCount = 1;
MCTPtr->DctData->ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof (CH_DEF_STRUCT);
NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
+ AllocHeapParams.BufferPtr += sizeof (MEM_PS_BLOCK);
+
+ MCTPtr->DctData->ChData->RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
+ AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
+ MCTPtr->DctData->ChData->WrDqsDlys = AllocHeapParams.BufferPtr;
//
// Initialize NB block's variables
NBPtr->InitRecovery = MemRecNMemInitON;
+ NBPtr->RecModeDefRegArray = RecModeDefRegArrayON;
+
NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldON;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyON;
+ NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyClientNb;
NBPtr->MemRecNSwitchDctNb = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctON;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctON;
- NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
NBPtr->TrainingFlow = MemNRecTrainingFlowClientNb;
NBPtr->ReadPattern = MemRecNContReadPatternClientNb;
+ NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
+ NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemRecNOverrideRcvEnSeedON;
return TRUE;
}
*
*----------------------------------------------------------------------------
*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 1);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- if ((Byte & 0x04) != 0) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if ((Byte & 0x02) != 0) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet != 0) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
/* -----------------------------------------------------------------------------*/
/**
*
IN UINT32 Field
)
{
- SBDFO Address;
+ TSEFO Address;
PCI_ADDR PciAddr;
UINT8 Type;
+ UINT8 IsLinked;
UINT32 Value;
UINT32 Highbit;
UINT32 Lowbit;
UINT32 Mask;
+ UINT8 IsPhyDirectAccess;
+ UINT8 IsWholeRegAccess;
+ UINT8 NumOfInstances;
+ UINT8 Instance;
Value = 0;
- if ((FieldName == BFDctAccessDone) || (FieldName == BFDctExtraAccessDone)) {
- Value = 1;
- } else if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
+ if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
Address = NBPtr->NBRegTable[FieldName];
- if (Address != 0) {
+ if (Address) {
Lowbit = TSEFO_END (Address);
Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
+ Type = (UINT8) TSEFO_TYPE (Address);
+ IsLinked = (UINT8) TSEFO_LINKED (Address);
+ IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address);
+ IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address);
+
+ ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
+ Address = TSEFO_OFFSET (Address);
+
+ // By default, a bit field has only one instance
+ NumOfInstances = 1;
+
+ if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
+ Address |= PHY_DIRECT_ADDRESS_MASK;
+ if (IsWholeRegAccess) {
+ // In the case of whole regiter access (bit 0 to 15),
+ // HW broadcast and nibble mask will be used.
+ Address |= Lowbit << 16;
Lowbit = 0;
- Highbit = 16;
+ Highbit = 15;
} else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
+ // In the case only some bits on a register is accessed,
+ // BIOS will do read-mod-write to all chiplets manually.
+ // And nibble mask will be 1111b always.
+ Address |= 0x000F0000;
+ Field >>= Lowbit;
+ if ((Address & 0x0F00) == 0x0F00) {
+ // Broadcast mode
+ // Find out how many instances to write to
+ NumOfInstances = RecInstancesPerTypeON[(Address >> 13) & 0x7];
+ if (!IsSet) {
+ // For read, only read from instance 0 in broadcast mode
+ NumOfInstances = 1;
+ }
+ }
+ }
}
+ ASSERT (NumOfInstances > 0);
+ for (Instance = 0; Instance < NumOfInstances; Instance++) {
if (Type == NB_ACCESS) {
Address |= (((UINT32) (24 + 0)) << 15);
PciAddr.AddressValue = Address;
LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
+ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
+ (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
+ IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
+ }
} else if (Type == DCT_PHY_ACCESS) {
+ if (IsPhyDirectAccess && (NumOfInstances > 1)) {
+ Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8);
+ }
MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-
Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
+ IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
} else if (Type == DCT_EXTRA) {
MemRecNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
Value = MemRecNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
+ IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
} else {
IDS_ERROR_TRAP;
}
- if (IsSet != 0) {
+ if (IsSet) {
// A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
if ((Highbit - Lowbit) != 31) {
Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
if (Type == NB_ACCESS) {
PciAddr.AddressValue = Address;
LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
+ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
+ (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
+ IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
+ }
} else if (Type == DCT_PHY_ACCESS) {
MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
Address |= DCT_ACCESS_WRITE;
-
MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+ IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
} else if (Type == DCT_EXTRA) {
MemRecNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
Address |= DCT_ACCESS_WRITE;
MemRecNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
+ IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
} else {
IDS_ERROR_TRAP;
}
+ if (IsLinked) {
+ MemRecNCmnGetSetFieldON (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
+ }
} else {
Value = Value >> Lowbit; // Shift
// A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
if ((Highbit - Lowbit) != 31) {
Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
}
+ if (IsLinked) {
+ Value |= MemRecNCmnGetSetFieldON (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
+ }
+ // For direct phy access, shift the bit back for compatibility reason.
+ if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
+ Value <<= Lowbit;
+ }
+ }
}
}
} else {
)
{
UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
+ for (i = 0; i < BFEndOfList; i++) {
NBRegTable[i] = 0;
}
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 6, 6, BFRxPtrInitReq);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode);
+ MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 27, 24, BFPllDiv);
MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 31, 16, BFPhyFence);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock);
+
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15, 0, BFPllRegWaitTime);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks);
+
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1C00, 15, 0, BFPNOdtCal);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1D00, 15, 0, BFPNDrvCal);
+ MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D081E00, 15, 0, BFCalVal);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl);
MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator);
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator);
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1);
MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 31, 0, BFDramTiming0);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 31, 0, BFDramTiming1);
+
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 2, 0, BFRdOdtTrnOnDly);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 6, 4, BFRdOdtOnDuration);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 8, 8, BFWrOdtTrnOnDly);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration);
+
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow);
+ MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow);
}
/*-----------------------------------------------------------------------------*/
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
IN OUT MEM_NB_BLOCK *NBPtr
);
-VOID
-MemRecNFinalizeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNInitializeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
VOID
MemRecNSetMaxLatencyON (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
+BOOLEAN
+MemRecNOverrideRcvEnSeedON (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN OUT VOID *SeedPtr
+ );
#endif /* _MRNON_H_ */
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem/NB)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
IN OUT MEM_NB_BLOCK *NBPtr
);
-VOID
-STATIC
-MemRecNInitPhyCompClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
IN OUT MEM_NB_BLOCK *NBPtr
)
{
+ IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", NBPtr->Dct);
+
// Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999.
MemRecNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80000000);
MemRecNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
MemRecNSetBitFieldNb (NBPtr, BFPllLockTime, 0x000F);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for DCT%d\n", NBPtr->Dct);
MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
MemRecNSetBitFieldNb (NBPtr, BFEnDramInit, 1);
- // Phy fence programming
- MemRecNPhyFenceTrainingNb (NBPtr);
-
- // Phy Compensation Initialization
- MemRecNInitPhyCompClientNb (NBPtr);
-
// Run DramInit sequence
AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
NBPtr->TechPtr->DramInit (NBPtr->TechPtr);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", DDR800_FREQUENCY);
}
/* -----------------------------------------------------------------------------*/
AGESA_TESTPOINT (TpProcMemRcvrCalcLatency , &(NBPtr->MemPtr->StdHeader));
- // Before calculating MaxRdLatecny, program a number of registers.
- MemRecNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
- MemRecNSetBitFieldNb (NBPtr, BFEnterSelfRef, 1);
- while (MemRecNGetBitFieldNb (NBPtr, BFEnterSelfRef) != 0) {}
- MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 2);
- MemRecNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
- while (MemRecNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
- MemRecNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
-
// P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) where RdPtrInitMin = RdPtrInit
P = 0;
}
/* -----------------------------------------------------------------------------*/
-CONST UINT16 RecPllDivTab[10] = {1, 2, 4, 8, 16, 128, 256, 1, 3, 6};
-
/**
*
* This function calculates and programs NB P-state dependent registers
UINT16 MemClkDid;
UINT8 PllMult;
UINT8 NclkDiv;
+ UINT8 RdPtrInit;
UINT32 NclkPeriod;
UINT32 MemClkPeriod;
INT32 PartialSum2x;
INT32 PartialSumSlotI2x;
+ INT32 RdPtrInitRmdr2x;
NclkFid = (UINT8) (MemRecNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10);
- MemClkDid = RecPllDivTab[MemRecNGetBitFieldNb (NBPtr, BFPllDiv)];
- PllMult = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFPllMult);
+ MemClkDid = 2; //BKDG recommended value for DDR800
+ PllMult = 16; //BKDG recommended value for DDR800
NclkDiv = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv);
NclkPeriod = (2500 * NclkDiv) / NclkFid;
MemClkPeriod = 1000000 / DDR800_FREQUENCY;
+ NBPtr->NBClkFreq = ((UINT32) NclkFid * 400) / NclkDiv;
+
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d Freq: %dMHz\n", 0, NBPtr->NBClkFreq);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", DDR800_FREQUENCY);
+
+ // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
+ // THEN 2 ELSE 3 ENDIF (Ontario)
+ RdPtrInit = NBPtr->FreqChangeParam->RdPtrInitLower667;
+ MemRecNSetBitFieldNb (NBPtr, BFRdPtrInit, RdPtrInit);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
// Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
MemRecNSetBitFieldNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16);
MemRecNSetBitFieldNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv);
+
// Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
// DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0].
// PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod;
PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod;
PartialSum2x += 520 * 2;
+ RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (NBPtr->FreqChangeParam->TDataPropLower800 + 520);
+ RdPtrInitRmdr2x %= MemClkPeriod;
+ PartialSum2x -= RdPtrInitRmdr2x;
PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here
PartialSum2x -= 2 * 5; //Tcwl + 5
if ((MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
} else {
PartialSum2x -= 2;
}
- // ((16 + RdPtrInitMin - D18F2x78[RdPtrInit]) MOD 16)/2 where RdPtrInitMin = RdPtrInit
- PartialSum2x -= 0;
PartialSum2x -= 2;
// If PartialSumSlotN is positive:
// DataTxFifoSchedDlyNegSlotN=1.
for (i = 0; i < 2; i++) {
PartialSumSlotI2x = PartialSum2x;
+ if (i == 0) {
PartialSumSlotI2x += 2;
+ }
if (PartialSumSlotI2x > 0) {
MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0);
MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2);
} else {
MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1);
PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod);
MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x);
}
}
// Program ProcOdtAdv
return DIMMRankType;
}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DDR phy compensation logic
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecNInitPhyCompClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
+UINT32
+MemRecNcmnGetSetTrainDlyClientNb (
+ IN OUT MEM_NB_BLOCK *NBPtr,
+ IN UINT8 IsSet,
+ IN TRN_DLY_TYPE TrnDly,
+ IN DRBN DrbnVar,
+ IN UINT16 Field
)
{
- // Slew rate table array [x]
- // array[0]: slew rate for VDDIO 1.5V
- // array[1]: slew rate for VDDIO 1.35V
- CONST STATIC UINT16 RecTxPrePNDataDqs[2][4] = {
- //{TxPreP, TxPreN}[VDDIO][Drive Strength]
- {0x924, 0x924, 0x924, 0x924},
- {0xFF6, 0xB6D, 0xB6D, 0x924}
- };
+ UINT16 Index;
+ UINT16 Offset;
+ UINT32 Value;
+ UINT32 Address;
+ UINT8 Dimm;
+ UINT8 Byte;
- CONST STATIC UINT16 RecTxPrePNCmdAddr[2][4] = {
- //{TxPreP, TxPreN}[VDDIO][Drive Strength]
- {0x492, 0x492, 0x492, 0x492},
- {0x492, 0x492, 0x492, 0x492}
- };
- CONST STATIC UINT16 RecTxPrePNClock[2][4] = {
- //{TxPreP, TxPreN}[VDDIO][Drive Strength]
- {0x924, 0x924, 0x924, 0x924},
- {0xDAD, 0xDAD, 0x924, 0x924}
- };
+ Dimm = DRBN_DIMM (DrbnVar);
+ Byte = DRBN_BYTE (DrbnVar);
- //
- // Tables to describe the relationship between drive strength bit fields, PreDriver Calibration bit fields and also
- // the extra value that needs to be written to specific PreDriver bit fields
- //
- CONST REC_PHY_COMP_INIT_CLIENTNB RecPhyCompInitBitField[] = {
- // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}.
- // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}.
- {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, RecTxPrePNDataDqs},
- {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, RecTxPrePNDataDqs},
- {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, RecTxPrePNDataDqs},
- // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}.
- // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}.
- {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, RecTxPrePNCmdAddr},
- {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, RecTxPrePNCmdAddr},
- {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, RecTxPrePNCmdAddr},
- {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, RecTxPrePNCmdAddr},
- {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, RecTxPrePNCmdAddr},
- // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}.
- {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, RecTxPrePNClock}
- };
+ ASSERT (Dimm < 2);
+ ASSERT (Byte <= ECC_DLY);
- BIT_FIELD_NAME CurrentBitField;
- CONST UINT16 *TxPrePNArray;
- UINT8 Voltage;
- UINT8 CurDct;
- UINT8 i;
- UINT8 j;
+ if ((Byte > 7)) {
+ // LN and ON do not support ECC delay, so:
+ if (IsSet) {
+ // On write, ignore
+ return 0;
+ } else {
+ // On read, redirect to byte 0 to correct fence averaging
+ Byte = 0;
+ }
+ }
+
+ switch (TrnDly) {
+ case AccessRcvEnDly:
+ Index = 0x10;
+ break;
+ case AccessWrDqsDly:
+ Index = 0x30;
+ break;
+ case AccessWrDatDly:
+ Index = 0x01;
+ break;
+ case AccessRdDqsDly:
+ Index = 0x05;
+ break;
+ case AccessPhRecDly:
+ Index = 0x50;
+ break;
+ default:
+ Index = 0;
+ IDS_ERROR_TRAP;
+ }
+
+ switch (TrnDly) {
+ case AccessRcvEnDly:
+ case AccessWrDqsDly:
+ Index += (Dimm * 3);
+ if (Byte & 0x04) {
+ // if byte 4,5,6,7
+ Index += 0x10;
+ }
+ if (Byte & 0x02) {
+ // if byte 2,3,6,7
+ Index++;
+ }
+ Offset = 16 * (Byte % 2);
+ break;
+
+ case AccessRdDqsDly:
+ case AccessWrDatDly:
+ Index += (Dimm * 0x100);
+ // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
+ // to run AccessPhRecDly sequence.
+ case AccessPhRecDly:
+ Index += (Byte / 4);
+ Offset = 8 * (Byte % 4);
+ break;
+ default:
+ Offset = 0;
+ IDS_ERROR_TRAP;
+ }
- CurDct = NBPtr->Dct;
- NBPtr->SwitchDCT (NBPtr, 0);
- // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisalbePredriverCal]={1b, 1b}
- MemRecNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000);
+ Address = Index;
+ MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
+ Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- NBPtr->SwitchDCT (NBPtr, CurDct);
+ if (IsSet) {
+ if (TrnDly == AccessPhRecDly) {
+ Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
+ }
- Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage;
+ Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset)));
+ MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
+ Address |= DCT_ACCESS_WRITE;
+ MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- for (j = 0; j < GET_SIZE_OF (RecPhyCompInitBitField); j ++) {
- i = (UINT8) MemRecNGetBitFieldNb (NBPtr, RecPhyCompInitBitField[j].IndexBitField);
- TxPrePNArray = RecPhyCompInitBitField[j].TxPrePN[Voltage];
- for (CurrentBitField = RecPhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= RecPhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) {
- MemRecNSetBitFieldNb (NBPtr, CurrentBitField, ((RecPhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[i]));
+ if (TrnDly == AccessPhRecDly) {
+ NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
}
+ // Gross WrDatDly and WrDqsDly cannot be larger than 4
+ ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (NBPtr->IsSupported[WLNegativeDelay] || (Field < 0xA0)) : TRUE);
+ } else {
+ Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF);
}
+
+ return Value;
}
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
CACHE_INFO *CacheInfoPtr;
- GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader);
+ GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+ FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader);
return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/NB)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
IN OUT MEM_NB_BLOCK *NBPtr
)
{
+ IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n");
+ IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr->MCTPtr->DieId);
MemRecTTrainDQSWriteHw3 (NBPtr->TechPtr);
MemRecTTrainRcvrEnHw (NBPtr->TechPtr);
// Clear DisableCal and set DisablePredriverCal
NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr);
+ NBPtr->SetBitField (NBPtr, BFRxPtrInitReq, 1);
+ while (NBPtr->GetBitField (NBPtr, BFRxPtrInitReq) != 0) {}
+ NBPtr->SetBitField (NBPtr, BFDisDllShutdownSR, 1);
+ NBPtr->SetBitField (NBPtr, BFEnterSelfRef, 1);
+ while (NBPtr->GetBitField (NBPtr, BFEnterSelfRef) != 0) {}
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n");
+ NBPtr->SetBitField (NBPtr, BFDbeGskMemClkAlignMode, 2);
+ NBPtr->SetBitField (NBPtr, BFExitSelfRef, 1);
+ while (NBPtr->GetBitField (NBPtr, BFExitSelfRef) != 0) {}
+ NBPtr->SetBitField (NBPtr, BFDisDllShutdownSR, 0);
MemRecTTrainDQSPosSw (NBPtr->TechPtr);
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
#include "AGESA.h"
#include "OptionMemory.h"
+#include "Ids.h"
#include "mm.h"
#include "mn.h"
#include "mru.h"
NBPtr = TechPtr->NBPtr;
MemPtr = NBPtr->MemPtr;
+ IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for DCT%d\n", NBPtr->Dct);
// 3.Program F2x[1,0]7C[EnDramInit]=1
NBPtr->SetBitField (NBPtr, BFEnDramInit, 1);
// 18.Program F2x[1,0]7C[EnDramInit]=0
NBPtr->SetBitField (NBPtr, BFEnDramInit, 0);
-
+ IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
}
/* -----------------------------------------------------------------------------*/
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
NBPtr = TechPtr->NBPtr;
+ IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n");
// Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 1);
// Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
// 1. Specify the target Dimm that is to be trained by programming
// F2x[1, 0]9C_x08[TrDimmSel].
+ IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", NBPtr->DimmToBeUsed << 1);
NBPtr->SetBitField (NBPtr, BFTrDimmSel, NBPtr->DimmToBeUsed);
// 2. Prepare the DIMMs for write levelization using DDR3-defined
// 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
NBPtr->SetBitField (NBPtr, BFZqcsInterval, 2);
+ IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n");
}
/*----------------------------------------------------------------------------
// Wait 10 MEMCLKs to allow for ODT signal settling.
MemRecUWait10ns (3, NBPtr->MemPtr);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: ");
// Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
// the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
// BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
// Get platform override seed
Seed = (UINT8 *) MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, NBPtr->MCTPtr->SocketId, ChannelPtr->ChannelID);
+ IDS_HDT_CONSOLE (MEM_FLOW, "Seeds: ");
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
// This includes ECC as byte 8
CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
ChannelPtr->WrDqsDlys[Dimm * MAX_BYTELANES + ByteLane] = CurrentSeed;
+ IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed);
}
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n");
// Program F2x[1, 0]9C_x08[WrtLvTrMode]=0 for phy assisted training.
// Program F2x[1, 0]9C_x08[TrNibbleSel]=0
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n");
}
/* -----------------------------------------------------------------------------*/
NBPtr = TechPtr->NBPtr;
Dimm = NBPtr->DimmToBeUsed;
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n");
// Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
// Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
// for the target Dimm and save these values.
+ IDS_HDT_CONSOLE (MEM_FLOW, " PRE WrDqs\n");
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
// This includes ECC as byte 8
Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane];
Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
+ IDS_HDT_CONSOLE (MEM_FLOW, " %02x ", Delay);
if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
// If seed has gross delay of 0 and PRE has gross delay of 3,
// then round the total delay of TxDqs to 0.
}
NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane] = Delay;
+ IDS_HDT_CONSOLE (MEM_FLOW, " %02x\n", Delay);
}
+
+ IDS_HDT_CONSOLE_DEBUG_CODE (
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: ");
+ for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+ IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[ByteLane]);
+ }
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+ );
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
{
UINT8 TempBuffer[64];
UINT8 Count;
- UINT32 TestAddrRJ16;
+ UINT32 TestAddr;
UINT8 ChipSel;
UINT16 MaxRcvrDly;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader));
+ IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n");
// Set environment settings before training
MemRecTBeginTraining (TechPtr);
ChipSel = NBPtr->DimmToBeUsed << 1;
- TestAddrRJ16 = 1 << 21;
+ TestAddr = 1 << 21;
+
+ IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", TechPtr->NBPtr->Dct);
+ IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x\n", TestAddr);
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
// 1.Prepare the DIMMs for training
NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1);
// 4.BIOS begins sending out of back-to-back reads to create
// a continuous stream of DQS edges on the DDR interface.
for (Count = 0; Count < 3; Count++) {
- NBPtr->ReadPattern (NBPtr, TempBuffer, TestAddrRJ16, 64);
+ NBPtr->ReadPattern (NBPtr, TempBuffer, TestAddr, 64);
}
// 6.Wait 200 MEMCLKs.
// Restore environment settings after training
MemRecTEndTraining (TechPtr);
+ IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n");
}
UINT16 SeedPreGross;
UINT16 DiffSeedGrossSeedPreGross;
UINT8 ByteLane;
+ UINT16 PlatEst;
UINT16 *PlatEstSeed;
+ UINT16 SeedValue[8];
+ UINT16 SeedTtl[8];
+ UINT16 SeedPre[8];
NBPtr = TechPtr->NBPtr;
ChannelPtr = TechPtr->NBPtr->ChannelPtr;
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
// For Pass1, BIOS starts with the delay value obtained from the first pass of write
// levelization training that was done in DDR3 Training and add a delay value of 3Bh.
- SeedTotal = ChannelPtr->WrDqsDlys[((ChipSel >> 1) * MAX_BYTELANES) + ByteLane] + (PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : 0x3B;
+ PlatEst = 0x3B;
+ NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst);
+ PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst);
+ SeedTotal = ChannelPtr->WrDqsDlys[((ChipSel >> 1) * MAX_BYTELANES) + ByteLane] + PlatEst;
+ SeedValue[ByteLane] = PlatEst;
+ SeedTtl[ByteLane] = SeedTotal;
// SeedGross = SeedTotal DIV 32.
- SeedGross = (SeedTotal & 0x60) >> 5;
+ SeedGross = SeedTotal >> 5;
// SeedFine = SeedTotal MOD 32.
SeedFine = SeedTotal & 0x1F;
//BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52) with SeedPreGrossPass1
//and SeedFinePass1 from the preceding steps.
NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine);
+ SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine;
// 202688: Program seed value to RcvEnDly also.
NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5);
}
+ IDS_HDT_CONSOLE_DEBUG_CODE (
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: ");
+ for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+ IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]);
+ }
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: ");
+ for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+ IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]);
+ }
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t SeedPRE: ");
+ for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+ IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]);
+ }
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n");
+ );
}
/* -----------------------------------------------------------------------------*/
UINT8 ByteLane;
UINT16 RcvEnDly;
UINT16 MaxDly;
+ UINT16 RankRcvEnDly[8];
NBPtr = TechPtr->NBPtr;
ChannelPtr = TechPtr->NBPtr->ChannelPtr;
+ IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: ");
MaxDly = 0;
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
DiffSeedGrossSeedPreGross = (ChannelPtr->RcvEnDlys[(ChipSel * MAX_BYTELANES) + ByteLane]) & 0x1E0;
RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane));
+ IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly);
RcvEnDly = RcvEnDly + DiffSeedGrossSeedPreGross;
// Add 1 UI to get to the midpoint of preamble
RcvEnDly += 0x20;
+ RankRcvEnDly[ByteLane] = RcvEnDly;
if (RcvEnDly > MaxDly) {
MaxDly = RcvEnDly;
NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly);
}
-
+ IDS_HDT_CONSOLE_DEBUG_CODE (
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: ");
+ for (ByteLane = 0; ByteLane < 8; ByteLane++) {
+ IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]);
+ }
+ IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
+ );
return MaxDly;
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
WrDqs = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane];
NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs + WrDatDly);
- RdDqs = (WrDatDly == 0) ? 0x2F : 0x0F;
+ RdDqs = (WrDatDly == 0) ? 0x2F : 0x012;
NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), RdDqs);
}
}
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
*
**/
/*
AgesaStatus = AgesaReadSpdRecovery (0, &SpdParam);
if (AgesaStatus == AGESA_SUCCESS) {
DimmSPDPtr->DimmPresent = TRUE;
+ IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer);
if (!FindSocketWithMem) {
FindSocketWithMem = TRUE;
}
projects / coreboot.git / commitdiff