8 * @xrefitem bom "File Content Label" "Release Content"
11 * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $
15 *****************************************************************************
17 * Copyright (c) 2011, Advanced Micro Devices, Inc.
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42 * ***************************************************************************
47 "F14PcieAlibSsdt.aml",
57 Name (varMaxPortIndexNumber, 6)
59 include ("PcieAlibCore.asl")
60 include ("PcieSmuLibV1.asl")
61 include ("PcieAlibPspp.asl")
62 include ("PcieAlibHotplug.asl")
64 /*----------------------------------------------------------------------------------------*/
68 * Arg0 - 1 - GEN1 2 - GEN2
69 * Arg1 - 0 (AC) 1 (DC)
71 Method (procNbLclkDpmActivate, 2, NotSerialized) {
73 Store (procSmuRcuRead (0x8490), Local0)
74 // Patch state only if at least one state is enable
75 if (LNotEqual (And (Local0, 0xF0), 0)) {
76 if (LEqual (Arg0, 2)) {
77 //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2,
78 //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0
79 //This is a battery ¡¥idle¡¦ state along with a ¡¥perf¡¦ state that will be programmed to the max LCLK achievable at the Gen2 VID
80 And (Local0, 0xFFFFFFA0, Local0)
81 Or (Local0, 0xA0, Local0)
84 if (LEqual (Arg1, 0)) {
85 //If AC, & if only Gen1 supported, activate state DPM0 and DPM1
86 //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0
87 And (Local0, 0xFFFFFF60, Local0)
88 Or (Local0, 0x60, Local0)
90 //If DC mode & Gen1 supported, activate only state DPM0
91 //set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1
92 And (Local0, 0xFFFFFF20, Local0)
93 Or (Local0, 0x20, Local0)
96 procSmuRcuWrite (0x8490, Local0)
100 /*----------------------------------------------------------------------------------------*/
102 * Power gate PCIe phy lanes (hotplug support)
104 * Arg0 - Start Lane ID
106 * Arg2 - Power ON(1) / OFF(0)
108 Method (procPcieLanePowerControl, 3, NotSerialized) {
112 /*----------------------------------------------------------------------------------------*/
116 * Arg0 - 1 - GEN1 2 - GEN2
119 Method (procPcieAdjustPll, 1, NotSerialized) {
123 } //End of Scope(\_SB)
124 } //End of DefinitionBlock