5 * AMD AGESA Basic Level Public APIs
7 * Contains basic Level Initialization routines.
9 * @xrefitem bom "File Content Label" "Release Content"
11 * @e sub-project: Interface
12 * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
16 *****************************************************************************
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * ***************************************************************************
48 /*----------------------------------------------------------------------------------------
49 * M O D U L E S U S E D
50 *----------------------------------------------------------------------------------------
55 #include "cpuCacheInit.h"
56 #include "cpuRegisters.h"
57 #include "cpuApicUtilities.h"
58 #include "cpuEarlyInit.h"
59 #include "AdvancedApi.h"
60 #include "cpuServices.h"
61 #include "CommonInits.h"
62 #include "GnbInterface.h"
65 RDATA_GROUP (G1_PEICC)
67 #define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE
68 /*----------------------------------------------------------------------------------------
69 * D E F I N I T I O N S A N D M A C R O S
70 *----------------------------------------------------------------------------------------
74 /*----------------------------------------------------------------------------------------
75 * T Y P E D E F S A N D S T R U C T U R E S
76 *----------------------------------------------------------------------------------------
78 EXECUTION_CACHE_REGION InitExeCacheMap[] =
80 {0x00000000, 0x00000000},
81 {0x00000000, 0x00000000},
82 {0x00000000, 0x00000000}
85 /*----------------------------------------------------------------------------------------
86 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
87 *----------------------------------------------------------------------------------------
91 /*----------------------------------------------------------------------------------------
92 * E X P O R T E D F U N C T I O N S
93 *----------------------------------------------------------------------------------------
95 extern BUILD_OPT_CFG UserOptions;
96 /*------------------------------------------------------------------------------------*/
98 * Initialize AmdInitEarly stage platform profile and user option input.
100 * @param[in,out] PlatformConfig Platform profile/build option config structure
101 * @param[in,out] StdHeader AMD standard header config param
103 * @retval AGESA_SUCCESS Always Succeeds.
107 AmdEarlyPlatformConfigInit (
108 IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
109 IN OUT AMD_CONFIG_PARAMS *StdHeader
112 CommonPlatformConfigInit (PlatformConfig, StdHeader);
114 return AGESA_SUCCESS;
116 /*------------------------------------------------------------------------------------*/
118 * Initializer routine that will be invoked by the wrapper to initialize the input
119 * structure for the AllocateExecutionCache.
121 * @param[in] StdHeader Opaque handle to standard config header
122 * @param[in] AmdExeAddrMapPtr Our Service interface struct
124 * @retval AGESA_SUCCESS Always Succeeds.
128 AllocateExecutionCacheInitializer (
129 IN AMD_CONFIG_PARAMS *StdHeader,
130 IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
134 ASSERT (AmdExeAddrMapPtr != NULL);
136 for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
137 AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr;
138 AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize;
141 return AGESA_SUCCESS;
144 /*---------------------------------------------------------------------------------------*/
147 * Initializer routine that will be invoked by the wrapper to initialize the input
148 * structure for the AmdInitEarly.
150 * @param[in] StdHeader AMD standard header config param.
151 * @param[in,out] EarlyParams The service interface struct to initialize.
153 * @retval AGESA_SUCCESS Always succeeds.
156 AmdInitEarlyInitializer (
157 IN AMD_CONFIG_PARAMS *StdHeader,
158 IN OUT AMD_EARLY_PARAMS *EarlyParams
161 ASSERT (StdHeader != NULL);
162 ASSERT (EarlyParams != NULL);
164 EarlyParams->StdHeader = *StdHeader;
166 // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED.
169 AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
171 AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig);
173 AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader);
175 return AGESA_SUCCESS;
179 /*---------------------------------------------------------------------------------------*/
181 * Perform initialization services required at the Early Init POST time point.
183 * Execution Cache, HyperTransport, and AP Init advanced services are performed.
185 * @param[in] EarlyParams The interface struct for all early services
187 * @return The most severe AGESA_STATUS returned by any called service.
192 IN OUT AMD_EARLY_PARAMS *EarlyParams
195 AGESA_STATUS CalledAgesaStatus;
196 AGESA_STATUS EarlyInitStatus;
197 WARM_RESET_REQUEST Request;
198 UINT8 PrevRequestBit;
201 AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);
202 IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
203 ASSERT (EarlyParams != NULL);
204 EarlyInitStatus = AGESA_SUCCESS;
205 PrevRequestBit = FALSE;
206 PrevStateBits = WR_STATE_COLD;
207 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEarly: Start %x \n\n", PrevStateBits);
208 // If a previously requested warm reset cannot be triggered in the
209 // current stage, store the previous state of request and reset the
210 // request struct to the current post stage
211 GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
212 if (Request.RequestBit == TRUE) {
213 if (Request.StateBits >= Request.PostStage) {
214 PrevRequestBit = Request.RequestBit;
215 PrevStateBits = Request.StateBits;
216 Request.RequestBit = FALSE;
217 Request.StateBits = Request.PostStage - 1;
218 SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
222 IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader);
224 // Setup ROM execution cache
225 IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n");
226 CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
227 IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n");
228 if (CalledAgesaStatus > EarlyInitStatus) {
229 EarlyInitStatus = CalledAgesaStatus;
232 // Full Hypertransport Initialization
233 // IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs.
234 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n");
235 CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig);
236 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n");
237 if (CalledAgesaStatus > EarlyInitStatus) {
238 EarlyInitStatus = CalledAgesaStatus;
242 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n");
243 CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig);
244 IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n");
245 if (CalledAgesaStatus > EarlyInitStatus) {
246 EarlyInitStatus = CalledAgesaStatus;
249 // Warm Reset, should be at the end of AmdInitEarly
250 GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
251 // If a warm reset is requested in the current post stage, trigger the
252 // warm reset and ignore the previous request
253 if (Request.RequestBit == TRUE) {
254 if (Request.StateBits < Request.PostStage) {
255 AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader);
258 // Otherwise, if there's a previous request, restore it
259 // so that the subsequent post stage can trigger the warm reset
260 if (PrevRequestBit == TRUE) {
261 Request.RequestBit = PrevRequestBit;
262 Request.StateBits = PrevStateBits;
263 SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
267 CalledAgesaStatus = GnbInitAtEarly (EarlyParams);
269 if (CalledAgesaStatus > EarlyInitStatus) {
270 EarlyInitStatus = CalledAgesaStatus;
272 // Check for Cache As Ram Corruption
273 IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader);
275 IDS_OPTION_HOOK (IDS_BEFORE_WARM_RESET, EarlyParams, &EarlyParams->StdHeader);
276 IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader);
277 IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
278 AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader);
279 IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n");
280 return EarlyInitStatus;