Remove remaining uses of

HAVE_FAILOVER_BOOT
HAVE_FALLBACK_BOOT
USE_FAILOVER_IMAGE
USE_FALLBACK_IMAGE

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/Kconfig b/src/Kconfig
index 55a40ff4f0773072e3fb1ea21f04618304d4919c..5da2973d073d180495c5b9a52e8c6cda5c9c86b5 100644 (file)
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -272,22 +272,6 @@ config ACPI_SSDTX_NUM
        int
        default 0
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default y
-
-config USE_FALLBACK_IMAGE
-       bool
-       default y
-
-config HAVE_FAILOVER_BOOT
-       bool
-       default n
-
-config USE_FAILOVER_IMAGE
-       bool
-       default n
-
 config HAVE_HARD_RESET
        bool
        default y if BOARD_HAS_HARD_RESET

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index d09934111bdaad8ed133aa16f680b46f44be9f3e..65f7555a0e3b2a58b2768fe9879fad93fef369da 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -71,9 +71,6 @@ cache_as_ram_setup:
        cvtsi2sd %eax, %xmm2
        cvtsd2si %xmm3, %ebx
 
-       /* hope we can skip the double set for normal part */
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
        /* check if cpu_init_detected */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
@@ -248,15 +245,6 @@ clear_fixed_var_mtrr_out:
        xorl    %edx, %edx
        movl    $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
        wrmsr
-#endif /*  CONFIG_USE_FAILOVER_IMAGE == 1*/
-
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
-       /* disable cache */
-       movl    %cr0, %eax
-       orl     $(0x1 << 30), %eax
-       movl    %eax, %cr0
-
-#endif
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
        /* enable write base caching so we can do execute in place
@@ -283,7 +271,6 @@ wbcache_post_fam10_setup:
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
        /* Set the default memory type and enable fixed and variable MTRRs */
        movl    $MTRRdefType_MSR, %ecx
        xorl    %edx, %edx
@@ -296,7 +283,6 @@ wbcache_post_fam10_setup:
        rdmsr
        orl     $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
        wrmsr
-#endif
 
        movb    $0xA1, %al
        outb    %al, $0x80
@@ -318,7 +304,6 @@ fam10_end_part1:
        movb    $0xA2, %al
        outb    %al, $0x80
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
        /* Read the range with lodsl*/
        cld
        movl    $CacheBase, %esi
@@ -331,8 +316,6 @@ fam10_end_part1:
        xorl    %eax, %eax
        rep     stosl
 
-#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
-
        /* set up the stack pointer */
        movl    $(CacheBase + CacheSize - GlobalVarSize), %eax
        movl    %eax, %esp

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 2d36eac67ff8ecd2fc43de8bee89592102de00ca..4781b0521cc456e0b6099180f1a457c8a3936457 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -29,8 +29,6 @@
        movl    %eax, %ebp
 
 cache_as_ram:
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
        post_code(0x20)
 
        /* Send INIT IPI to all excluding ourself */
@@ -134,7 +132,6 @@ clear_mtrrs:
         movl   %cr0, %eax
        andl    $( ~( (1 << 30) | (1 << 29) ) ), %eax
        movl    %eax, %cr0
-#endif
 
        /* Set up stack pointer */
 #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 28d510066d418a10ea68d951631b85409c93a394..848c84d2c224773a6c7f9569313d5e73838bbf14 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -29,8 +29,6 @@
        movl    %eax, %ebp
 
 cache_as_ram:
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
        post_code(0x20)
 
        /* Send INIT IPI to all excluding ourself */
@@ -123,7 +121,6 @@ clear_mtrrs:
         movl   %cr0, %eax
        andl    $( ~( (1 << 30) | (1 << 29) ) ), %eax
        movl    %eax, %cr0
-#endif
 
        /* Set up stack pointer */
 #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index a664da2f873607ec0266d73c4d72911e75bd15db..50f9608dcc85272deb5a3e29b42e45b222085b4b 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -29,8 +29,6 @@
        movl    %eax, %ebp
 
 cache_as_ram:
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
        post_code(0x20)
 
        /* Send INIT IPI to all excluding ourself */
@@ -130,7 +128,6 @@ clear_mtrrs:
         movl   %cr0, %eax
        andl    $( ~( (1 << 30) | (1 << 29) ) ), %eax
        movl    %eax, %cr0
-#endif
 
        /* Set up stack pointer */
 #if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)

diff --git a/src/cpu/x86/car/cache_as_ram.inc b/src/cpu/x86/car/cache_as_ram.inc
index bfc2ebdb31706f41ae6d09a98b56a9927ac3e492..cd37ac39ab6cad80993cea9be7c593d6afae6ca2 100644 (file)
--- a/src/cpu/x86/car/cache_as_ram.inc
+++ b/src/cpu/x86/car/cache_as_ram.inc
@@ -36,9 +36,6 @@
        movl    %eax, %ebp
 
 CacheAsRam:
-       /* hope we can skip the double set for normal part */
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
        // Check whether the processor has HT capability
        movl    $01, %eax
        cpuid
@@ -191,14 +188,6 @@ clear_fixed_var_mtrr_out:
        simplemask CacheSize, 0
        wrmsr
 
-#else
-       /* disable cache */
-       movl    %cr0, %eax
-       orl     $(0x1 << 30), %eax
-       movl    %eax, %cr0
-
-#endif /*  CONFIG_USE_FALLBACK_IMAGE == 1*/
-
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
@@ -225,8 +214,6 @@ clear_fixed_var_mtrr_out:
        andl    $0x9fffffff, %eax
        movl    %eax, %cr0
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
        /* Read the range with lodsl*/
        movl    $CacheBase, %esi
        cld
@@ -283,8 +270,6 @@ clear_fixed_var_mtrr_out:
 .xout1x:
 
 #endif
-#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
-
 
        movl    $(CacheBase + CacheSize - 4), %eax
        movl    %eax, %esp
@@ -319,7 +304,6 @@ var_mtrr_msr:
        .long   0x20C, 0x20D, 0x20E, 0x20F
        .long   0x000 /* NULL, end of table */
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
        .align 0x1000
        .code16
 .global LogicalAP_SIPI
@@ -349,5 +333,4 @@ Halt_LogicalAP:
        hlt
        jmp     Halt_LogicalAP
        .code32
-#endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
 .CacheAsRam_out:

diff --git a/src/include/fallback.h b/src/include/fallback.h
index baf868412840d7d5e7361b4e002108938067e8ef..4af826616a16515c335fa9e0744834128cf7c31d 100644 (file)
--- a/src/include/fallback.h
+++ b/src/include/fallback.h
@@ -3,12 +3,7 @@
 
 #ifndef ASSEMBLY
 
-#if CONFIG_HAVE_FALLBACK_BOOT == 1
 void set_boot_successful(void);
-#else
-#define set_boot_successful()
-#endif
-
 void boot_successful(void);
 
 #endif /* ASSEMBLY */

diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index e2da65cf91b19bf9d68eb4f3f57a3aa2c9072389..5cf703bf267ab6af7667dcd03a1dadeb0e2379c9 100644 (file)
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -5,7 +5,6 @@
 #include <arch/io.h>
 
 
-#if CONFIG_HAVE_FALLBACK_BOOT == 1
 void set_boot_successful(void)
 {
        /* Remember I succesfully booted by setting
@@ -26,7 +25,6 @@ void set_boot_successful(void)
                byte &= 0x0f;
        outb(byte, RTC_PORT(1));
 }
-#endif
 
 void boot_successful(void)
 {

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index ebb47f1cdc38164b75609ccd2fad9960db450117..eb0adc5fc8d27f67009eddf723c8491c2a6f710a 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -58,14 +58,12 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -80,8 +78,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
 #include "cpu/x86/bist.h"
 
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
 static int smbus_read_byte(u32 device, u32 address);
 
 #include "superio/ite/it8718f/it8718f_early_serial.c"
@@ -128,13 +124,10 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
-
 
 #include "northbridge/amd/amdfam10/early_ht.c"
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
 //#include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -306,5 +299,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x43);        // Should never see this post code.
 }
 
-
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 470a7ee40a3c36e3301493d190729fe61f4afa36..0bf5864870aec7ddc9f000f47f6ab23f9c8a1b66 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -43,21 +43,18 @@ static void post_code(uint8_t value) {
 #endif
 }
 #endif
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
 
 
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -152,13 +149,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -336,4 +330,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif

diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 3e9b7a5941f2b8c4bcc617a332de7743336d8f49..b63dc1099bfb47eaaf9e919d90c8b4dcda7e4d6d 100644 (file)
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -58,7 +58,6 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
 #include "arch/i386/lib/console.c"
 #include "pc80/serial.c"
 #include "lib/ramtest.c"
@@ -66,7 +65,6 @@ static void post_code(u8 value) {
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
-#endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
@@ -80,8 +78,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
 #include "cpu/x86/bist.h"
 
 
-#if (CONFIG_USE_FAILOVER_IMAGE == 0)
-
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -141,13 +137,10 @@ static int spd_read_byte(u32 device, u32 address)
 #include "cpu/amd/model_10xxx/init_cpus.c"
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif /* (CONFIG_USE_FAILOVER_IMAGE == 0) */
-
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
-#if (CONFIG_USE_FAILOVER_IMAGE==0)
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -316,5 +309,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-
-#endif /* CONFIG_USE_FAILOVER_IMAGE==0 */

diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 92ad54216e4136a0fb840b039e940536be59e153..6cf71b0b4008c9b1a2414a4cf07651886556a389 100644 (file)
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -47,8 +47,6 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 /* Used by ck894_early_setup(). */
 #define CK804_NUM 1
 
@@ -96,8 +94,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif /* CONFIG_USE_FAILOVER_IMAGE */
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -118,7 +114,6 @@ static void sio_setup(void)
        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -200,4 +195,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-#endif /* CONFIG_USE_FAILOVER_IMAGE */

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
index 348139b50198fc0cd85a4a9e13b4081833c41ba4..9873d6d431e1f5356f023c86a6e5183983bcab18 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
+++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig
@@ -75,16 +75,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_GIGABYTE_GA_2761GXDK
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_GIGABYTE_GA_2761GXDK
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_GIGABYTE_GA_2761GXDK
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 0444e4916631267ae6548bc1dd61f2476c8b6185..1819b901c8da44b04cfd1266140917c547710be9 100644 (file)
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -56,7 +56,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -73,15 +72,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -150,8 +145,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 
@@ -175,8 +168,6 @@ static void sio_setup(void)
         pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
@@ -303,5 +294,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-
-#endif

diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 098312cc9a03f517a4fe05f12576bc849c951d86..5a4f0a7dc7148fdd8d25842f5e70b5b8a66cc8ef 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -78,16 +78,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_GIGABYTE_M57SLI
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_GIGABYTE_M57SLI
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_GIGABYTE_M57SLI
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index bd67ab95955ea0de58cf58b71e2635dd081c847a..4226ac36144cc620ac897d40ddc59a44883492c6 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -54,7 +54,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8716f/it8716f_early_serial.c"
 #include "superio/ite/it8716f/it8716f_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -148,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -175,8 +168,6 @@ static void sio_setup(void)
 }
 
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
@@ -316,5 +307,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-
-#endif

diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index db65f65493767837fef565cf83d42b9700735f97..64b1c79b7213609b7e9fd1ca3b167b12f7e9a947 100644 (file)
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -61,7 +61,6 @@
 #include "pc80/mc146818rtc_early.c"
 
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -73,8 +72,6 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
@@ -83,8 +80,6 @@
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -153,8 +148,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 #if 0
@@ -195,8 +188,6 @@ static void setup_early_ipmi_serial()
 }
 #endif
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -312,4 +303,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-#endif

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index bac2a0bc966c3e1b345c744e0134d54bf1349fec..1441bb559720ca42f62f0b58bd104a0a201db3dc 100644 (file)
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -216,9 +216,7 @@ static void early_ich7_init(void)
        RCBA32(0x2034) = reg32;
 }
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
 
 #include <cbmem.h>
 

diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index d928de5c56dc5016f3638547a9a42ca088235e72..4a04b9a091bb45b34cca4db037498be3d2be2084 100644 (file)
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -121,9 +121,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i3100/cmos_failover.c"
-#endif
 
 void early_config(void) {
        device_t dev;

diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 54ae5dde9b192875fbafa37318ccb6b47c590ef2..901b18fe5ff2eb774d8ce20fa9dfede4683b3ed7 100644 (file)
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -32,21 +32,17 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
-
 
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -128,13 +124,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -260,4 +253,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif

diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 0131d443e958e47ef53d11e38d05d74a38634703..6231fd9962830a50f593004f52f3a046bfe5ae9c 100644 (file)
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -32,21 +32,17 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
-
 
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -128,13 +124,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -260,4 +253,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif

diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 0131d443e958e47ef53d11e38d05d74a38634703..9c1487374fcca3758e54288c95681a0ede817650 100644 (file)
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -32,21 +32,16 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
-#endif
-
-
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "cpu/x86/bist.h"
 
 #include "lib/delay.c"
@@ -128,13 +123,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 #include "cpu/amd/model_fxx/fidvid.c"
-#endif
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -260,4 +252,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 
 }
-#endif

diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 6ea41b6e4ba3f6bd0c7c173c598de762907278a1..32cd1c7ff92c3ac268bea7d5189ae2677653889a 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -352,9 +352,7 @@ static void early_ich7_init(void)
        RCBA32(0x2034) = reg32;
 }
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
 
 #include <cbmem.h>
 

diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 54753b28190b4aa056ce6208e44b6798229ba674..66a29b9fc66d40035266cd825abdbe4177128cfd 100644 (file)
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -47,8 +47,6 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 /* Used by ck804_early_setup(). */
 #define CK804_NUM 1
 #define CK804_USE_NIC 1
@@ -98,8 +96,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/car/post_cache_as_ram.c"
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif /* CONFIG_USE_FAILOVER_IMAGE */
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -121,7 +117,6 @@ static void sio_setup(void)
        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -204,4 +199,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-#endif /* CONFIG_USE_FAILOVER_IMAGE */

diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index ce7a6b27346ea1431930438a01333e8c2cfe4b00..52a3651c262f756d0334c5ab8674592d2021a547 100644 (file)
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_MSI_MS7260
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_MSI_MS7260
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_MSI_MS7260
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 635284175501929539a3a518dd8ad00255cf623e..f2e654bb6d3772ba00ad6bd4f26f5c143f11a7ad 100644 (file)
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -58,8 +58,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -73,15 +71,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
@@ -129,8 +123,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -152,8 +144,6 @@ static void sio_setup(void)
        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE == 0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr[] = {
@@ -282,4 +272,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();
 }
 
-#endif

diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig
index eeeafda55d802dae27d2b8440018af8b10bccba1..1cc800be09a85780728614009febd90f371ba31a 100644 (file)
--- a/src/mainboard/msi/ms9282/Kconfig
+++ b/src/mainboard/msi/ms9282/Kconfig
@@ -70,16 +70,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_MSI_MS9282
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_MSI_MS9282
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_MSI_MS9282
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index c595f63b3b888e7a4c860418667b277eac35d9f8..87e20cc3e2fabaf60c345203b9c7997b5f78f568 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -42,26 +42,6 @@ config CONFIG_ACPI_SSDTX_NUM
        default 0x1F
        depends on BOARD_MSI_MS9652_FAM10
 
-config USE_FALLBACK_IMAGE
-       bool
-       default y
-       depends on BOARD_MSI_MS9652_FAM10
-
-config HAVE_FALLBACK_BOOT
-       bool
-       default y
-       depends on BOARD_MSI_MS9652_FAM10
-
-config CONFIG_USE_FAILOVER_IMAGE
-       bool
-       default y
-       depends on BOARD_MSI_MS9652_FAM10
-
-config CONFIG_HAVE_FAILOVER_BOOT
-       bool
-       default y
-       depends on BOARD_MSI_MS9652_FAM10
-
 config GENERATE_PIRQ_TABLE
        bool
        default y

diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index f99f50b22ff1257528751af4ed14ad4786a90c5d..3ab04b0eeb3297ca44910006cc3fb27dc11c776b 100644 (file)
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -54,7 +54,6 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
@@ -68,14 +67,10 @@ static void post_code(u8 value) {
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -143,8 +138,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -163,7 +156,6 @@ static void sio_setup(void)
        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -323,5 +315,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x43);        // Should never see this post code.
 }
 
-
-#endif

diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index e12f0274f9eff7d31ee53d34f2a214d2fc685e1c..0db62a4c8f0608d5b798eb9a790f10a79e8142cd 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_NVIDIA_L1_2PVV
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_NVIDIA_L1_2PVV
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_NVIDIA_L1_2PVV
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 3e8f9e7ee3bc6f1b69359edfed8b1442530f9f29..ad04b5eeb3b47df3ce27ecc9fab4943cc7125461 100644 (file)
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -54,7 +54,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -148,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -175,7 +168,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
@@ -301,5 +293,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-
-#endif

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index b88b90749577b3d18bca145e4978dafd5b67e84b..1f4b85672736b4c58ad288ecb565071c82b21e54 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -259,9 +259,7 @@ static void early_ich7_init(void)
        RCBA32(0x2034) = reg32;
 }
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
 #include "southbridge/intel/i82801gx/cmos_failover.c"
-#endif
 
 static void init_artec_dongle(void)
 {

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index ac441a6ec8ed9edb761071d3eb79d364c8ecd3aa..4b08206a0fab1551749b302b7d5737d941eb72ff 100644 (file)
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -52,7 +52,6 @@
 // for enable the FAN
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -64,15 +63,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -191,8 +186,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -225,8 +218,6 @@ static void sio_setup(void)
 #define RC0 (2<<8)
 #define RC1 (1<<8)
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 /* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
@@ -371,4 +362,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-#endif

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 5b74c6059057aa2b6541847bbbc8870468dde478..1de0dc43f83c8269145ab07ce739c242e3cbce86 100644 (file)
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -55,7 +55,6 @@
 // for enable the FAN
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -67,15 +66,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -137,8 +132,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -167,8 +160,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
@@ -291,5 +282,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-
-#endif

diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index b09ae781f6b4de09e38498cd8da217a6359670e4..0648105d22df8a92e3ada0e80c49565fb3a09ffe 100644 (file)
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -54,7 +54,6 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -65,15 +64,11 @@ static void post_code(u8 value) {
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -133,8 +128,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -163,7 +156,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -317,5 +309,3 @@ post_code(0x40);
 
 }
 
-
-#endif

diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 1128b1130dba32fc0b842965efe554a6ef6a035d..45989aa5eb8b80013e9e8626f5f02792b39e3449 100644 (file)
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -54,7 +54,6 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -65,15 +64,11 @@ static void post_code(u8 value) {
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -136,8 +131,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -166,7 +159,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -360,5 +352,3 @@ post_code(0x40);
 
 }
 
-
-#endif

diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 72b1b68548aa9cab57f02b46fd53df8711609160..bb953edf546486b748210fb6abdb9c011a08474a 100644 (file)
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -19,7 +19,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
@@ -32,8 +31,6 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
@@ -42,8 +39,6 @@
 
 #define SUPERIO_GPIO_IO_BASE 0x400
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -114,8 +109,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/init_cpus.c"
 
-#endif
-
 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -147,8 +140,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
@@ -226,4 +217,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-#endif

diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 2dafde478e7de7a30a0a0ee0c7ad4aa36365d4c4..79ea97b4f358a37d47bf928b66279b87f2b09135 100644 (file)
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -76,16 +76,6 @@ config PCI_64BIT_PREF_MEM
         default n
        depends on BOARD_TYAN_S2912
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_TYAN_S2912
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_TYAN_S2912
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index c6be2cb88f394415b03ae079abc89202437e73f3..2fdff068e8d6b9e4c66641684ca8196f6609bbc5 100644 (file)
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -54,7 +54,6 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -70,15 +69,11 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/debug.c"
@@ -146,8 +141,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -174,8 +167,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
@@ -299,5 +290,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 }
 
-
-#endif

diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index 740932ff77396b106c3374979faf4c4203479879..e1ac2dc2227f15bfc8cab9b14fbf8aebd4c66ba0 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -38,26 +38,6 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE
        default 0x04000
        depends on BOARD_TYAN_S2912_FAM10
 
-config USE_FALLBACK_IMAGE
-       bool
-       default y
-       depends on BOARD_TYAN_S2912_FAM10
-
-config HAVE_FALLBACK_BOOT
-       bool
-       default y
-       depends on BOARD_TYAN_S2912_FAM10
-
-config CONFIG_USE_FAILOVER_IMAGE
-       bool
-       default y
-       depends on BOARD_TYAN_S2912_FAM10
-
-config CONFIG_HAVE_FAILOVER_BOOT
-       bool
-       default y
-       depends on BOARD_TYAN_S2912_FAM10
-
 config APIC_ID_OFFSET
        hex
        default 0
@@ -98,16 +78,6 @@ config PCI_64BIT_PREF_MEM
        default n
        depends on BOARD_TYAN_S2912_FAM10
 
-config HAVE_FALLBACK_BOOT
-       bool
-       default n
-       depends on BOARD_TYAN_S2912_FAM10
-
-config USE_FALLBACK_IMAGE
-       bool
-       default n
-       depends on BOARD_TYAN_S2912_FAM10
-
 config HW_MEM_HOLE_SIZEK
        hex
        default 0x100000

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index e8bca07ce5fed5a09d13eeb85274f1c19596f279..29e40602437524007677851dd225b7bcb26b985d 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -53,7 +53,6 @@ static void post_code(u8 value) {
        outb(value, 0x80);
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #if CONFIG_USBDEBUG_DIRECT
@@ -68,15 +67,11 @@ static void post_code(u8 value) {
 #include "northbridge/amd/amdfam10/raminit.h"
 #include "northbridge/amd/amdfam10/amdfam10.h"
 
-#endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
-
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdfam10/debug.c"
@@ -142,8 +137,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/model_10xxx/fidvid.c"
 
-#endif
-
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdfam10/early_ht.c"
 
@@ -168,7 +161,6 @@ static void sio_setup(void)
 
 }
 
-#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "spd_addr.h"
 #include "cpu/amd/microcode/microcode.c"
 #include "cpu/amd/model_10xxx/update_microcode.c"
@@ -317,5 +309,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_code(0x43);        // Should never see this post code.
 }
 
-
-#endif

diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index 222210217006ff31639a3ced691c67818ab5fd93..66b270cdffa0074fa4a33728638da4296585cbde 100644 (file)
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -3,8 +3,6 @@
  *  by yinghai.lu@amd.com
  */
 
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
 static void bcm5785_enable_rom(void)
 {
         unsigned char byte;
@@ -42,8 +40,6 @@ static void bcm5785_enable_lpc(void)
         byte |=(1<<1)|(1<<0);
         pci_write_config8(dev, 0x48, byte);
 }
-#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
-
 
 static void bcm5785_enable_wdt_port_cf9(void)
 {