2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007 Carl-Daniel Hailfinger
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 /* We will use 4K bytes only */
27 /* disable HyperThreading is done by eswar*/
28 /* other's is the same as AMD except remove amd specific msr */
30 #define CacheSize CONFIG_DCACHE_RAM_SIZE
31 #define CacheBase (0xd0000 - CacheSize)
33 #include <cpu/x86/mtrr.h>
35 /* Save the BIST result */
39 /* hope we can skip the double set for normal part */
40 #if CONFIG_USE_FALLBACK_IMAGE == 1
42 // Check whether the processor has HT capability
51 // It is a HT processor; Send SIPI to the other logical processor
52 // within this processor so that the CAR related common system registers
53 // are programmed accordingly
55 // Use some register that is common to both logical processors
56 // as semaphore. Refer Appendix B, Vol.3
62 // Figure out the logical AP's APIC ID; the following logic will work
63 // only for processors with 2 threads
64 // Refer to Vol 3. Table 7-1 for details about this logic
65 movl $0xFEE00020, %esi
67 andl $0xFF000000, %ebx
76 bswapl %ebx // ebx - logical AP's APIC ID
78 // Fill up the IPI command registers in the Local APIC mapped to default address
79 // and issue SIPI to the other logical processor within this processor die.
82 movl $0xFEE00310, %esi
85 // SIPI vector - F900:0000
86 movl $0x000006F9, %eax
87 movl $0xFEE00300, %esi
97 andl $0x00001000, %eax
100 // Wait for the Logical AP to complete initialization
101 LogicalAP_SIPINotdone:
105 jz LogicalAP_SIPINotdone
110 /* Set the default memory type and enable fixed and variable MTRRs */
111 movl $MTRRdefType_MSR, %ecx
113 /* Enable Variable and Fixed MTRRs */
114 movl $0x00000c00, %eax
118 /* Clear all MTRRs */
120 movl $fixed_mtrr_msr, %esi
122 clear_fixed_var_mtrr:
125 jz clear_fixed_var_mtrr_out
131 jmp clear_fixed_var_mtrr
132 clear_fixed_var_mtrr_out:
134 /* 0x06 is the WB IO type for a given 4k segment.
135 * segs is the number of 4k segments in the area of the particular
136 * register we want to use for CAR.
137 * reg is the register where the IO type should be stored.
139 .macro extractmask segs, reg
141 /* The xorl here is superfluous because at the point of first execution
142 * of this macro, %eax and %edx are cleared. Later invocations of this
143 * macro will have a monotonically increasing segs parameter.
147 movl $0x06000000, \reg /* WB IO type */
149 movl $0x06060000, \reg /* WB IO type */
151 movl $0x06060600, \reg /* WB IO type */
153 movl $0x06060606, \reg /* WB IO type */
157 /* size is the cache size in bytes we want to use for CAR.
158 * windowoffset is the 32k-aligned window into CAR size
160 .macro simplemask carsize, windowoffset
161 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
162 extractmask gas_bug_workaround, %eax
163 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
164 extractmask gas_bug_workaround, %edx
165 /* Without the gas bug workaround, the entire macro would consist only of the
167 extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
168 extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
172 #if CacheSize > 0x10000
173 #error Invalid CAR size, must be at most 64k.
175 #if CacheSize < 0x1000
176 #error Invalid CAR size, must be at least 4k. This is a processor limitation.
178 #if (CacheSize & (0x1000 - 1))
179 #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
182 #if CacheSize > 0x8000
183 /* enable caching for 32K-64K using fixed mtrr */
184 movl $0x268, %ecx /* fix4k_c0000*/
185 simplemask CacheSize, 0x8000
189 /* enable caching for 0-32K using fixed mtrr */
190 movl $0x269, %ecx /* fix4k_c8000*/
191 simplemask CacheSize, 0
197 orl $(0x1 << 30), %eax
200 #endif /* CONFIG_USE_FALLBACK_IMAGE == 1*/
202 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
203 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
204 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
206 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
208 /* enable write base caching so we can do execute in place
213 movl $REAL_XIP_ROM_BASE, %eax
214 orl $MTRR_TYPE_WRBACK, %eax
218 movl $0x0000000f, %edx
219 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
221 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
225 andl $0x9fffffff, %eax
228 #if CONFIG_USE_FALLBACK_IMAGE == 1
230 /* Read the range with lodsl*/
231 movl $CacheBase, %esi
233 movl $(CacheSize >> 2), %ecx
236 /* Clear the range */
237 movl $CacheBase, %edi
238 movl $(CacheSize >> 2), %ecx
244 /* check the cache as ram */
245 movl $CacheBase, %esi
246 movl $(CacheSize>>2), %ecx
256 movl $CacheBase, %esi
257 // movl $(CacheSize>>2), %ecx
271 je .xin2 /* dont show */
286 #endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/
289 movl $(CacheBase + CacheSize - 4), %eax
292 /* Load a different set of data segments */
294 movw $CACHE_RAM_DATA_SEG, %ax
301 /* Restore the BIST result */
304 /* We need to set ebp ? No need */
306 pushl %eax /* bist */
308 /* We will not go back */
311 .long 0x250, 0x258, 0x259
312 .long 0x268, 0x269, 0x26A
313 .long 0x26B, 0x26C, 0x26D
316 .long 0x200, 0x201, 0x202, 0x203
317 .long 0x204, 0x205, 0x206, 0x207
318 .long 0x208, 0x209, 0x20A, 0x20B
319 .long 0x20C, 0x20D, 0x20E, 0x20F
320 .long 0x000 /* NULL, end of table */
322 #if CONFIG_USE_FALLBACK_IMAGE == 1
325 .global LogicalAP_SIPI
327 // cr0 register is shared among the logical processors;
328 // so clear CD & NW bits so that the BSP's cr0 register
329 // controls the cache behavior
330 // Note: The cache behavior is determined by "OR" result
331 // of the cr0 registers of the logical processors
334 andl $0x9FFFFFFF, %eax
339 // Set the semaphore to indicate the Logical AP is done
340 // with CAR specific initialization
352 #endif /*CONFIG_USE_FALLBACK_IMAGE == 1*/