src/mainboard/tyan/s2895/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define K8_ALLOCATE_IO_RANGE 1
   5
   6 #define QRANK_DIMM_SUPPORT 1
   7
   8 #if CONFIG_LOGICAL_CPUS==1
   9 #define SET_NB_CFG_54 1
  10 #endif
  11
  12 #include <stdint.h>
  13 #include <string.h>
  14 #include <device/pci_def.h>
  15 #include <arch/io.h>
  16 #include <device/pnp_def.h>
  17 #include <arch/romcc_io.h>
  18 #include <cpu/x86/lapic.h>
  19 #include "option_table.h"
  20 #include "pc80/mc146818rtc_early.c"
  21
  22 #if CONFIG_USE_FAILOVER_IMAGE==0
  23 #include "pc80/serial.c"
  24 #include "arch/i386/lib/console.c"
  25 #include "lib/ramtest.c"
  26
  27 #include <cpu/amd/model_fxx_rev.h>
  28
  29 #include "northbridge/amd/amdk8/incoherent_ht.c"
  30 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33 #include "lib/delay.c"
  34
  35 #endif
  36
  37 #include "cpu/x86/lapic/boot_cpu.c"
  38 #include "northbridge/amd/amdk8/reset_test.c"
  39 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  40 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  41 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  42
  43 #define SUPERIO_GPIO_IO_BASE 0x400
  44
  45 #if CONFIG_USE_FAILOVER_IMAGE==0
  46
  47 #include "cpu/x86/bist.h"
  48
  49 #include "northbridge/amd/amdk8/debug.c"
  50
  51 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  52
  53 #include "northbridge/amd/amdk8/setup_resource_map.c"
  54
  55 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  56
  57 static void memreset_setup(void)
  58 {
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 static void sio_gpio_setup(void){
  66
  67         unsigned value;
  68
  69         /*Enable onboard scsi*/
  70         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  71         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  72         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  73
  74 }
  75
  76 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  77 {
  78         /* nothing to do */
  79 }
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86 #include "northbridge/amd/amdk8/raminit.c"
  87 #include "northbridge/amd/amdk8/coherent_ht.c"
  88 #include "lib/generic_sdram.c"
  89
  90  /* tyan does not want the default */
  91 #include "resourcemap.c"
  92
  93 #include "cpu/amd/dualcore/dualcore.c"
  94
  95 #define CK804_NUM 2
  96 #define CK804_USE_NIC 1
  97 #define CK804_USE_ACI 1
  98
  99 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 100
 101 //set GPIO to input mode
 102 #define CK804_MB_SETUP \
 103         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 104         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 105         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 106         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 107         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 108         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 109
 110 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 111
 112 #include "cpu/amd/car/copy_and_run.c"
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116
 117 #endif
 118
 119 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 120 #include "northbridge/amd/amdk8/early_ht.c"
 121
 122 static void sio_setup(void)
 123 {
 124
 125         unsigned value;
 126         uint32_t dword;
 127         uint8_t byte;
 128
 129         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 130
 131         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 132         byte |= 0x20;
 133         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 134
 135         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 136         dword |= (1<<29)|(1<<0);
 137         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 138
 139         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 140         dword |= (1<<16);
 141         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 142
 143         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 144         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 145         value &= 0xbf;
 146         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 147
 148 }
 149
 150 #if CONFIG_USE_FAILOVER_IMAGE==0
 151
 152 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 153 {
 154         static const uint16_t spd_addr [] = {
 155                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 156                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 157 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 158                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 159                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 160 #endif
 161         };
 162
 163         int needs_reset;
 164         unsigned bsp_apicid = 0;
 165
 166         struct mem_controller ctrl[8];
 167         unsigned nodes;
 168
 169         if (!cpu_init_detectedx && boot_cpu()) {
 170                 /* Nothing special needs to be done to find bus 0 */
 171                 /* Allow the HT devices to be found */
 172
 173                 enumerate_ht_chain();
 174
 175                 sio_setup();
 176
 177                 /* Setup the ck804 */
 178                 ck804_enable_rom();
 179         }
 180
 181         if (bist == 0) {
 182                 bsp_apicid = init_cpus(cpu_init_detectedx);
 183         }
 184
 185 //      post_code(0x32);
 186
 187         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 188         uart_init();
 189         console_init();
 190
 191         /* Halt if there was a built in self test failure */
 192         report_bist_failure(bist);
 193
 194         sio_gpio_setup();
 195
 196         setup_mb_resource_map();
 197
 198         needs_reset = setup_coherent_ht_domain();
 199
 200         wait_all_core0_started();
 201 #if CONFIG_LOGICAL_CPUS==1
 202         // It is said that we should start core1 after all core0 launched
 203         start_other_cores();
 204         wait_all_other_cores_started(bsp_apicid);
 205 #endif
 206
 207         needs_reset |= ht_setup_chains_x();
 208
 209         needs_reset |= ck804_early_setup_x();
 210
 211         if (needs_reset) {
 212                 printk_info("ht reset -\n");
 213                 soft_reset();
 214         }
 215
 216         allow_all_aps_stop(bsp_apicid);
 217
 218         nodes = get_nodes();
 219         //It's the time to set ctrl now;
 220         fill_mem_ctrl(nodes, ctrl, spd_addr);
 221
 222         enable_smbus();
 223
 224         memreset_setup();
 225         sdram_initialize(nodes, ctrl);
 226
 227         post_cache_as_ram();
 228 }
 229 #endif