* combination:
*/
-struct chip;
struct device {
struct bus * bus; /* bus this device is on */
device_t sibling; /* next device on this bus */
#define ASSEMBLY 1
-#define MAXIMUM_CONSOLE_LOGLEVEL 9
-#define DEFAULT_CONSOLE_LOGLEVEL 9
+//#define MAXIMUM_CONSOLE_LOGLEVEL 9
+//#define DEFAULT_CONSOLE_LOGLEVEL 9
#include <stdint.h>
#include <device/pci_def.h>
*/
uint32_t ret = 0x00010101; /* default row entry */
-
+/*
static const unsigned int rows_2p[2][2] = {
{0x00030101, 0x00010202},
{0x00010202, 0x00030101}
};
+*/
static const unsigned int rows_4p[4][4] = {
{0x00070101, 0x00010202, 0x00030404, 0x00010204},
};
if (!(node >= maxnodes || row >= maxnodes)) {
+/*
if (maxnodes == 2)
ret = rows_2p[node][row];
if (maxnodes == 4)
+*/
ret = rows_4p[node][row];
}
#include "fakespd.c"
#endif
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
.channel1 = {RC3 | DIMM1, RC3 | DIMM3, 0, 0},
}
};
+
+ static const struct ht_chain ht_c[] = {
+ { /* Link 2 of CPU0 */
+ .udev = PCI_DEV(0, 0x18, 0),
+ .upos = 0xc0,
+ .devreg = 0xe0, /* Preset bus num in resource map */
+ },
+ { /* Link 1 of CPU1 */
+ .udev = PCI_DEV(0, 0x19, 0),
+ .upos = 0xa0,
+ .devreg = 0xe4, /* Preset bus num in resource map */
+ },
+ };
+
int needs_reset;
enable_lapic();
console_init();
setup_quartet_resource_map();
needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Build the objects we have code for in this directory.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
driver mainboard.o
-#dir /drivers/lsi/53c1030
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#dir /drivers/broadcom/tg3_ipmi
-dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=2
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### When debugging disable the watchdog timer
-###
-##option MAXIMUM_CONSOLE_LOGLEVEL=7
-#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#
-#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
-#
-###
-### Romcc output
-###
+#object reset.o
+##
+## Romcc output
+##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
- depends "./romcc ./failover.E"
+ depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
###
-### Include the secondary Configuration files
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8111 "amd8111" link 0
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
dir /pc80
-#dir /bioscall
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
+config chip.h
+
+# sample config for tyan/s2850
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on # LDT0
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
end
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(1, 0x02, 0), 0x47, 1);
+}
+
#define REV_B_RESET 0
static void memreset_setup(void)
{
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
#include "sdram/generic_sdram.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
-static void main(void)
+
+static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
};
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-extern struct chip_control mainboard_tyan_s2850_control;
+extern struct chip_operations mainboard_tyan_s2850_ops;
struct mainboard_tyan_s2850_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
+
#if 0
static void print_pci_regs(struct device *dev)
{
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
pci_write_config8(dev, 0x43, byte);
}
#endif
+#if 0
static void onboard_scsi_fixup(void)
{
struct device *dev;
-#if 0
+#if 1
unsigned char i,j,k;
- for(i=0;i<=6;i++) {
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
// print_mem();
// amd8111_enable_rom();
}
+#endif
#if 0
static void vga_fixup(void) {
// we do this right here because:
#endif
#if CONFIG_VGABIOS == 1
printk_debug("DO THE VGA BIOS\n");
- do_vgabios();
+ do_vgabios(0x0600);
post_code(0x93);
#endif
}
-#endif
+#endif
+
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s2850_config *conf =
- (struct mainboard_tyan_s2850_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_PCI:
// case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
- if (conf->fixup_scsi)
- onboard_scsi_fixup();
+// if (conf->fixup_scsi)
+// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
}
}
-void final_mainboard_fixup(void)
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
+ unsigned bus;
+ unsigned devfn;
+#if 0
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
#if 0
- enable_ide_devices();
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
#endif
}
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
-};
-static void enumerate(struct chip *chip)
+static void debug_noop(device_t dummy)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
- }
}
-struct chip_control mainboard_tyan_s2850_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s2850 mainboard ",
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
};
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2850_ops = {
+ .name = "Tyan s2850 mainboard ",
+ .enable_dev = enable_dev,
+};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
/* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
- printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+ printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8111_1 = 2;
bus_isa = 3;
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+arch i386 end
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Build the objects we have code for in this directory.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
driver mainboard.o
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /driver/intel/82551
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=5
-default HARD_RESET_FUNCTION=0
-#
-#
-arch i386 end
-
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-end
+#object reset.o
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-###
-### Romcc output
-###
+##
+## Romcc output
+##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
- depends "./romcc ./failover.E"
+ depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
-
makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
-#
###
-### Include the secondary Configuration files
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-dir /pc80
-
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8151 "amd8151" link 0
- pci 0:0.0
- pci 0:1.0
- end
- southbridge amd/amd8111 "amd8111" link 0
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 on
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
+###
+### O.k. We aren't just an intermediary anymore!
+###
-#dir /bioscall
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
-end
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
-cpu k8 "cpu1"
+# sample config for tyan/s2875
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
end
#define ASSEMBLY 1
-
+
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1);
}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(1, 0x05, 0), 0x47, 1);
+}
+
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
*/
uint32_t ret=0x00010101; /* default row entry */
-
+/*
+ (L1) (L1) (L0)
+ CPU1-------------CPU0--------8151---------8111
+*/
+ /* Link1 of CPU0 to Link1 of CPU1 */
static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 }
return smbus_read_byte(device, address);
}
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
};
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
+
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+// report_bist_failure(bist);
+
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-extern struct chip_control mainboard_tyan_s2875_control;
+extern struct chip_operations mainboard_tyan_s2875_ops;
struct mainboard_tyan_s2875_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0,1
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
+
#if 0
static void print_pci_regs(struct device *dev)
{
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
static void onboard_scsi_fixup(void)
{
struct device *dev;
-#if 1
+#if 1
unsigned char i,j,k;
- for(i=0;i<=6;i++) {
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
#endif
-
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s2875_config *conf =
- (struct mainboard_tyan_s2875_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
- // onboard_scsi_fixup();
+// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
}
}
-void final_mainboard_fixup(void)
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
+ unsigned bus;
+ unsigned devfn;
#if 0
- enable_ide_devices();
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
+#if 0
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
#endif
}
+
+static void debug_noop(device_t dummy)
+{
+}
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
+};
+
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+
static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
};
-static void enumerate(struct chip *chip)
+static void enable_dev(struct device *dev)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
- }
+ dev_root.ops = &mainboard_operations;
}
-struct chip_control mainboard_tyan_s2875_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s2875 mainboard ",
+struct chip_operations mainboard_tyan_s2875_ops = {
+ .name = "Tyan s2875 mainboard ",
+ .enable_dev = enable_dev,
};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
driver mainboard.o
-#dir /drivers/lsi/53c1030
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-###
-### Romcc output
-###
+#object reset.o
+##
+## Romcc output
+##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
+ depends "$(MAINBOARD)/auto.c option_table.h "
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
###
-### Include the secondary Configuration files
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 0
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
- end
- southbridge amd/amd8111 "amd8111" link 0
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
+###
+### O.k. We aren't just an intermediary anymore!
+###
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+##
+## Include the secondary Configuration files
+##
dir /pc80
-#dir /bioscall
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
+config chip.h
+
+# sample config for tyan/s2880
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
-cpu k8 "cpu1"
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
end
+
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
+}
+
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
*/
uint32_t ret=0x00010101; /* default row entry */
-
+ /* Link1 of CPU0 to Link1 of CPU1 */
static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 }
return smbus_read_byte(device, address);
}
-/* include mainboard specific ht code */
-//#include "hypertransport.c"
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
#endif
};
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
+
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+// report_bist_failure(bist);
+
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-extern struct chip_control mainboard_tyan_s2880_control;
+extern struct chip_operations mainboard_tyan_s2880_ops;
struct mainboard_tyan_s2880_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0,1
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
-#if 1
+
+#if 0
static void print_pci_regs(struct device *dev)
{
uint8_t byte;
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
pci_write_config8(dev, 0x43, byte);
}
#endif
+#if 0
static void onboard_scsi_fixup(void)
{
struct device *dev;
-#if 0
+#if 1
unsigned char i,j,k;
- for(i=0;i<=6;i++) {
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
// print_mem();
// amd8111_enable_rom();
}
+#endif
#if 0
static void vga_fixup(void) {
// we do this right here because:
#endif
#if CONFIG_VGABIOS == 1
printk_debug("DO THE VGA BIOS\n");
- do_vgabios();
+ do_vgabios(0x0600);
post_code(0x93);
#endif
}
-#endif
+#endif
+
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s2880_config *conf =
- (struct mainboard_tyan_s2880_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_PCI:
// case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
- if (conf->fixup_scsi)
- onboard_scsi_fixup();
+// if (conf->fixup_scsi)
+// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
}
}
-void final_mainboard_fixup(void)
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
+ unsigned bus;
+ unsigned devfn;
#if 0
- enable_ide_devices();
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
+#if 0
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
#endif
}
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
-};
-static void enumerate(struct chip *chip)
+static void debug_noop(device_t dummy)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
- }
}
-struct chip_control mainboard_tyan_s2880_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s2880 mainboard ",
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
};
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2880_ops = {
+ .name = "Tyan s2880 mainboard ",
+ .enable_dev = enable_dev,
+};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
- uint32_t base;
+
+ device_t dev;
+ struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 3, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 4, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
+
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
driver mainboard.o
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#dir /drivers/broadcom/tg3_ipmi
-dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
+
+makerule ./failover.inc
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
-#
-#### Should this be in the northbridge code?
+
+### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
+
+##
+## Include an id string (For safe flashing)
+##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
+
###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-#
if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-#
-#
-###
-### Setup the serial port
###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### Romcc output
+### O.k. We aren't just an intermediary anymore!
###
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
-end
-
-makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
-end
-makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
-end
-mainboardinit cpu/k8/enable_mmx_sse.inc
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Include the secondary Configuration files
-###
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+##
+## Include the secondary Configuration files
+##
dir /pc80
+config chip.h
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 2
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
- end
- southbridge amd/amd8111 "amd8111" link 2
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
-end
-
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
-
+# sample config for tyan/s2881
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
-#dir /bioscall
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
end
-cpu k8 "cpu1"
-end
#define ASSEMBLY 1
+
#include <stdint.h>
-#include <device/pci_def.h>
+#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
+}
+
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
*/
uint32_t ret=0x00010101; /* default row entry */
-
+ /* Link0 of CPU0 to Link0 of CPU1 */
static const unsigned int rows_2p[2][2] = {
{ 0x00030101, 0x00010202 },
{ 0x00010202, 0x00030101 }
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
#endif
};
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+// report_bist_failure(bist);
+
setup_s2881_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
-extern struct chip_control mainboard_tyan_s2881_control;
+extern struct chip_operations mainboard_tyan_s2881_ops;
struct mainboard_tyan_s2881_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0,1
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
word = 0x10f1;
pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
// Set the subsytem id
- word = 0x2881;
+ word = 0x2880;
pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
// Disable writes to the device id
byte = 0;
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
+
#if 0
static void print_pci_regs(struct device *dev)
{
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
pci_write_config8(dev, 0x43, byte);
}
#endif
+#if 0
static void onboard_scsi_fixup(void)
{
struct device *dev;
-#if 0
+#if 1
unsigned char i,j,k;
- for(i=0;i<=6;i++) {
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
// print_mem();
// amd8111_enable_rom();
}
+#endif
#if 0
static void vga_fixup(void) {
// we do this right here because:
#endif
#if CONFIG_VGABIOS == 1
printk_debug("DO THE VGA BIOS\n");
- do_vgabios();
+ do_vgabios(0x0600);
post_code(0x93);
#endif
}
-#endif
+#endif
+
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s2881_config *conf =
- (struct mainboard_tyan_s2881_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
- // onboard_scsi_fixup();
+// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
-// printk_debug("mainboard fixup pass %d done\r\n",pass);
+ printk_debug("mainboard fixup pass %d done\r\n",
+ pass);
break;
}
}
-void final_mainboard_fixup(void)
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
+ unsigned bus;
+ unsigned devfn;
+#if 0
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
#if 0
- enable_ide_devices();
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
#endif
}
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
-};
-static void enumerate(struct chip *chip)
+static void debug_noop(device_t dummy)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
- }
}
-struct chip_control mainboard_tyan_s2881_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s2881 mainboard ",
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
};
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2881_ops = {
+ .name = "Tyan s2881 mainboard ",
+ .enable_dev = enable_dev,
+};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
- uint32_t base;
+ device_t dev;
+ struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 3, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 4, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
+
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
driver mainboard.o
-#dir /drvers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551_ipmi
-dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### When debugging disable the watchdog timer
-###
-##option MAXIMUM_CONSOLE_LOGLEVEL=7
-#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#
-#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
-#
-###
-### Romcc output
-###
+#object reset.o
+##
+## Romcc output
+##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Include the secondary Configuration files
-###
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 0
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
- end
- southbridge amd/amd8111 "amd8111" link 0
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
dir /pc80
-#dir /bioscall
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
+config chip.h
-cpu k8 "cpu1"
+# sample config for tyan/s2882
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
end
+
#define ASSEMBLY 1
+
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
+#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+}
+
#define REV_B_RESET 0
static void memreset_setup(void)
*/
uint32_t ret=0x00010101; /* default row entry */
-
+ /* Link1 of CPU0 to Link1 of CPU1 */
static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 }
};
-
+#if 0
if(maxnodes>2) {
- print_debug("this mainboard is only designed for 2 cpus\r\n");
+ printo_debug("this mainboard is only designed for 2 cpus\r\n");
maxnodes=2;
}
-
+#endif
if (!(node>=maxnodes || row>=maxnodes)) {
ret=rows_2p[node][row];
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
+
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
};
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
+
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
}
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+
+ /* Halt if there was a built in self test failure */
+// report_bist_failure(bist);
+
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
-extern struct chip_control mainboard_tyan_s2882_control;
+extern struct chip_operations mainboard_tyan_s2882_ops;
struct mainboard_tyan_s2882_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
0x746b, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x8d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ 0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0,1
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
+
#if 0
static void print_pci_regs(struct device *dev)
{
for(i=0;i<256;i++) {
byte = pci_read_config8(dev, i);
- if((i%16)==0) printk_info("\n%02x:",i);
+ if((i%16)==0) printk_debug("\n%02x:",i);
printk_debug(" %02x",byte);
}
printk_debug("\n");
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
pci_write_config8(dev, 0x43, byte);
}
#endif
+#if 0
static void onboard_scsi_fixup(void)
{
- struct device *dev;
+ struct device *dev;
+#if 1
unsigned char i,j,k;
-#if 0
- for(i=0;i<=5;i++) {
+
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
// print_mem();
// amd8111_enable_rom();
}
-/*
+#endif
+#if 0
static void vga_fixup(void) {
// we do this right here because:
// - all the hardware is working, and some VGA bioses seem to need
#endif
#if CONFIG_VGABIOS == 1
printk_debug("DO THE VGA BIOS\n");
- do_vgabios();
+ do_vgabios(0x0600);
post_code(0x93);
#endif
}
- */
+#endif
+
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s2882_config *conf =
- (struct mainboard_tyan_s2882_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_CONSOLE:
// case CONF_PASS_PRE_PCI:
- case CONF_PASS_POST_PCI:
+// case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
// if (conf->fixup_scsi)
// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
-// printk_debug("mainboard fixup pass %d done\r\n",pass);
+ printk_debug("mainboard fixup pass %d done\r\n",
+ pass);
break;
}
}
-void final_mainboard_fixup(void)
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
+ unsigned bus;
+ unsigned devfn;
#if 0
- enable_ide_devices();
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
+#if 0
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
#endif
}
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
+
+static void debug_noop(device_t dummy)
+{
+}
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
};
-static void enumerate(struct chip *chip)
+static unsigned int scan_root_bus(device_t root, unsigned int max)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
- }
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
}
-struct chip_control mainboard_tyan_s2882_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s2882 mainboard ",
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
};
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2882_ops = {
+ .name = "Tyan s2882 mainboard ",
+ .enable_dev = enable_dev,
+};
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
+#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+#define ASSIGN_IRQ 0
+
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
- uint32_t base;
+ device_t dev;
+ struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 3, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 4, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
+
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
-
+#if ASSIGN_IRQ
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, 0x2, 0x13);
+
+ {
+ device_t dev;
+ dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x746b, 0);
+ if (dev) {
+ /* initialize PCI interupts - these assignments depend
+ on the PCB routing of PINTA-D
+
+ PINTA = IRQ5
+ PINTB = IRQ9
+ PINTC = IRQ11
+ PINTD = IRQ10
+ */
+ pci_write_config16(dev, 0x56, 0xab95);
+ }
+ }
+#endif
+
+#if ASSIGN_IRQ
+ printk_info("setting Onboard AMD Southbridge \n");
+ static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
+ pci_assign_irqs(1, 4, slotIrqs_1_4);
+#endif
//On Board AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
+#if ASSIGN_IRQ
+ printk_info("setting Onboard AMD USB \n");
+ static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
+ pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
+#endif
+
//On Board ATI Display Adapter
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x2, 0x12);
+#if ASSIGN_IRQ
+ printk_info("setting Onboard ATI Display Adapter\n");
+ static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
+ pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
+#endif
+
#if 1
//Slot 5 PCI 32
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, 0x2, 0x12); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, 0x2, 0x13); //
+
+#if ASSIGN_IRQ
+ printk_info("setting Slot 5 \n");
+ static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
+ pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
+#endif
+
#endif
//Onboard SI Serial ATA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x2, 0x13);
+
+#if ASSIGN_IRQ
+ printk_info("setting Onboard SI Serail ATA\n");
+ static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
+ pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
+#endif
+
//Onboard Intel 82551 10/100M NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, 0x2, 0x12);
+#if ASSIGN_IRQ
+ printk_info("setting Onboard Intel NIC\n");
+ static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
+ pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
+#endif
+
#if 1
//Slot 3 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, 0x3, 0x1);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, 0x3, 0x2);//
+#if ASSIGN_IRQ
+ printk_info("setting Slot 3\n");
+ static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
+ pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
+#endif
+
//Slot 4 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, 0x3, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, 0x3, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, 0x3, 0x0);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, 0x3, 0x1);//
+
+#if ASSIGN_IRQ
+ printk_info("setting Slot 4\n");
+ static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
+ pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
+#endif
+
#endif
//Onboard adaptec scsi
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, 0x3, 0x1);
+
+#if ASSIGN_IRQ
+ printk_info("setting Onboard Adaptec SCSI\n");
+ static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
+ pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
+#endif
+
//On Board NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x3, 0x1);
+
+
+#if ASSIGN_IRQ
+ printk_info("setting Onboard Broadcom NIC\n");
+ static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
+ pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
+#endif
+
#if 1
//Slot 1 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
+#if ASSIGN_IRQ
+ printk_info("setting Slot 1\n");
+ static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
+ pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
+#endif
+
//Slot 2 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, 0x4, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, 0x4, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, 0x4, 0x3);//
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, 0x4, 0x0);//
+#if ASSIGN_IRQ
+ printk_info("setting Slot 2\n");
+ static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
+ pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
+#endif
+
#endif
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-
##
-## Build code to reset the motherboard from linuxBIOS
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
-default HAVE_HARD_RESET=1
-default HARD_RESET_BUS=3
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-###
-### Build code to export a programmable irq routing table
-###
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
##
-default HAVE_MP_TABLE=1
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Build code to export a CMOS option table
+## Compute where this copy of linuxBIOS will start in the boot rom
##
-default HAVE_OPTION_TABLE=1
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-#
-###
-### Build code to setup a generic IOAPIC
-###
-default CONFIG_IOAPIC=1
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-###
-### Clean up the motherboard id strings
-###
-default MAINBOARD_PART_NUMBER="S2885"
-default MAINBOARD_VENDOR="Tyan"
+arch i386 end
-###
-### Set all of the defaults for an x86 architecture
-###
-
-arch i386 end
+##
+## Build the objects we have code for in this directory.
+##
-###
-### Build the objects we have code for in this directory.
-###
driver mainboard.o
-#dir /drvers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#driver ti_firewire.o
-#dir /drivers/vga
-
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
+makerule ./failover.inc
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+end
+makerule ./auto.inc
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
-#### Should this be in the northbridge code?
+### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
+
+##
+## Include an id string (For safe flashing)
+##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
+
###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
###
-#
if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
-#
-#
###
-### Setup the serial port
+### O.k. We aren't just an intermediary anymore!
###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-###
-### Romcc output
-###
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c"
- action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
-end
-makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
-end
-
-makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
-end
-
-mainboardinit cpu/k8/enable_mmx_sse.inc
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
-#
-###
-### Include the secondary Configuration files
-###
+##
+## Include the secondary Configuration files
+##
dir /pc80
config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 2
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
+# sample config for tyan/s2885
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on # LDT0
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
+ end
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
end
- southbridge amd/amd8111 "amd8111" link 2
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 on
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
- southbridge amd/amd8151 "amd8151" link 0
- pci 0:0.0
- pci 0:1.0
- end
-end
-
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
-
-cpu k8 "cpu0"
- register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
- register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
-
-cpu k8 "cpu1"
end
#define ASSEMBLY 1
+
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
- set_bios_reset();
+ set_bios_reset();
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
+ /* enable cf9 */
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ /* reset */
+ outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- } else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
+ if (is_cpu_pre_c0()) {
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ }
+ else {
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ }
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
- if (is_cpu_pre_c0()) {
- udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
- udelay(90);
- }
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ udelay(90);
+ }
}
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
* [3] Route to Link 2
*/
- uint32_t ret = 0x00010101; /* default row entry */
-
- /* CPU0 LDT1 <-> LDT1 CPU1 */
+ uint32_t ret=0x00010101; /* default row entry */
+/*
+ (L1) (L1) (L2)
+ CPU1-------------CPU0--------8131------8111
+ |(L0)
+ |
+ |
+ |
+ |
+ |
+ 8151
+*/
+ /* Link1 of CPU0 to Link1 of CPU1 */
static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 }
};
- if (maxnodes > 2) {
+ if(maxnodes>2) {
print_debug("this mainboard is only designed for 2 cpus\r\n");
- maxnodes = 2;
+ maxnodes=2;
}
- if (!(node >= maxnodes || row >= maxnodes)) {
- ret = rows_2p[node][row];
+
+ if (!(node>=maxnodes || row>=maxnodes)) {
+ ret=rows_2p[node][row];
}
return ret;
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
#if 1
static const struct ht_chain ht_c[] = {
- {
+ { /* Link 2 of CPU0 */
.udev = PCI_DEV(0, 0x18, 0),
.upos = 0xc0,
- .devreg = 0xe0,
+ .devreg = 0xe0, /* Preset bus num in resource map */
},
- {
+ { /* Link 0 of CPU0 */
.udev = PCI_DEV(0, 0x18, 0),
.upos = 0x80,
- .devreg = 0xe4,
+ .devreg = 0xe4, /* Preset bus num in resource map */
},
};
#endif
int needs_reset;
- enable_lapic();
- init_timer();
-
- if (cpu_init_detected()) {
- asm volatile ("jmp __cpu_reset");
- }
-
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
-
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
+ /* Halt if there was a built in self test failure */
+// report_bist_failure(bist);
+
setup_s2885_resource_map();
needs_reset = setup_coherent_ht_domain();
+#if 0
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
+#else
needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
+#endif
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
-#if 0
- print_pci_devices();
-#endif
-
enable_smbus();
-
#if 0
dump_spd_registers(&cpu[0]);
#endif
-
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
+#endif
+#if 0
dump_pci_device(PCI_DEV(0, 0x18, 1));
#endif
+ /* Check all of memory */
+#if 0
+ msr_t msr;
+ msr = rdmsr(TOP_MEM2);
+ print_debug("TOP_MEM2: ");
+ print_debug_hex32(msr.hi);
+ print_debug_hex32(msr.lo);
+ print_debug("\r\n");
+
+ ram_check(0x00000000, msr.lo+(msr.hi<<32));
+
+#endif
+
+#if 0
+
+//#if TOTAL_CPUS < 2
+ // Check 16MB of memory @ 0
+ ram_check(0x00000000, 0x00100000);
+//#else
+ // Check 16MB of memory @ 2GB
+// ram_check(0x80000000, 0x80100000);
+//#endif
+#endif
+
+
}
-extern struct chip_control mainboard_tyan_s2885_control;
+extern struct chip_operations mainboard_tyan_s2885_ops;
struct mainboard_tyan_s2885_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
}
normal_image:
asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
cpu_reset:
+#if 0
asm volatile ("jmp __cpu_reset"
- : /* outputs */
- : "a"(bist) /* inputs */
- : /* clobbers */
- );
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
+#if 0
+static void fixup_lsi_53c1030(struct device *pdev)
{
- 0, 1
-};
+// uint8_t byte;
+ uint16_t word;
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
-};
+ byte = 1;
+ pci_write_config8(pdev, 0xff, byte);
+ // Set the device id
+// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
+ // Set the subsytem vendor id
+// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);
+ word = 0x10f1;
+ pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
+ // Set the subsytem id
+ word = 0x2880;
+ pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
+ // Disable writes to the device id
+ byte = 0;
+ pci_write_config8(pdev, 0xff, byte);
+
+// lsi_scsi_init(pdev);
+
+}
+#endif
+
+#if 0
+static void print_pci_regs(struct device *dev)
+{
+ uint8_t byte;
+ int i;
+
+ for(i=0;i<256;i++) {
+ byte = pci_read_config8(dev, i);
+
+ if((i%16)==0) printk_debug("\n%02x:",i);
+ printk_debug(" %02x",byte);
+ }
+ printk_debug("\n");
+
+// pci_write_config8(dev, 0x4, byte);
-static void enumerate(struct chip *chip)
+}
+#endif
+#if 0
+static void print_mem(void)
{
- struct chip *child;
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
+ if((i%16)==0) printk_debug("\n %08x:",i);
+ printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
+ }
+#if 0
+ for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ if((i%16)==0) printk_debug("\n %08x:",i);
+ printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
+ }
+#endif
+ }
+#endif
+#if 0
+static void amd8111_enable_rom(void)
+{
+ uint8_t byte;
+ struct device *dev;
+
+ /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
+ /* Locate the amd8111 */
+ dev = dev_find_device(0x1022, 0x7468, 0);
- if (chip->control && chip->control->name) {
- printk_debug("Enumerating: %s\n", chip->control->name);
+ /* Set the 4MB enable bit bit */
+ byte = pci_read_config8(dev, 0x43);
+ byte |= 0x80;
+ pci_write_config8(dev, 0x43, byte);
+}
+#endif
+#if 0
+static void onboard_scsi_fixup(void)
+{
+ struct device *dev;
+#if 1
+ unsigned char i,j,k;
+
+ for(i=0;i<=15;i++) {
+ for(j=0;j<=0x1f;j++) {
+ for (k=0;k<=6;k++){
+ dev = dev_find_slot(i, PCI_DEVFN(j, k));
+ if (dev) {
+ printk_debug("%02x:%02x:%02x",i,j,k);
+ print_pci_regs(dev);
+ }
+ }
+ }
}
+#endif
+
- /* update device operation for dynamic root */
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for (child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
+#if 0
+ dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
+ if(!dev) {
+ printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
+ return;
}
+
+ lsi_scsi_init(dev);
+#endif
+// print_mem();
+// amd8111_enable_rom();
+}
+#endif
+#if 0
+static void vga_fixup(void) {
+ // we do this right here because:
+ // - all the hardware is working, and some VGA bioses seem to need
+ // that
+ // - we need page 0 below for linuxbios tables.
+#if CONFIG_REALMODE_IDT == 1
+ printk_debug("INSTALL REAL-MODE IDT\n");
+ setup_realmode_idt();
+#endif
+#if CONFIG_VGABIOS == 1
+ printk_debug("DO THE VGA BIOS\n");
+ do_vgabios(0x0600);
+ post_code(0x93);
+#endif
+
}
-struct chip_control mainboard_tyan_s2885_control = {
- .enumerate = enumerate,
- .name = "Tyan s2885 mainboard ",
+#endif
+
+#if 0
+static void
+enable(struct chip *chip, enum chip_pass pass)
+{
+
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
+
+ switch (pass) {
+ default: break;
+// case CONF_PASS_PRE_CONSOLE:
+// case CONF_PASS_PRE_PCI:
+// case CONF_PASS_POST_PCI:
+ case CONF_PASS_PRE_BOOT:
+// if (conf->fixup_scsi)
+// onboard_scsi_fixup();
+// if (conf->fixup_vga)
+// vga_fixup();
+ printk_debug("mainboard fixup pass %d done\r\n",
+ pass);
+ break;
+ }
+
+}
+#endif
+
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
+{
+ unsigned bus;
+ unsigned devfn;
+#if 0
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
+#if 0
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
+#endif
+}
+
+static void debug_noop(device_t dummy)
+{
+}
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
+};
+
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s2885_ops = {
+ .name = "Tyan s2885 mainboard ",
+ .enable_dev = enable_dev,
};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
device_t dev;
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
- uint32_t base;
+ device_t dev;
+ struct resource *res;
dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 3, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
}
dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 4, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
}
}
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06010207,
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000007,
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link2 of CPU 0
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070003, // AMD 8151 on link0 of CPU 0
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};
word |= ((1 << 2) |(1<<4)); // Command: 3--> 17
pci_write_config16(dev, 0x4, word);
- printk_debug("TI_FIREWIRE_FIXUP: done \n");
-
}
static struct device_operations ti_firewire_ops = {
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1"
-#register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
driver mainboard.o
-#dir /drivers/lsi/53c1030
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### Romcc output
-###
+#object reset.o
+##
+## Romcc output
+##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
-end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Include the secondary Configuration files
-###
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 2
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
- end
- southbridge amd/amd8111 "amd8111" link 2
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
-northbridge amd/amdk8 "mc2"
- pci 0:1a.0
- pci 0:1a.0
- pci 0:1a.0
- pci 0:1a.1
- pci 0:1a.2
- pci 0:1a.3
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
-northbridge amd/amdk8 "mc3"
- pci 0:1b.0
- pci 0:1b.0
- pci 0:1b.0
- pci 0:1b.1
- pci 0:1b.2
- pci 0:1b.3
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
+###
+### O.k. We aren't just an intermediary anymore!
+###
-dir /pc80
-#dir /bioscall
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
-cpu k8 "cpu0"
- register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
-cpu k8 "cpu1"
-end
+# sample config for tyan/s4880
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+
+ chip northbridge/amd/amdk8
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.1 on end
+ device pci 1a.2 on end
+ device pci 1a.3 on end
+ end
-cpu k8 "cpu2"
+ chip northbridge/amd/amdk8
+ device pci 1b.0 on end
+ device pci 1b.0 on end
+ device pci 1b.0 on end
+ device pci 1b.1 on end
+ device pci 1b.2 on end
+ device pci 1b.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 2 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 3 on end
+ end
+ end
end
-cpu k8 "cpu3"
-end
#define ASSEMBLY 1
+
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
set_bios_reset();
/* enable cf9 */
- pci_write_config8(PCI_DEV(1, 0x04, 3), 0x41, 0xf1);
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
- pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
+}
static void memreset_setup(void)
{
*/
uint32_t ret=0x00010101; /* default row entry */
+/*
+ (L1) (L2)
+ CPU3-------------CPU1
+ (L0)| |(L0)
+ | |
+ | |
+ | |
+ | |
+ (L0)| |(L0)
+ CPU2-------------CPU0---------8131----------8111
+ (L2) (L1) (L2)
+*/
+
+ /* Link0 of CPU0 to Link0 of CPU1 */
+ /* Link1 of CPU0 to Link2 of CPU2 */
+ /* Link2 of CPU1 to Link1 of CPU3 */
+ /* Link0 of CPU2 to Link0 of CPU3 */
static const unsigned int rows_4p[4][4] = {
{ 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#define DIMM2 0x52
#define DIMM3 0x53
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
};
int i;
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
+
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+// report_bist_failure(bist);
+
setup_s4880_resource_map();
needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
-extern struct chip_control mainboard_tyan_s4880_control;
+extern struct chip_operations mainboard_tyan_s4880_ops;
struct mainboard_tyan_s4880_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0,1,2,3
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
word = 0x10f1;
pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
// Set the subsytem id
- word = 0x4880;
+ word = 0x2880;
pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
// Disable writes to the device id
byte = 0;
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
-#if 1
+
+#if 0
static void print_pci_regs(struct device *dev)
{
uint8_t byte;
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
pci_write_config8(dev, 0x43, byte);
}
#endif
-#if 1
+#if 0
static void onboard_scsi_fixup(void)
{
struct device *dev;
#if 1
unsigned char i,j,k;
- for(i=0;i<=6;i++) {
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
#endif
#if CONFIG_VGABIOS == 1
printk_debug("DO THE VGA BIOS\n");
- do_vgabios();
+ do_vgabios(0x0600);
post_code(0x93);
#endif
}
-#endif
+#endif
+
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s4880_config *conf =
- (struct mainboard_tyan_s4880_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
// case CONF_PASS_PRE_PCI:
// case CONF_PASS_POST_PCI:
case CONF_PASS_PRE_BOOT:
- if (conf->fixup_scsi)
- onboard_scsi_fixup();
+// if (conf->fixup_scsi)
+// onboard_scsi_fixup();
// if (conf->fixup_vga)
// vga_fixup();
printk_debug("mainboard fixup pass %d done\r\n",
}
}
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
-};
+#endif
-static void enumerate(struct chip *chip)
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
+ unsigned bus;
+ unsigned devfn;
+#if 0
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
}
+#endif
+#if 0
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
+ }
+#endif
+}
+
+static void debug_noop(device_t dummy)
+{
}
-struct chip_control mainboard_tyan_s4880_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s4880 mainboard ",
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
};
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s4880_ops = {
+ .name = "Tyan s4880 mainboard ",
+ .enable_dev = enable_dev,
+};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 4, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
- uint32_t base;
+ device_t dev;
+ struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 5, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x05, 0x11, res->base);
+ }
}
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 6, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x06, 0x11, res->base);
+ }
}
+
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1"
-#register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
driver mainboard.o
-#dir /drivers/lsi/53c1030
-#dir /drivers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551
-#dir /drivers/ati/ragexl
-#object reset.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#cpu k8 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/i386/reset16.inc
- ldscript /cpu/i386/reset16.lds
-else
- mainboardinit cpu/i386/reset32.inc
- ldscript /cpu/i386/reset32.lds
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
-end
-#
-###
-### Setup our mtrrs
-###
-mainboardinit cpu/k8/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to
-###
-#
-if USE_FALLBACK_IMAGE
- mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### Romcc output
-###
-#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
-#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
-#mainboardinit .failover.inc
+#object reset.o
+##
+## Romcc output
+##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
- depends "./romcc ./failover.E"
- action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+ depends "./failover.E ./romcc"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
+end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h"
- action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ depends "$(MAINBOARD)/auto.c option_table.h "
+ action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
- depends "./romcc ./auto.E"
- action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
-end
-mainboardinit cpu/k8/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/k8/disable_mmx_sse.inc
-#
-###
-### Include the secondary Configuration files
-###
-northbridge amd/amdk8 "mc0"
- pci 0:18.0
- pci 0:18.0
- pci 0:18.0
- pci 0:18.1
- pci 0:18.2
- pci 0:18.3
- southbridge amd/amd8131 "amd8131" link 1
- pci 0:0.0
- pci 0:0.1
- pci 0:1.0
- pci 0:1.1
- end
- southbridge amd/amd8111 "amd8111" link 1
- pci 0:0.0
- pci 0:1.0 on
- pci 0:1.1 on
- pci 0:1.2 on
- pci 0:1.3 on
- pci 0:1.5 off
- pci 0:1.6 off
- pci 1:0.0 on
- pci 1:0.1 on
- pci 1:0.2 off
- pci 1:1.0 off
- superio winbond/w83627hf link 1
- pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- pnp 2e.6 off # CIR
- pnp 2e.7 off # GAME_MIDI_GIPO1
- pnp 2e.8 off # GPIO2
- pnp 2e.9 off # GPIO3
- pnp 2e.a off # ACPI
- pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- end
+ depends "./auto.E ./romcc"
+ action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
end
-northbridge amd/amdk8 "mc1"
- pci 0:19.0
- pci 0:19.0
- pci 0:19.0
- pci 0:19.1
- pci 0:19.2
- pci 0:19.3
-end
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
-northbridge amd/amdk8 "mc2"
- pci 0:1a.0
- pci 0:1a.0
- pci 0:1a.0
- pci 0:1a.1
- pci 0:1a.2
- pci 0:1a.3
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
-northbridge amd/amdk8 "mc3"
- pci 0:1b.0
- pci 0:1b.0
- pci 0:1b.0
- pci 0:1b.1
- pci 0:1b.2
- pci 0:1b.3
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
end
+###
+### O.k. We aren't just an intermediary anymore!
+###
-dir /pc80
-#dir /bioscall
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
-cpu k8 "cpu0"
- register "ldt1" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
-end
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
-cpu k8 "cpu1"
-end
+# sample config for tyan/s4882
+chip northbridge/amd/amdk8
+ device pci_domain 0 on
+ device pci 18.0 on end # LDT0
+ device pci 18.0 on # northbridge
+ # devices on link 1, link 1 == LDT 1
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # device pci 18.0
+
+ device pci 18.0 on end
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+
+ chip northbridge/amd/amdk8
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.0 on end
+ device pci 1a.1 on end
+ device pci 1a.2 on end
+ device pci 1a.3 on end
+ end
-cpu k8 "cpu2"
+ chip northbridge/amd/amdk8
+ device pci 1b.0 on end
+ device pci 1b.0 on end
+ device pci 1b.0 on end
+ device pci 1b.1 on end
+ device pci 1b.2 on end
+ device pci 1b.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 2 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 3 on end
+ end
+ end
end
-cpu k8 "cpu3"
-end
#define ASSEMBLY 1
+
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
+static void soft2_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
+}
static void memreset_setup(void)
{
*/
uint32_t ret=0x00010101; /* default row entry */
+/*
+ (L2) (L1)
+ CPU3-------------CPU1
+ (L0)| |(L0)
+ | |
+ | |
+ | |
+ | |
+ (L0)| |(L0)
+ CPU2-------------CPU0---------8131----------8111
+ (L1) (L2) (L1)
+*/
+
+ /* Link0 of CPU0 to Link0 of CPU1 */
+ /* Link2 of CPU0 to Link1 of CPU2 */
+ /* Link1 of CPU1 to Link2 of CPU3 */
+ /* Link0 of CPU2 to Link0 of CPU3 */
static const unsigned int rows_4p[4][4] = {
{ 0x000b0101, 0x00010202, 0x00030808, 0x00010208 },
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#define DIMM2 0x52
#define DIMM3 0x53
-static void main(void)
+static void main(unsigned long bist)
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
};
int i;
int needs_reset;
- enable_lapic();
- init_timer();
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- distinguish_cpu_resets();
- if (!boot_cpu()) {
- stop_this_cpu();
- }
+ if (bist == 0) {
+ /* Skip this if there was a built in self test failure */
+ amd_early_mtrr_init();
+ enable_lapic();
+ init_timer();
+
+ if (cpu_init_detected()) {
+#if 0
+ asm volatile ("jmp __cpu_reset");
+#else
+ /* cpu reset also reset the memtroller ????
+ need soft_reset to reset all except keep HT link freq and width */
+ distinguish_cpu_resets();
+ soft2_reset();
+#endif
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ }
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
setup_s4882_resource_map();
needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0);
-extern struct chip_control mainboard_tyan_s4882_control;
+extern struct chip_operations mainboard_tyan_s4882_ops;
struct mainboard_tyan_s4882_config {
int fixup_scsi;
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
+445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
-#else
-static void main(void)
-{
- unsigned long bist = 0;
-#endif
/* Make cerain my local apic is useable */
enable_lapic();
goto fallback_image;
}
normal_image:
- asm("jmp __normal_image"
+ asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
- asm("jmp __cpu_reset"
+#if 0
+ asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
+#endif
fallback_image:
-#if HAVE_REGPARM_SUPPORT
return bist;
-#else
- return;
-#endif
}
#include <device/pci_ops.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
-//#include <part/mainboard.h>
-//#include "lsi_scsi.c"
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
- 0,1,2,3
-};
+
#if 0
static void fixup_lsi_53c1030(struct device *pdev)
{
word = 0x10f1;
pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
// Set the subsytem id
- word = 0x4882;
+ word = 0x2880;
pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
// Disable writes to the device id
byte = 0;
}
#endif
-//extern static void lsi_scsi_init(struct device *dev);
+
#if 0
static void print_pci_regs(struct device *dev)
{
#if 0
static void print_mem(void)
{
- int i;
- int low_1MB = 0;
- for(i=low_1MB;i<low_1MB+1024*4;i++) {
+ unsigned int i;
+ unsigned int low_1MB = 0xf4107000;
+ for(i=low_1MB;i<low_1MB+1024;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
}
-
+#if 0
for(i=low_1MB;i<low_1MB+1024*4;i++) {
if((i%16)==0) printk_debug("\n %08x:",i);
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
}
+#endif
}
#endif
#if 0
static void onboard_scsi_fixup(void)
{
struct device *dev;
-#if 0
+#if 1
unsigned char i,j,k;
- for(i=0;i<=6;i++) {
+ for(i=0;i<=15;i++) {
for(j=0;j<=0x1f;j++) {
for (k=0;k<=6;k++){
dev = dev_find_slot(i, PCI_DEVFN(j, k));
#endif
#if CONFIG_VGABIOS == 1
printk_debug("DO THE VGA BIOS\n");
- do_vgabios();
+ do_vgabios(0x0600);
post_code(0x93);
#endif
}
-#endif
+#endif
+
+#if 0
static void
enable(struct chip *chip, enum chip_pass pass)
{
- struct mainboard_tyan_s4882_config *conf =
- (struct mainboard_tyan_s4882_config *)chip->chip_info;
+ struct mainboard_tyan_s2895_config *conf =
+ (struct mainboard_tyan_s2895_config *)chip->chip_info;
switch (pass) {
default: break;
}
}
-static struct device_operations mainboard_operations = {
- .read_resources = root_dev_read_resources,
- .set_resources = root_dev_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_scan_root_bus,
- .enable = 0,
-};
+#endif
-static void enumerate(struct chip *chip)
+#undef DEBUG
+#define DEBUG 0
+#if DEBUG
+static void debug_init(device_t dev)
{
- struct chip *child;
- dev_root.ops = &mainboard_operations;
- chip->dev = &dev_root;
- chip->bus = 0;
- for(child = chip->children; child; child = child->next) {
- child->bus = &dev_root.link[0];
+ unsigned bus;
+ unsigned devfn;
+#if 0
+ for(bus = 0; bus < 256; bus++) {
+ for(devfn = 0; devfn < 256; devfn++) {
+ int i;
+ dev = dev_find_slot(bus, devfn);
+ if (!dev) {
+ continue;
+ }
+ if (!dev->enabled) {
+ continue;
+ }
+ printk_info("%02x:%02x.%0x aka %s\n",
+ bus, devfn >> 3, devfn & 7, dev_path(dev));
+ for(i = 0; i < 256; i++) {
+ if ((i & 0x0f) == 0) {
+ printk_info("%02x:", i);
+ }
+ printk_info(" %02x", pci_read_config8(dev, i));
+ if ((i & 0x0f) == 0xf) {
+ printk_info("\n");
+ }
+ }
+ printk_info("\n");
+ }
+ }
+#endif
+#if 0
+ msr_t msr;
+ unsigned index;
+ unsigned eax, ebx, ecx, edx;
+ index = 0x80000007;
+ printk_debug("calling cpuid 0x%08x\n", index);
+ asm volatile(
+ "cpuid"
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+ : "a" (index)
+ );
+ printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
+ index, eax, ebx, ecx, edx);
+ if (edx & (3 << 1)) {
+ index = 0xC0010042;
+ printk_debug("Reading msr: 0x%08x\n", index);
+ msr = rdmsr(index);
+ printk_debug("msr[0x%08x]: 0x%08x%08x\n",
+ index, msr.hi, msr.hi);
}
+#endif
}
-struct chip_control mainboard_tyan_s4882_control = {
- .enable = enable,
- .enumerate = enumerate,
- .name = "Tyan s4882 mainboard ",
+
+static void debug_noop(device_t dummy)
+{
+}
+
+static struct device_operations debug_operations = {
+ .read_resources = debug_noop,
+ .set_resources = debug_noop,
+ .enable_resources = debug_noop,
+ .init = debug_init,
};
+static unsigned int scan_root_bus(device_t root, unsigned int max)
+{
+ struct device_path path;
+ device_t debug;
+ max = root_dev_scan_bus(root, max);
+ path.type = DEVICE_PATH_PNP;
+ path.u.pnp.port = 0;
+ path.u.pnp.device = 0;
+ debug = alloc_dev(&root->link[1], &path);
+ debug->ops = &debug_operations;
+ return max;
+}
+#endif
+static void mainboard_init(device_t dev)
+{
+ root_dev_init(dev);
+
+// do_verify_cpu_voltages();
+}
+
+static struct device_operations mainboard_operations = {
+ .read_resources = root_dev_read_resources,
+ .set_resources = root_dev_set_resources,
+ .enable_resources = root_dev_enable_resources,
+ .init = mainboard_init,
+#if !DEBUG
+ .scan_bus = root_dev_scan_bus,
+#else
+ .scan_bus = scan_root_bus,
+#endif
+ .enable = 0,
+};
+
+static void enable_dev(struct device *dev)
+{
+ dev_root.ops = &mainboard_operations;
+}
+struct chip_operations mainboard_tyan_s4882_ops = {
+ .name = "Tyan s4882 mainboard ",
+ .enable_dev = enable_dev,
+};
#include <string.h>
#include <stdint.h>
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN ";
mc->mpe_checksum = 0;
mc->reserved = 0;
- smp_write_processors(mc, processor_map);
+ smp_write_processors(mc);
{
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 4, 0x11, 0xfec00000);
{
- struct pci_dev *dev;
- uint32_t base;
+ device_t dev;
+ struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 5, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x05, 0x11, res->base);
+ }
}
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
if (dev) {
- base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- base &= PCI_BASE_ADDRESS_MEM_MASK;
- smp_write_ioapic(mc, 6, 0x11, base);
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x06, 0x11, res->base);
+ }
}
+
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
return smp_next_mpe_entry(mc);
}
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v, processor_map);
+ return (unsigned long)smp_write_config_table(v);
}
(id == 0x0000ffff) || (id == 0xffff0000)) {
continue;
}
+
pos = ht_lookup_slave_capability(dev);
if (!pos) {
continue;
}
-
+
/* Clear the unitid */
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
(((id >> 16) & 0xffff) == 0x0000)) {
break;
}
+
pos = ht_lookup_slave_capability(dev);
if (!pos) {
print_err("HT link capability not found\r\n");
break;
}
+
/* Setup the Hypertransport link */
reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
unsigned upos;
unsigned devreg;
};
-
-static int ht_setup_chainx(device_t udev, unsigned upos, unsigned next_unitid)
+static int ht_setup_chainx(device_t udev, unsigned upos, unsigned bus)
{
- unsigned last_unitid;
+ unsigned next_unitid, last_unitid;
unsigned uoffs;
int reset_needed=0;
uoffs = PCI_HT_HOST_OFFS;
+ next_unitid = 1;
+
do {
uint32_t id;
uint8_t pos;
unsigned flags, count;
- device_t dev = PCI_DEV(0, 0, 0);
+
+ device_t dev = PCI_DEV(bus, 0, 0);
last_unitid = next_unitid;
id = pci_read_config32(dev, PCI_VENDOR_ID);
(((id >> 16) & 0xffff) == 0x0000)) {
break;
}
+#if 0
+ print_debug("bus=");
+ print_debug_hex8(bus);
+ print_debug(" id =");
+ print_debug_hex32(id);
+ print_debug("\r\n");
+#endif
+
+
pos = ht_lookup_slave_capability(dev);
if (!pos) {
print_err("HT link capability not found\r\n");
break;
}
+
/* Setup the Hypertransport link */
reset_needed |= ht_optimize_link(udev, upos, uoffs, dev, pos, PCI_HT_SLAVE0_OFFS);
next_unitid += count;
} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
- if(reset_needed!=0) next_unitid |= 0xffff0000;
- return next_unitid;
+ return reset_needed;
}
static int ht_setup_chains(const struct ht_chain *ht_c, int ht_c_num)
* non Coherent links the appropriate bus registers for the
* links needs to be programed to point at bus 0.
*/
- unsigned next_unitid;
int reset_needed;
- unsigned upos;
- device_t udev;
+ unsigned upos;
+ device_t udev;
int i;
- /* Make certain the HT bus is not enumerated */
- ht_collapse_previous_enumeration(0);
-
reset_needed = 0;
- next_unitid = 1;
for (i = 0; i < ht_c_num; i++) {
uint32_t reg;
- uint8_t reg8;
+ unsigned devpos;
+ unsigned regpos;
+ uint32_t dword;
+ unsigned busn;
+
reg = pci_read_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg);
- reg |= (0xff<<24) | 7;
- reg &= ~(0xff<<16);
- pci_write_config32(PCI_DEV(0,0x18,1), ht_c[i].devreg, reg);
-#if CONFIG_MAX_CPUS > 1
- pci_write_config32(PCI_DEV(0,0x19,1), ht_c[i].devreg, reg);
-#endif
-#if CONFIG_MAX_CPUS > 2
- pci_write_config32(PCI_DEV(0,0x1a,1), ht_c[i].devreg, reg);
- pci_write_config32(PCI_DEV(0,0x1b,1), ht_c[i].devreg, reg);
+ //We need setup 0x94, 0xb4, and 0xd4 according to the reg
+ devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
+ regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
+ busn = (reg & 0xff0000)>>16;
+
+ dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
+ dword &= ~(0xffff<<8);
+ dword |= (reg & 0xffff0000)>>8;
+ pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
+#if 0
+ print_debug("PCI_DEV=(0,0x");
+ print_debug_hex8(devpos);
+ print_debug(",0) 0x");
+ print_debug_hex8(regpos);
+ print_debug("=");
+ print_debug_hex32(dword);
+ print_debug("\r\n");
#endif
+
+ /* Make certain the HT bus is not enumerated */
+ ht_collapse_previous_enumeration(busn);
- //Store dev min
- reg8 = next_unitid & 0xff ;
- upos = ht_c[i].upos;
- udev = ht_c[i].udev;
-
- next_unitid = ht_setup_chainx(udev,upos,next_unitid);
- if((next_unitid & 0xffff0000) == 0xffff0000) {
- reset_needed |= 1;
- next_unitid &=0x0000ffff;
- }
-
- //set dev min
- pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+2, reg8);
-#if CONFIG_MAX_CPUS > 1
- pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+2, reg8);
-#endif
-#if CONFIG_MAX_CPUS > 2
- pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+2, reg8);
- pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+2, reg8);
-#endif
+ upos = ht_c[i].upos;
+ udev = ht_c[i].udev;
+
+ reset_needed |= ht_setup_chainx(udev,upos,busn );
- //Set dev max
- reg8 = (next_unitid-1) & 0xff ;
- pci_write_config8(PCI_DEV(0,0x18,1), ht_c[i].devreg+3, reg8);
-#if CONFIG_MAX_CPUS > 1
- pci_write_config8(PCI_DEV(0,0x19,1), ht_c[i].devreg+3, reg8);
-#endif
-#if CONFIG_MAX_CPUS > 2
- pci_write_config8(PCI_DEV(0,0x1a,1), ht_c[i].devreg+3, reg8);
- pci_write_config8(PCI_DEV(0,0x1b,1), ht_c[i].devreg+3, reg8);
-#endif
}
return reset_needed;
#define SIO_COM2_BASE 0x2F8
#endif
-extern struct chip_control superio_winbond_w83627hf_control;
+extern struct chip_operations superio_winbond_w83627hf_ops;
#include <pc80/keyboard.h>
#include <uart8250.h>
if (!dev->enabled) {
return;
}
- conf = dev->chip->chip_info;
+ conf = dev->chip_info;
switch(dev->path.u.pnp.device) {
case W83627HF_SP1:
- res0 = get_resource(dev, PNP_IDX_IO0);
+ res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case W83627HF_SP2:
- res0 = get_resource(dev, PNP_IDX_IO0);
+ res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case W83627HF_KBC:
- res0 = get_resource(dev, PNP_IDX_IO0);
- res1 = get_resource(dev, PNP_IDX_IO1);
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
case W83627HF_HWM:
- res0 = get_resource(dev, PNP_IDX_IO0);
+ res0 = find_resource(dev, PNP_IDX_IO0);
init_hwm(res0->base);
break;
}
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
};
-static void enumerate(struct chip *chip)
+static void enable_dev(struct device *dev)
{
- pnp_enumerate(chip, sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]),
- &pnp_ops, pnp_dev_info);
+ pnp_enable_devices(dev, &pnp_ops,
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
}
-struct chip_control superio_winbond_w83627hf_control = {
- .enumerate = enumerate,
- .name = "Winbond w83627hf"
+struct chip_operations superio_winbond_w83627hf_ops = {
+ .name = "Winbond w83627hf",
+ .enable_dev = enable_dev,
};
# the Tyan s2850
# This will make a target directory of ./s2850
-loadoptions
-
target s2850
+mainboard tyan/s2850
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_HARD_RESET=1
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=0
-#option CONFIG_REALMODE_IDT=0
-#option CONFIG_PCIBIOS=0
-#option VGABIOS_START=0xfff8c000
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=1
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=1
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S2850"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=8
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 128K stack
-##
-option STACK_SIZE=0x4000
-
-##
-## Use a 256K heap
-##
-option HEAP_SIZE=0x8000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s2895
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
- option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2850
-# payload ../../../payloads/eepro100--ide_disk.zelf
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/eepro100--filo_btext.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
- option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2850
-# payload ../../../payloads/eepro100--ide_disk.zelf
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/eepro100--filo_btext.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
# the Tyan s2875
# This will make a target directory of ./s2875
-loadoptions
-
target s2875
+mainboard tyan/s2875
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-#uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-#option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=1
-#option CONFIG_REALMODE_IDT=1
-#option CONFIG_PCIBIOS=1
-#option VGABIOS_START=1
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-option HAVE_HARD_RESET=1
-
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=13
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S2875"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=8
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s2895
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
- option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2875
-# payload ../../../payloads/e1000--ide_disk.zelf
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2875
-# payload ../../../payloads/e1000--ide_disk.zelf
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
# the Tyan s2880
# This will make a target directory of ./s2880
-loadoptions
-
target s2880
+mainboard tyan/s2880
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-
-option HAVE_HARD_RESET=1
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=0
-#option CONFIG_REALMODE_IDT=0
-#option CONFIG_PCIBIOS=0
-#option VGABIOS_START=0xfff8c000
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S2880"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s2895
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
-# option ROM_SIZE = (512*1024 - 48*1024)
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
-
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2880
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/tg3--filo_btext.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2880
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/tg3--filo_btext.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
cd "$TYANMB"
make
#cat ../fwx.rom ../atix.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
-#cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
+#cat ../fwx.rom ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
+cat ./normal/linuxbios.rom ./fallback/linuxbios.rom > $TYANMB"_linuxbios.rom"
cp -f $TYANMB"_linuxbios.rom" /home/yhlu/
# Sample config file for
-# the Tyan s2880
-# This will make a target directory of ./s2880
-
-loadoptions
+# the Tyan s2881
+# This will make a target directory of ./s2881
target s2881
+mainboard tyan/s2881
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_HARD_RESET=1
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=0
-#option CONFIG_REALMODE_IDT=0
-#option CONFIG_PCIBIOS=0
-#option VGABIOS_START=0xfff8c000
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=9
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S2881"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s2881
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
-# 64K for Etherboot
-# option ROM_SIZE = 458752
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2881
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/tg3--filo_btext.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2881
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/tg3--filo_btext.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
# Sample config file for
-# the Tyan s2880
-# This will make a target directory of ./s2880
-
-loadoptions
+# the Tyan s2882
+# This will make a target directory of ./s2882
target s2882
+mainboard tyan/s2882
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-#SMDC Support
-#uses CONFIG_CONSOLE_SERIAL8250_2
-#uses TTYS1_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-uses CONFIG_FS_STREAM
-uses CONFIG_IDE
-
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-option HAVE_HARD_RESET=1
-
-option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=1
-#option CONFIG_REALMODE_IDT=1
-#option CONFIG_PCIBIOS=1
-#option VGABIOS_START=0xfff8c000
-#option SCSIFW_START=0xfff80000
-
-#option CONFIG_FS_STREAM=1
-#option CONFIG_IDE=1
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=15
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S2882"
-option MAINBOARD_VENDOR="Tyan"
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-#SMDC support
-#option CONFIG_CONSOLE_SERIAL8250_2=1
-#option TTYS1_BAUD=19200
-
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s2882
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
# 64K for Etherboot
-# option ROM_SIZE = 458752
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
- option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2882
-# payload ../../../payloads/tg3--ide_disk.zelf
+# option ROM_SIZE = 458752
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
- payload ../../../payloads/tg3--filo_btext.zelf
-# SMDC support
-# payload ../../tg3--ide_disk_com1_2.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2882
-# payload ../../../payloads/tg3--ide_disk.zelf
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+# payload ../../../payloads/tg3--ide_disk.zelf
+# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
- payload ../../../payloads/tg3_btext.zelf
-
-#SMDC support
-# payload ../../tg3--ide_disk_com1_2.zelf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
# the Tyan s2885
# This will make a target directory of ./s2885
-loadoptions
-
target s2885
+mainboard tyan/s2885
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-#option CONFIG_VGABIOS=1
-#option CONFIG_REALMODE_IDT=1
-#option CONFIG_PCIBIOS=1
-#option VGABIOS_START=1
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-option HAVE_HARD_RESET=1
-
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=11
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S2885"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=8
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s2895
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
# 64K for Etherboot
# option ROM_SIZE = 458752
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
- option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2885
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s2885
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
# Sample config file for
-# the Tyan s2880
-# This will make a target directory of ./s2880
-
-loadoptions
+# the Tyan s4880
+# This will make a target directory of ./s4880
target s4880
+mainboard tyan/s4880
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-#uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_HARD_RESET=1
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-#option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=0
-#option CONFIG_REALMODE_IDT=0
-#option CONFIG_PCIBIOS=0
-#option VGABIOS_START=0xfff8c000
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=22
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=4
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=4
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S4880"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s4880
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s4880
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
-# payload ../../../payloads/tg3--filo_btext.zelf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s4880
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
-# payload ../../../payloads/tg3--filo_btext.zelf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
# Sample config file for
-# the Tyan s2880
-# This will make a target directory of ./s2880
-
-loadoptions
+# the Tyan s4882
+# This will make a target directory of ./s4882
target s4882
+mainboard tyan/s4882
-uses ARCH
-uses CONFIG_COMPRESS
-uses CONFIG_IOAPIC
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_SMP
-uses CONFIG_UDELAY_TSC
-uses CPU_FIXUP
-uses FALLBACK_SIZE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses i586
-uses i686
-uses INTEL_PPRO_MTRR
-uses HEAP_SIZE
-uses IRQ_SLOT_COUNT
-uses k7
-uses k8
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-#uses MEMORY_HOLE
-uses PAYLOAD_SIZE
-uses _RAMBASE
-uses _ROMBASE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_OFFSET
-uses ROM_SECTION_SIZE
-uses ROM_SIZE
-uses STACK_SIZE
-uses USE_FALLBACK_IMAGE
-uses USE_OPTION_TABLE
-uses HAVE_OPTION_TABLE
-uses CONFIG_CHIP_CONFIGURE
-
-#uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses DEBUG
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses LINUXBIOS_EXTRA_VERSION
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-uses HAVE_HARD_RESET
-
-#uses CONFIG_VGABIOS
-#uses CONFIG_REALMODE_IDT
-#uses CONFIG_PCIBIOS
-#uses VGABIOS_START
-#uses SCSIFW_START
-
-#
-#uses CONFIG_LSI_SCSI_FW_FIXUP
-
-option HAVE_HARD_RESET=1
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option CPU_FIXUP=1
-option CONFIG_UDELAY_TSC=0
-option i686=1
-option i586=1
-option INTEL_PPRO_MTRR=1
-option k7=1
-option k8=1
-option ROM_SIZE=524288
-
-#option CONFIG_CONSOLE_BTEXT=1
-#option CONFIG_VGABIOS=0
-#option CONFIG_REALMODE_IDT=0
-#option CONFIG_PCIBIOS=0
-#option VGABIOS_START=0xfff8c000
-#option SCSIFW_START=0xfff80000
-
-
-option HAVE_FALLBACK_BOOT=1
-
-# use the new chip configure code.
-
-option CONFIG_CHIP_CONFIGURE=1
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=22
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=4
-option CONFIG_LOGICAL_CPUS=0
-option CONFIG_MAX_PHYSICAL_CPUS=4
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="S4882"
-option MAINBOARD_VENDOR="Tyan"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
+# Tyan s4882
romimage "normal"
-# 48K for SCSI FW
+# 48K for SCSI FW
# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s4882
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
-# payload ../../../payloads/tg3--filo_btext.zelf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- mainboard tyan/s4882
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo_mem_btext.elf
-# payload ../../../payloads/filo_btext.zelf
-# payload ../../../payloads/tg3--filo_btext.zelf
# payload ../../../payloads/filo.zelf
- payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/tg3--filo.zelf
+# payload ../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+ payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
*
*
* Copyright 2000 Silicon Integrated System Corporation
+ * Copyright 2004 Tyan Corp
+ * yhlu yhlu@tyan.com add exclude start and end option
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#include "sst_fwhub.h"
struct flashchip flashchips[] = {
+#if 1
{"Am29F040B", AMD_ID, AM_29F040B, NULL, 512, 64 * 1024,
probe_29f040b, erase_29f040b, write_29f040b, NULL},
{"At29C040A", ATMEL_ID, AT_29C040A, NULL, 512, 256,
probe_jedec, erase_chip_jedec, write_49lf040,NULL},
{"SST49LF008A", SST_ID, SST_49LF008A, NULL, 1024, 4096,
probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub, NULL},
+#endif
{"Pm49FL004", PMC_ID, PMC_49FL004, NULL, 512, 64 * 1024,
probe_jedec, erase_chip_jedec, write_49fl004,NULL},
+#if 1
{"W29C011", WINBOND_ID, W_29C011, NULL, 128, 128,
probe_jedec, erase_chip_jedec, write_jedec, NULL},
{"W29C020C", WINBOND_ID, W_29C020C, NULL, 256, 128,
MSYSTEMS_ID, MSYSTEMS_MD2802,
NULL, 8, 8 * 1024,
probe_md2802, erase_md2802, write_md2802, read_md2802},
+#endif
{NULL,}
};
void usage(const char *name)
{
- printf("usage: %s [-rwv] [-c chipname][file]\n", name);
+ printf("usage: %s [-rwv] [-c chipname] [-s exclude_start] [-e exclude_end] [file]\n", name);
printf("-r: read flash and save into file\n"
"-w: write file into flash (default when file is specified)\n"
"-v: verify flash against file\n"
"-c: probe only for specified flash chip\n"
+ "-s: exclude start position\n"
+ "-e: exclude end postion\n"
" If no file is specified, then all that happens\n"
" is that flash info is dumped\n");
exit(1);
}
+int exclude_start_page, exclude_end_page;
+
int main(int argc, char *argv[])
{
char *buf;
int read_it = 0, write_it = 0, verify_it = 0, verbose = 0;
char *filename = NULL;
+
+ unsigned int exclude_start_position=0, exclude_end_position=0; // [x,y)
+ char *tempstr=NULL;
+#if 0
+
+#if 1
+ /* Keep fallback image */
+ exclude_start_position = 0x60000;
+ exclude_end_position = 0x80000;
+#else
+ /* Keep DMI etc. */
+ exclude_start_position = 0x60000;
+ exclude_end_position = 0x70000;
+#endif
+
+#endif
+
+ if (argc > 1) {
+ /* Yes, print them. */
+ int i;
+ printf ("The arguments are:\n");
+ for (i = 1; i < argc; ++i)
+ printf ("%s\n", argv[i]);
+ }
+
setbuf(stdout, NULL);
- while ((opt = getopt(argc, argv, "rwvVc:")) != EOF) {
+ while ((opt = getopt(argc, argv, "rwvVc:s:e:")) != EOF) {
switch (opt) {
case 'r':
read_it = 1;
case 'V':
verbose = 1;
break;
+ case 's':
+ tempstr = strdup(optarg);
+ sscanf(tempstr,"%x",&exclude_start_position);
+ break;
+ case 'e':
+ tempstr = strdup(optarg);
+ sscanf(tempstr,"%x",&exclude_end_position);
+ break;
+
default:
usage(argv[0]);
break;
}
}
+
+
if (read_it && write_it) {
printf("-r and -w are mutually exclusive\n");
usage(argv[0]);
printf("Part is %s\n", flash->name);
if (!filename) {
- printf("OK, only ENABLING flash write, but NOT FLASHING\n");
+ printf
+ ("OK, only ENABLING flash write, but NOT FLASHING\n");
return 0;
}
size = flash->total_size * 1024;
memcpy(buf, (const char *) flash->virt_addr, size);
else
flash->read(flash, buf);
+
+ if(exclude_end_position - exclude_start_position > 0)
+ memset(buf+exclude_start_position, 0, exclude_end_position-exclude_start_position);
+
fwrite(buf, sizeof(char), size, image);
fclose(image);
printf("done\n");
fclose(image);
}
- if (write_it || (!read_it && !verify_it))
+ if(exclude_end_position - exclude_start_position > 0)
+ memcpy(buf+exclude_start_position, (const char *) flash->virt_addr+exclude_start_position,
+ exclude_end_position-exclude_start_position);
+
+ exclude_start_page = exclude_start_position/flash->page_size;
+ if((exclude_start_position%flash->page_size) != 0) {
+ exclude_start_page++;
+ }
+ exclude_end_page = exclude_end_position/flash->page_size;
+
+ if (write_it || (!read_it && !verify_it)) {
flash->write(flash, buf);
+ }
if (verify_it)
verify_flash(flash, buf, verbose);
return 0;
*
*
* Copyright 2004 Tyan Corporation
+ * yhlu yhlu@tyan.com add exclude range
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
return (0);
}
+
+extern int exclude_start_page, exclude_end_page;
+
int write_49fl004(struct flashchip *flash, unsigned char *buf)
{
int i;
int total_size = flash->total_size * 1024, page_size =
flash->page_size;
volatile char *bios = flash->virt_addr;
-
+
printf("Programming Page: ");
for (i = 0; i < total_size / page_size; i++) {
+ if( (i>=exclude_start_page) && (i<exclude_end_page))
+ continue;
+
/* erase the page before programming */
erase_block_49fl004(bios, i * page_size);
projects / coreboot.git / commitdiff