3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <arch/smp/lapic.h>
8 #include "option_table.h"
9 #include "pc80/mc146818rtc_early.c"
10 #include "pc80/serial.c"
11 #include "arch/i386/lib/console.c"
12 #include "ram/ramtest.c"
13 #include "northbridge/amd/amdk8/incoherent_ht.c"
14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
15 #include "northbridge/amd/amdk8/raminit.h"
16 #include "cpu/k8/apic_timer.c"
17 #include "lib/delay.c"
18 #include "cpu/p6/boot_cpu.c"
19 #include "northbridge/amd/amdk8/reset_test.c"
20 #include "northbridge/amd/amdk8/debug.c"
21 #include "northbridge/amd/amdk8/cpu_rev.c"
22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
24 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
26 static void hard_reset(void)
31 pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
36 static void soft_reset(void)
39 pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
42 static void memreset_setup(void)
44 if (is_cpu_pre_c0()) {
45 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
48 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
50 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
53 static void memreset(int controllers, const struct mem_controller *ctrl)
55 if (is_cpu_pre_c0()) {
57 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
62 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
64 /* Routing Table Node i
66 * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
67 * i: 0, 1, 2, 3, 4, 5, 6, 7
69 * [ 0: 3] Request Route
70 * [0] Route to this node
74 * [11: 8] Response Route
75 * [0] Route to this node
79 * [19:16] Broadcast route
80 * [0] Route to this node
86 uint32_t ret=0x00010101; /* default row entry */
88 static const unsigned int rows_2p[2][2] = {
89 { 0x00030101, 0x00010202 },
90 { 0x00010202, 0x00030101 }
94 print_debug("this mainboard is only designed for 2 cpus\r\n");
99 if (!(node>=maxnodes || row>=maxnodes)) {
100 ret=rows_2p[node][row];
106 static inline void activate_spd_rom(const struct mem_controller *ctrl)
111 static inline int spd_read_byte(unsigned device, unsigned address)
113 return smbus_read_byte(device, address);
116 #include "northbridge/amd/amdk8/raminit.c"
117 #include "northbridge/amd/amdk8/coherent_ht.c"
118 #include "sdram/generic_sdram.c"
120 #include "resourcemap.c" /* tyan does not want the default */
124 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
125 static void main(void)
127 static const struct mem_controller cpu[] = {
131 .f0 = PCI_DEV(0, 0x18, 0),
132 .f1 = PCI_DEV(0, 0x18, 1),
133 .f2 = PCI_DEV(0, 0x18, 2),
134 .f3 = PCI_DEV(0, 0x18, 3),
135 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
136 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
142 .f0 = PCI_DEV(0, 0x19, 0),
143 .f1 = PCI_DEV(0, 0x19, 1),
144 .f2 = PCI_DEV(0, 0x19, 2),
145 .f3 = PCI_DEV(0, 0x19, 3),
146 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
147 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
154 if (cpu_init_detected()) {
155 asm("jmp __cpu_reset");
157 distinguish_cpu_resets();
161 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
164 setup_s2881_resource_map();
165 needs_reset = setup_coherent_ht_domain();
166 needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
168 print_info("ht reset -\r\n");
177 dump_spd_registers(&cpu[0]);
180 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
186 dump_pci_device(PCI_DEV(0, 0x18, 1));
189 /* Check all of memory */
192 msr = rdmsr(TOP_MEM2);
193 print_debug("TOP_MEM2: ");
194 print_debug_hex32(msr.hi);
195 print_debug_hex32(msr.lo);
200 ram_check(0x00000000, msr.lo+(msr.hi<<32));
203 // Check 16MB of memory @ 0
204 ram_check(0x00000000, 0x01000000);
206 // Check 16MB of memory @ 2GB
207 ram_check(0x80000000, 0x81000000);