src/mainboard/tyan/s4882/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12
  13 #
  14 #
  15 ###
  16 ### Set all of the defaults for an x86 architecture
  17 ###
  18 #
  19 #
  20 ###
  21 ### Build the objects we have code for in this directory.
  22 ###
  23 ##object mainboard.o
  24 config chip.h
  25 register "fixup_scsi" = "1"
  26 #register "fixup_vga" = "1"
  27
  28
  29 ##
  30 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  31 ##
  32 default LB_CKS_RANGE_START=49
  33 default LB_CKS_RANGE_END=122
  34 default LB_CKS_LOC=123
  35
  36 driver mainboard.o
  37 #dir /drivers/lsi/53c1030
  38 #dir /drivers/adaptec/7902
  39 #dir /drivers/si/3114
  40 #dir /drivers/intel/82551
  41 #dir /drivers/ati/ragexl
  42 #object reset.o
  43 if HAVE_MP_TABLE object mptable.o end
  44 if HAVE_PIRQ_TABLE object irq_tables.o end
  45 #
  46 default HARD_RESET_BUS=1
  47 default HARD_RESET_DEVICE=4
  48 default HARD_RESET_FUNCTION=0
  49 #
  50 arch i386 end
  51 #cpu k8 end
  52 #
  53 ###
  54 ### Build our 16 bit and 32 bit linuxBIOS entry code
  55 ###
  56 mainboardinit cpu/i386/entry16.inc
  57 mainboardinit cpu/i386/entry32.inc
  58 mainboardinit cpu/i386/bist32.inc
  59 ldscript /cpu/i386/entry16.lds
  60 ldscript /cpu/i386/entry32.lds
  61 #
  62 ###
  63 ### Build our reset vector (This is where linuxBIOS is entered)
  64 ###
  65 if USE_FALLBACK_IMAGE
  66         mainboardinit cpu/i386/reset16.inc
  67         ldscript /cpu/i386/reset16.lds
  68 else
  69         mainboardinit cpu/i386/reset32.inc
  70         ldscript /cpu/i386/reset32.lds
  71 end
  72 #
  73 #### Should this be in the northbridge code?
  74 mainboardinit arch/i386/lib/cpu_reset.inc
  75 #
  76 ###
  77 ### Include an id string (For safe flashing)
  78 ###
  79 mainboardinit arch/i386/lib/id.inc
  80 ldscript /arch/i386/lib/id.lds
  81 #
  82 ####
  83 #### This is the early phase of linuxBIOS startup
  84 #### Things are delicate and we test to see if we should
  85 #### failover to another image.
  86 ####
  87 #option MAX_REBOOT_CNT=2
  88 if USE_FALLBACK_IMAGE
  89   ldscript /arch/i386/lib/failover.lds
  90 end
  91 #
  92 ###
  93 ### Setup our mtrrs
  94 ###
  95 mainboardinit cpu/k8/earlymtrr.inc
  96 ###
  97 ### Only the bootstrap cpu makes it here.
  98 ### Failover if we need to
  99 ###
 100 #
 101 if USE_FALLBACK_IMAGE
 102   mainboardinit ./failover.inc
 103 end
 104
 105 #
 106 #
 107 ###
 108 ### Setup the serial port
 109 ###
 110 mainboardinit pc80/serial.inc
 111 mainboardinit arch/i386/lib/console.inc
 112 mainboardinit cpu/i386/bist32_fail.inc
 113 #
 114 ####
 115 #### O.k. We aren't just an intermediary anymore!
 116 ####
 117 #
 118 ###
 119 ### Romcc output
 120 ###
 121 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
 122 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
 123 #mainboardinit .failover.inc
 124
 125 makerule ./failover.E
 126         depends "$(MAINBOARD)/failover.c"
 127         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 128 end
 129
 130 makerule ./failover.inc
 131         depends "./romcc ./failover.E"
 132         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 133
 134 makerule ./auto.E
 135         depends "$(MAINBOARD)/auto.c option_table.h"
 136         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 137 end
 138 makerule ./auto.inc
 139         depends "./romcc ./auto.E"
 140         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 141 end
 142 mainboardinit cpu/k8/enable_mmx_sse.inc
 143 mainboardinit ./auto.inc
 144 mainboardinit cpu/k8/disable_mmx_sse.inc
 145 #
 146 ###
 147 ### Include the secondary Configuration files
 148 ###
 149 northbridge amd/amdk8 "mc0"
 150         pci 0:18.0
 151         pci 0:18.0
 152         pci 0:18.0
 153         pci 0:18.1
 154         pci 0:18.2
 155         pci 0:18.3
 156         southbridge amd/amd8131 "amd8131" link 1
 157                 pci 0:0.0
 158                 pci 0:0.1
 159                 pci 0:1.0
 160                 pci 0:1.1
 161         end
 162         southbridge amd/amd8111 "amd8111" link 1
 163                 pci 0:0.0
 164                 pci 0:1.0 on
 165                 pci 0:1.1 on
 166                 pci 0:1.2 on
 167                 pci 0:1.3 on
 168                 pci 0:1.5 off
 169                 pci 0:1.6 off
 170                 pci 1:0.0 on
 171                 pci 1:0.1 on
 172                 pci 1:0.2 off
 173                 pci 1:1.0 off
 174                 superio winbond/w83627hf link 1
 175                         pnp 2e.0 off #  Floppy
 176                                  io 0x60 = 0x3f0
 177                                 irq 0x70 = 6
 178                                 drq 0x74 = 2
 179                         pnp 2e.1 off #  Parallel Port
 180                                  io 0x60 = 0x378
 181                                 irq 0x70 = 7
 182                         pnp 2e.2 on #  Com1
 183                                  io 0x60 = 0x3f8
 184                                 irq 0x70 = 4
 185                         pnp 2e.3 off #  Com2
 186                                  io 0x60 = 0x2f8
 187                                 irq 0x70 = 3
 188                         pnp 2e.5 on #  Keyboard
 189                                  io 0x60 = 0x60
 190                                  io 0x62 = 0x64
 191                                 irq 0x70 = 1
 192                                 irq 0x72 = 12
 193                         pnp 2e.6 off #  CIR
 194                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 195                         pnp 2e.8 off #  GPIO2
 196                         pnp 2e.9 off #  GPIO3
 197                         pnp 2e.a off #  ACPI
 198                         pnp 2e.b on  #  HW Monitor
 199                                  io 0x60 = 0x290
 200                 end
 201         end
 202 end
 203
 204 northbridge amd/amdk8 "mc1"
 205         pci 0:19.0
 206         pci 0:19.0
 207         pci 0:19.0
 208         pci 0:19.1
 209         pci 0:19.2
 210         pci 0:19.3
 211 end
 212
 213 northbridge amd/amdk8 "mc2"
 214         pci 0:1a.0
 215         pci 0:1a.0
 216         pci 0:1a.0
 217         pci 0:1a.1
 218         pci 0:1a.2
 219         pci 0:1a.3
 220 end
 221
 222
 223 northbridge amd/amdk8 "mc3"
 224         pci 0:1b.0
 225         pci 0:1b.0
 226         pci 0:1b.0
 227         pci 0:1b.1
 228         pci 0:1b.2
 229         pci 0:1b.3
 230 end
 231
 232
 233 dir /pc80
 234 #dir /bioscall
 235
 236 cpu k8 "cpu0"
 237   register "ldt1" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 238 end
 239
 240 cpu k8 "cpu1"
 241 end
 242
 243 cpu k8 "cpu2"
 244 end
 245
 246 cpu k8 "cpu3"
 247 end