src/mainboard/tyan/s2850/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <arch/smp/lapic.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "ram/ramtest.c"
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/k8/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/p6/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include "northbridge/amd/amdk8/cpu_rev.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23
  24 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  25
  26 static void hard_reset(void)
  27 {
  28         set_bios_reset();
  29
  30         /* enable cf9 */
  31         pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
  32         /* reset */
  33         outb(0x0e, 0x0cf9);
  34 }
  35
  36 static void soft_reset(void)
  37 {
  38         set_bios_reset();
  39         pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
  40 }
  41
  42 #define REV_B_RESET 0
  43 static void memreset_setup(void)
  44 {
  45         if (is_cpu_pre_c0()) {
  46                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (0 << 0), SMBUS_IO_BASE + 0xc0 + 16);       //REVC_MEMRST_EN=0
  47         } else {
  48                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 16);       //REVC_MEMRST_EN=1
  49         }
  50         outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
  51              (0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56         if (is_cpu_pre_c0()) {
  57                 udelay(800);
  58                 outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) | (1 << 0), SMBUS_IO_BASE + 0xc0 + 17);       //REVB_MEMRST_L=1
  59                 udelay(90);
  60         }
  61 }
  62
  63
  64 static unsigned int generate_row(uint8_t node, uint8_t row,
  65                                  uint8_t maxnodes)
  66 {
  67         /* Routing Table Node i
  68          *
  69          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  70          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  71          *
  72          * [ 0: 3] Request Route
  73          *     [0] Route to this node
  74          *     [1] Route to Link 0
  75          *     [2] Route to Link 1
  76          *     [3] Route to Link 2
  77          * [11: 8] Response Route
  78          *     [0] Route to this node
  79          *     [1] Route to Link 0
  80          *     [2] Route to Link 1
  81          *     [3] Route to Link 2
  82          * [19:16] Broadcast route
  83          *     [0] Route to this node
  84          *     [1] Route to Link 0
  85          *     [2] Route to Link 1
  86          *     [3] Route to Link 2
  87          */
  88
  89         uint32_t ret = 0x00010101;      /* default row entry */
  90
  91
  92         return ret;
  93 }
  94
  95 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  96 {
  97         /* nothing to do */
  98 }
  99
 100 static inline int spd_read_byte(unsigned device, unsigned address)
 101 {
 102         return smbus_read_byte(device, address);
 103 }
 104
 105 #include "northbridge/amd/amdk8/raminit.c"
 106 #include "northbridge/amd/amdk8/coherent_ht.c"
 107 #include "northbridge/amd/amdk8/resourcemap.c"
 108 #include "sdram/generic_sdram.c"
 109
 110 static void main(void)
 111 {
 112         /*
 113          * GPIO28 of 8111 will control H0_MEMRESET_L
 114          * GPIO29 of 8111 will control H1_MEMRESET_L
 115          */
 116         static const struct mem_controller cpu[] = {
 117                 {
 118                  .node_id = 0,
 119                  .f0 = PCI_DEV(0, 0x18, 0),
 120                  .f1 = PCI_DEV(0, 0x18, 1),
 121                  .f2 = PCI_DEV(0, 0x18, 2),
 122                  .f3 = PCI_DEV(0, 0x18, 3),
 123                  .channel0 = {(0xa << 3) | 0, (0xa << 3) | 2, 0, 0},
 124                  .channel1 = {(0xa << 3) | 1, (0xa << 3) | 3, 0, 0},
 125                  },
 126         };
 127
 128         int needs_reset;
 129         enable_lapic();
 130         init_timer();
 131         if (cpu_init_detected()) {
 132                 asm("jmp __cpu_reset");
 133         }
 134         distinguish_cpu_resets();
 135         if (!boot_cpu()) {
 136                 stop_this_cpu();
 137         }
 138         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 139         uart_init();
 140         console_init();
 141         setup_default_resource_map();
 142         needs_reset = setup_coherent_ht_domain();
 143         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 144         if (needs_reset) {
 145                 print_info("ht reset -\r\n");
 146                 soft_reset();
 147         }
 148 #if 0
 149         print_pci_devices();
 150 #endif
 151         enable_smbus();
 152 #if 0
 153 //      dump_spd_registers(&cpu[0]);
 154         dump_smbus_registers();
 155 #endif
 156
 157         memreset_setup();
 158         sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
 159
 160 #if 0
 161         dump_pci_devices();
 162 #endif
 163 #if 0
 164         dump_pci_device(PCI_DEV(0, 0x18, 1));
 165 #endif
 166
 167         /* Check all of memory */
 168 #if 0
 169         msr_t msr;
 170         msr = rdmsr(TOP_MEM2);
 171         print_debug("TOP_MEM2: ");
 172         print_debug_hex32(msr.hi);
 173         print_debug_hex32(msr.lo);
 174         print_debug("\r\n");
 175 #endif
 176 /*
 177 #if  0
 178         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 179 #else
 180 #if TOTAL_CPUS < 2
 181         // Check 16MB of memory @ 0
 182         ram_check(0x00000000, 0x01000000);
 183 #else
 184         // Check 16MB of memory @ 2GB
 185         ram_check(0x80000000, 0x81000000);
 186 #endif
 187 #endif
 188 */
 189 }