2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * Description: Include file for all generic DDR 3 MCT files.
26 /*===========================================================================
28 ===========================================================================*/
29 #define PT_L1 0 /* CPU Package Type */
36 #define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
37 #define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/
38 #define K_MIN 1 /* k loop constraint. 1=200 Mhz*/
39 #define K_MAX 5 /* k loop constraint. 5=533 Mhz*/
40 #define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
41 #define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
43 #define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
44 /* memory initialization (ecc and check-bits).*/
45 /* 1=40 ns/64 bytes.*/
46 #define FirstPass 1 /* First pass through RcvEn training*/
47 #define SecondPass 2 /* Second pass through Rcven training*/
49 #define RCVREN_MARGIN 6 /* number of DLL taps to delay beyond first passing position*/
50 #define MAXASYNCLATCTL_2 2 /* Max Async Latency Control value*/
51 #define MAXASYNCLATCTL_3 3 /* Max Async Latency Control value*/
55 #define DQS_WRITEDIR 1
57 #define MIN_DQS_WNDW 3
58 #define secPassOffset 6
59 #define Pass1MemClkDly 0x20 /* Add 1/2 Memlock delay */
60 #define MAX_RD_LAT 0x3FF
63 #define MIN_DQS_WR_FENCE 14
64 #define MAX_DQS_WR_FENCE 20
65 #define FenceTrnFinDlySeed 19
68 #define PA_HOST(Node) ((((0x18+Node) << 3)+0) << 12) /* Node 0 Host Bus function PCI Address bits [15:0]*/
69 #define PA_MAP(Node) ((((0x18+Node) << 3)+1) << 12) /* Node 0 MAP function PCI Address bits [15:0]*/
70 #define PA_DCT(Node) ((((0x18+Node) << 3)+2) << 12) /* Node 0 DCT function PCI Address bits [15:0]*/
71 /* #define PA_EXT_DCT (((00 << 3)+4) << 8) */ /*Node 0 DCT extended configuration registers*/
72 /* #define PA_DCTADDL (((00 << 3)+2) << 8) */ /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/
73 /* #define PA_EXT_DCTADDL (((00 << 3)+5) << 8) */ /*Node x DCT function, Additional Registers PCI Address bits [15:0]*/
75 #define PA_NBMISC(Node) ((((0x18+Node) << 3)+3) << 12) /*Node 0 Misc PCI Address bits [15:0]*/
76 /* #define PA_NBDEVOP (((00 << 3)+3) << 8) */ /*Node 0 Misc PCI Address bits [15:0]*/
78 #define DCC_EN 1 /* X:2:0x94[19]*/
79 #define ILD_Lmt 3 /* X:2:0x94[18:16]*/
81 #define EncodedTSPD 0x00191709 /* encodes which SPD byte to get T from*/
82 /* versus CL X, CL X-.5, and CL X-1*/
84 #define Bias_TrpT 5 /* bias to convert bus clocks to bit field value*/
94 #define Min_TrpT 5 /* min programmable value in busclocks */
95 #define Max_TrpT 12 /* max programmable value in busclocks */
113 /*common register bit names*/
114 #define DramHoleValid 0 /* func 1, offset F0h, bit 0*/
115 #define DramMemHoistValid 1 /* func 1, offset F0h, bit 1*/
116 #define CSEnable 0 /* func 2, offset 40h-5C, bit 0*/
117 #define Spare 1 /* func 2, offset 40h-5C, bit 1*/
118 #define TestFail 2 /* func 2, offset 40h-5C, bit 2*/
119 #define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/
120 #define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/
121 #define PchgPDModeSel 23 /* func 2, offset 84h, bit 23 */
122 #define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/
123 #define InitDram 0 /* func 2, offset 90h, bit 0*/
124 #define BurstLength32 10 /* func 2, offset 90h, bit 10*/
125 #define Width128 11 /* func 2, offset 90h, bit 11*/
126 #define X4Dimm 12 /* func 2, offset 90h, bit 12*/
127 #define UnBuffDimm 16 /* func 2, offset 90h, bit 16*/
128 #define DimmEcEn 19 /* func 2, offset 90h, bit 19*/
129 #define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/
130 #define RDqsEn 12 /* func 2, offset 94h, bit 12*/
131 #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/
132 #define PowerDownEn 15 /* func 2, offset 94h, bit 15*/
133 #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/
134 #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/
135 #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/
136 #define PwrSavingsEn 10 /* func 2, offset A0h, bit 10*/
137 #define Mod64BitMux 4 /* func 2, offset A0h, bit 4*/
138 #define DisableJitter 1 /* func 2, offset A0h, bit 1*/
139 #define MemClrDis 1 /* func 3, offset F8h, FNC 4, bit 1*/
140 #define SyncOnUcEccEn 2 /* func 3, offset 44h, bit 2*/
141 #define Dr_MemClrStatus 10 /* func 3, offset 110h, bit 10*/
142 #define MemClrBusy 9 /* func 3, offset 110h, bit 9*/
143 #define DctGangEn 4 /* func 3, offset 110h, bit 4*/
144 #define MemClrInit 3 /* func 3, offset 110h, bit 3*/
145 #define SendZQCmd 29 /* func 2, offset 7Ch, bit 29 */
146 #define AssertCke 28 /* func 2, offset 7Ch, bit 28*/
147 #define DeassertMemRstX 27 /* func 2, offset 7Ch, bit 27*/
148 #define SendMrsCmd 26 /* func 2, offset 7Ch, bit 26*/
149 #define SendAutoRefresh 25 /* func 2, offset 7Ch, bit 25*/
150 #define SendPchgAll 24 /* func 2, offset 7Ch, bit 24*/
151 #define DisDqsBar 6 /* func 2, offset 90h, bit 6*/
152 #define DramEnabled 8 /* func 2, offset 110h, bit 8*/
153 #define LegacyBiosMode 9 /* func 2, offset 94h, bit 9*/
154 #define PrefDramTrainMode 28 /* func 2, offset 11Ch, bit 28*/
155 #define FlushWr 30 /* func 2, offset 11Ch, bit 30*/
156 #define DisAutoComp 30 /* func 2, offset 9Ch, Index 8, bit 30*/
157 #define DqsRcvTrEn 13 /* func 2, offset 9Ch, Index 8, bit 13*/
158 #define ForceAutoPchg 23 /* func 2, offset 90h, bit 23*/
159 #define ClLinesToNbDis 15 /* Bu_CFG2, bit 15*/
160 #define WbEnhWsbDis_D (48-32)
161 #define PhyFenceTrEn 3 /* func 2, offset 9Ch, Index 8, bit 3 */
162 #define ParEn 8 /* func 2, offset 90h, bit 8 */
163 #define DcqArbBypassEn 19 /* func 2, offset 94h, bit 19 */
164 #define ActiveCmdAtRst 1 /* func 2, offset A8H, bit 1 */
165 #define FlushWrOnStpGnt 29 /* func 2, offset 11Ch, bit 29 */
166 #define BankSwizzleMode 22 /* func 2, offset 94h, bit 22 */
167 #define ChSetupSync 15 /* func 2, offset 78h, bit 15 */
169 #define Ddr3Mode 8 /* func 2, offset 94h, bit 8 */
170 #define EnterSelfRef 17 /* func 2, offset 90h, bit 17 */
171 #define onDimmMirror 3 /* func 2, offset 5C:40h, bit 3 */
172 #define OdtSwizzle 6 /* func 2, offset A8h, bit 6 */
173 #define FreqChgInProg 21 /* func 2, offset 94h, bit 21 */
174 #define ExitSelfRef 1 /* func 2, offset 90h, bit 1 */
176 #define SubMemclkRegDly 5 /* func 2, offset A8h, bit 5 */
177 #define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */
178 #define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */
180 #define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */
181 /*=============================================================================
183 ============================================================================*/
185 #define OCD_Default 2
188 /*=============================================================================
190 =============================================================================*/
191 #define SPD_ByteUse 0
192 #define SPD_TYPE 2 /*SPD byte read location*/
193 #define JED_DDRSDRAM 0x07 /*Jedec defined bit field*/
194 #define JED_DDR2SDRAM 0x08 /*Jedec defined bit field*/
195 #define JED_DDR3SDRAM 0x0B /* Jedec defined bit field*/
197 #define SPD_DIMMTYPE 3
198 #define SPD_ATTRIB 21
199 #define JED_DIFCKMSK 0x20 /*Differential Clock Input*/
200 #define JED_REGADCMSK 0x11 /*Registered Address/Control*/
201 #define JED_PROBEMSK 0x40 /*Analysis Probe installed*/
202 #define JED_RDIMM 0x1 /* RDIMM */
203 #define JED_MiniRDIMM 0x5 /* Mini-RDIMM */
204 #define SPD_Density 4 /* Bank address bits,SDRAM capacity */
205 #define SPD_Addressing 5 /* Row/Column address bits */
206 #define SPD_Organization 7 /* rank#,Device width */
207 #define SPD_BusWidth 8 /* ECC, Bus width */
208 #define JED_ECC 8 /* ECC capability */
210 #define SPD_MTBDividend 10
211 #define SPD_MTBDivisor 11
212 #define SPD_tCKmin 12
213 #define SPD_CASLow 14
214 #define SPD_CASHigh 15
215 #define SPD_tAAmin 16
217 #define SPD_DEVATTRIB 22
218 #define SPD_EDCTYPE 11
219 #define JED_ADRCPAR 0x04
221 #define SPD_tWRmin 17
222 #define SPD_tRCDmin 18
223 #define SPD_tRRDmin 19
224 #define SPD_tRPmin 20
225 #define SPD_Upper_tRAS_tRC 21
226 #define SPD_tRASmin 22
227 #define SPD_tRCmin 23
228 #define SPD_tWTRmin 26
229 #define SPD_tRTPmin 27
230 #define SPD_Upper_tFAW 28
231 #define SPD_tFAWmin 29
233 #define SPD_RefRawCard 62
234 #define SPD_AddressMirror 63
235 #define SPD_RegManufactureID_L 65 /* not used */
236 #define SPD_RegManufactureID_H 66 /* not used */
237 #define SPD_RegManRevID 67 /* not used */
239 #define SPD_byte_126 126
240 #define SPD_byte_127 127
244 #define SPD_LBANKS 17 /*number of [logical] banks on each device*/
245 #define SPD_DMBANKS 5 /*number of physical banks on dimm*/
246 #define SPDPLBit 4 /* Dram package bit*/
247 #define SPD_BANKSZ 31 /*capacity of physical bank*/
248 #define SPD_DEVWIDTH 13
249 #define SPD_CASLAT 18
257 #define SPD_TRCRFC 40
261 #define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/
263 #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/
265 /*-----------------------------
266 Jedec DDR II related equates
267 -----------------------------*/
268 #define MYEAR06 6 /* Manufacturing Year BCD encoding of 2006 - 06d*/
269 #define MWEEK24 0x24 /* Manufacturing Week BCD encoding of June - 24d*/
271 /*=============================================================================
273 =============================================================================*/
275 #define _2GB_RJ8 (2<<(30-8))
276 #define _4GB_RJ8 (4<<(30-8))
277 #define _4GB_RJ4 (4<<(30-4))
279 #define BigPagex8_RJ8 (1<<(17+3-8)) /*128KB * 8 >> 8 */
281 /*=============================================================================
282 Global MCT Status Structure
283 =============================================================================*/
284 struct MCTStatStruc {
285 u32 GStatus; /* Global Status bitfield*/
286 u32 HoleBase; /* If not zero, BASE[39:8] (system address)
287 of sub 4GB dram hole for HW remapping.*/
288 u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/
289 u32 SysLimit; /* LIMIT[39:8] (system address)*/
292 /*=============================================================================
293 Global MCT Configuration Status Word (GStatus)
294 =============================================================================*/
295 /*These should begin at bit 0 of GStatus[31:0]*/
296 #define GSB_MTRRshort 0 /* Ran out of MTRRs while mapping memory*/
297 #define GSB_ECCDIMMs 1 /* All banks of all Nodes are ECC capable*/
298 #define GSB_DramECCDis 2 /* Dram ECC requested but not enabled.*/
299 #define GSB_SoftHole 3 /* A Node Base gap was created*/
300 #define GSB_HWHole 4 /* A HW dram remap was created*/
301 #define GSB_NodeIntlv 5 /* Node Memory interleaving was enabled*/
302 #define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/
303 #define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */
304 /* NOTE: This is a local bit used by memory code */
306 /*===============================================================================
307 Local DCT Status structure (a structure for each DCT)
308 ===============================================================================*/
309 #include "mwlc_d.h" /* I have to */
311 struct DCTStatStruc { /* A per Node structure*/
312 /* DCTStatStruct_F - start */
313 u8 Node_ID; /* Node ID of current controller*/
314 u8 ErrCode; /* Current error condition of Node
316 1= Variance Error, DCT is running but not in an optimal configuration.
317 2= Stop Error, DCT is NOT running
318 3= Fatal Error, DCT/MCT initialization has been halted.*/
319 u32 ErrStatus; /* Error Status bit Field */
320 u32 Status; /* Status bit Field*/
321 u8 DIMMAddr[8]; /* SPD address of DIMM controlled by MA0_CS_L[0,1]*/
322 /* SPD address of..MB0_CS_L[0,1]*/
323 /* SPD address of..MA1_CS_L[0,1]*/
324 /* SPD address of..MB1_CS_L[0,1]*/
325 /* SPD address of..MA2_CS_L[0,1]*/
326 /* SPD address of..MB2_CS_L[0,1]*/
327 /* SPD address of..MA3_CS_L[0,1]*/
328 /* SPD address of..MB3_CS_L[0,1]*/
329 u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present.
339 u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
340 u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */
341 u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
342 u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
343 u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
344 u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
345 u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
346 u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
347 u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
348 u8 MAload[2]; /* Number of devices loading MAA bus*/
349 /* Number of devices loading MAB bus*/
350 u8 MAdimms[2]; /*Number of DIMMs loading CH A*/
351 /* Number of DIMMs loading CH B*/
352 u8 DATAload[2]; /*Number of ranks loading CH A DATA*/
353 /* Number of ranks loading CH B DATA*/
354 u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs
360 u8 DIMMCASL; /* Min valid Mfg. CL bitfield
366 u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
367 u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
368 u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
369 u16 DIMMTras; /* Minimax Tras*40 (ns) of DIMMs*/
370 u16 DIMMTrc; /* Minimax Trc*40 (ns) of DIMMs*/
371 u16 DIMMTwr; /* Minimax Twr*40 (ns) of DIMMs*/
372 u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
373 u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
374 u8 Speed; /* Bus Speed (to set Controller)
379 u8 CASL; /* CAS latency DCT setting
385 u8 Trcd; /* DCT Trcd (busclocks) */
386 u8 Trp; /* DCT Trp (busclocks) */
387 u8 Trtp; /* DCT Trtp (busclocks) */
388 u8 Tras; /* DCT Tras (busclocks) */
389 u8 Trc; /* DCT Trc (busclocks) */
390 u8 Twr; /* DCT Twr (busclocks) */
391 u8 Trrd; /* DCT Trrd (busclocks) */
392 u8 Twtr; /* DCT Twtr (busclocks) */
393 u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
394 0=75ns (for 256Mb devs)
395 1=105ns (for 512Mb devs)
396 2=127.5ns (for 1Gb devs)
397 3=195ns (for 2Gb devs)
398 4=327.5ns (for 4Gb devs) */
399 /* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
400 /* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
401 /* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
402 u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
403 u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
404 u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
405 u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
406 u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
407 u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
411 400=400Mhz (DDR800) */
412 u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
415 u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
416 u8 Twrrd; /* DCT Twrrd (busclocks)*/
417 u8 Twrwr; /* DCT Twrwr (busclocks)*/
418 u8 Trdrd; /* DCT Trdrd (busclocks)*/
419 u32 CH_ODC_CTL[2]; /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h*/
420 u32 CH_ADDR_TMG[2]; /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h*/
421 /* Output Driver Strength (see BKDG FN2:Offset 9Ch, index 20h*/
422 /* Address Bus Timing (see BKDG FN2:Offset 9Ch, index 24h*/
423 u16 CH_EccDQSLike[2]; /* CHA DQS ECC byte like...*/
424 u8 CH_EccDQSScale[2]; /* CHA DQS ECC byte scale*/
425 /* CHA DQS ECC byte like...*/
426 /* CHA DQS ECC byte scale*/
427 u8 MaxAsyncLat; /* Max Asynchronous Latency (ns)*/
428 /* NOTE: Not used in Barcelona - u8 CH_D_RCVRDLY[2][4]; */
429 /* CHA DIMM 0 - 4 Receiver Enable Delay*/
430 /* CHB DIMM 0 - 4 Receiver Enable Delay */
431 /* NOTE: Not used in Barcelona - u8 CH_D_B_DQS[2][2][8]; */
432 /* CHA Byte 0-7 Write DQS Delay */
433 /* CHA Byte 0-7 Read DQS Delay */
434 /* CHB Byte 0-7 Write DQS Delay */
435 /* CHB Byte 0-7 Read DQS Delay */
436 u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
437 u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/
438 u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
439 u8 ByteLane; /* Current Byte Lane (0..7)*/
440 u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
441 u8 Pattern; /* Current pattern*/
442 u8 DQSDelay; /* Current DQS delay value*/
443 u32 TrainErrors; /* Current Training Errors*/
445 u32 AMC_TSC_DeltaLo; /* Time Stamp Counter measurement of AMC, Low dword*/
446 u32 AMC_TSC_DeltaHi; /* Time Stamp Counter measurement of AMC, High dword*/
447 /* NOTE: Not used in Barcelona - */
448 u8 CH_D_DIR_MaxMin_B_Dly[2][2][2][8];
449 /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
450 /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
451 /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
452 /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
453 /* CH A byte lane 0 - 7 minimum filtered window passing DQS delay value*/
454 /* CH A byte lane 0 - 7 maximum filtered window passing DQS delay value*/
455 /* CH B byte lane 0 - 7 minimum filtered window passing DQS delay value*/
456 /* CH B byte lane 0 - 7 maximum filtered window passing DQS delay value*/
457 u32 LogicalCPUID; /* The logical CPUID of the node*/
458 u16 HostBiosSrvc1; /* Word sized general purpose field for use by host BIOS. Scratch space.*/
459 u32 HostBiosSrvc2; /* Dword sized general purpose field for use by host BIOS. Scratch space.*/
460 u16 DimmQRPresent; /* QuadRank DIMM present?*/
461 u16 DimmTrainFail; /* Bitmap showing which dimms failed training*/
462 u16 CSTrainFail; /* Bitmap showing which chipselects failed training*/
463 u16 DimmYr06; /* Bitmap indicating which Dimms have a manufactur's year code <= 2006*/
464 u16 DimmWk2406; /* Bitmap indicating which Dimms have a manufactur's week code <= 24 of 2006 (June)*/
465 u16 DimmDRPresent; /* Bitmap indicating that Dual Rank Dimms are present*/
466 u16 DimmPlPresent; /* Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.*/
467 u16 ChannelTrainFai; /* Bitmap showing the channel information about failed Chip Selects
468 0 in any bit field indicates Channel 0
469 1 in any bit field indicates Channel 1 */
470 u16 DIMMTfaw; /* Minimax Tfaw*16 (ns) of DIMMs */
471 u8 Tfaw; /* DCT Tfaw (busclocks) */
472 u16 CSUsrTestFail; /* Chip selects excluded by user */
473 /* DCTStatStruct_F - end */
475 u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/
476 /* Max Read Latency (ns) for DCT 1*/
477 u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */
478 /* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
479 /* CHA DIMM0 Byte 0 - 7 and Check Read DQS Delay*/
480 /* CHA DIMM1 Byte 0 - 7 and Check Write DQS Delay*/
481 /* CHA DIMM1 Byte 0 - 7 and Check Read DQS Delay*/
482 /* CHB DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
483 /* CHB DIMM0 Byte 0 - 7 and Check Read DQS Delay*/
484 /* CHB DIMM1 Byte 0 - 7 and Check Write DQS Delay*/
485 /* CHB DIMM1 Byte 0 - 7 and Check Read DQS Delay*/
486 u8 CH_D_B_TxDqs[2][4][9]; /* [A/B] [DIMM1-4] [DQS] */
487 /* CHA DIMM0 Byte 0 - 7 TxDqs */
488 /* CHA DIMM0 Byte 0 - 7 TxDqs */
489 /* CHA DIMM1 Byte 0 - 7 TxDqs */
490 /* CHA DIMM1 Byte 0 - 7 TxDqs */
491 /* CHB DIMM0 Byte 0 - 7 TxDqs */
492 /* CHB DIMM0 Byte 0 - 7 TxDqs */
493 /* CHB DIMM1 Byte 0 - 7 TxDqs */
494 /* CHB DIMM1 Byte 0 - 7 TxDqs */
495 u8 CH_D_B_RCVRDLY[2][4][8]; /* [A/B] [DIMM0-3] [DQS] */
496 /* CHA DIMM 0 Receiver Enable Delay*/
497 /* CHA DIMM 1 Receiver Enable Delay*/
498 /* CHA DIMM 2 Receiver Enable Delay*/
499 /* CHA DIMM 3 Receiver Enable Delay*/
501 /* CHB DIMM 0 Receiver Enable Delay*/
502 /* CHB DIMM 1 Receiver Enable Delay*/
503 /* CHB DIMM 2 Receiver Enable Delay*/
504 /* CHB DIMM 3 Receiver Enable Delay*/
505 u8 CH_D_BC_RCVRDLY[2][4];
506 /* CHA DIMM 0 - 4 Check Byte Receiver Enable Delay*/
507 /* CHB DIMM 0 - 4 Check Byte Receiver Enable Delay*/
508 u8 DIMMValidDCT[2]; /* DIMM# in DCT0*/
510 u16 CSPresent_DCT[2]; /* DCT# CS mapping */
511 u16 MirrPresU_NumRegR; /* Address mapping from edge connect to DIMM present for unbuffered dimm
512 Number of registers on the dimm for registered dimm */
513 u8 MaxDCTs; /* Max number of DCTs in system*/
514 /* NOTE: removed u8 DCT. Use ->dev_ for pci R/W; */ /*DCT pointer*/
515 u8 GangedMode; /* Ganged mode enabled, 0 = disabled, 1 = enabled*/
516 u8 DRPresent; /* Family 10 present flag, 0 = not Fam10, 1 = Fam10*/
517 u32 NodeSysLimit; /* BASE[39:8],for DCT0+DCT1 system address*/
520 /* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */
524 /* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */
531 u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/
532 u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/
533 u8 DqsRcvEn_Pass; /* for TrainRcvrEn byte lane pass flag*/
534 u8 DqsRcvEn_Saved; /* for TrainRcvrEn byte lane saved flag*/
535 u8 SeedPass1Remainder; /* for Phy assisted DQS receiver enable training*/
537 /* for second pass - Second pass should never run for Fam10*/
538 /* NOTE: Not used for Barcelona - u8 CH_D_B_RCVRDLY_1[2][4][8]; */ /* CHA DIMM 0 Receiver Enable Delay */
539 /* CHA DIMM 1 Receiver Enable Delay*/
540 /* CHA DIMM 2 Receiver Enable Delay*/
541 /* CHA DIMM 3 Receiver Enable Delay*/
543 /* CHB DIMM 0 Receiver Enable Delay*/
544 /* CHB DIMM 1 Receiver Enable Delay*/
545 /* CHB DIMM 2 Receiver Enable Delay*/
546 /* CHB DIMM 3 Receiver Enable Delay*/
548 u8 ClToNB_flag; /* is used to restore ClLinesToNbDis bit after memory */
549 u32 NodeSysBase; /* for channel interleave usage */
551 /* New for LB Support */
568 u16 RegMan1Present; /* DIMM present bitmap of Register manufacture 1 */
569 u16 RegMan2Present; /* DIMM present bitmap of Register manufacture 2 */
571 struct _sMCTStruct *C_MCTPtr;
572 struct _sDCTStruct *C_DCTPtr[2];
573 /* struct _sDCTStruct *C_DCT1Ptr; */
575 struct _sMCTStruct s_C_MCTPtr;
576 struct _sDCTStruct s_C_DCTPtr[2];
577 /* struct _sDCTStruct s_C_DCT1Ptr[8]; */
580 /*===============================================================================
581 Local Error Status Codes (DCTStatStruc.ErrCode)
582 ===============================================================================*/
583 #define SC_RunningOK 0
584 #define SC_VarianceErr 1 /* Running non-optimally*/
585 #define SC_StopError 2 /* Not Running*/
586 #define SC_FatalErr 3 /* Fatal Error, MCTB has exited immediately*/
588 /*===============================================================================
589 Local Error Status (DCTStatStruc.ErrStatus[31:0])
590 ===============================================================================*/
592 #define SB_DIMMChkSum 1
593 #define SB_DimmMismatchM 2 /* dimm module type(buffer) mismatch*/
594 #define SB_DimmMismatchT 3 /* dimm CL/T mismatch*/
595 #define SB_DimmMismatchO 4 /* dimm organization mismatch (128-bit)*/
596 #define SB_NoTrcTrfc 5 /* SPD missing Trc or Trfc info*/
597 #define SB_NoCycTime 6 /* SPD missing byte 23 or 25*/
598 #define SB_BkIntDis 7 /* Bank interleave requested but not enabled*/
599 #define SB_DramECCDis 8 /* Dram ECC requested but not enabled*/
600 #define SB_SpareDis 9 /* Online spare requested but not enabled*/
601 #define SB_MinimumMode 10 /* Running in Minimum Mode*/
602 #define SB_NORCVREN 11 /* No DQS Receiver Enable pass window found*/
603 #define SB_CHA2BRCVREN 12 /* DQS Rcvr En pass window CHA to CH B too large*/
604 #define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/
605 #define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/
606 #define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/
607 #define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */
609 /*===============================================================================
610 Local Configuration Status (DCTStatStruc.Status[31:0])
611 ===============================================================================*/
612 #define SB_Registered 0 /* All DIMMs are Registered*/
613 #define SB_ECCDIMMs 1 /* All banks ECC capable*/
614 #define SB_PARDIMMs 2 /* All banks Addr/CMD Parity capable*/
615 #define SB_DiagClks 3 /* Jedec ALL slots clock enable diag mode*/
616 #define SB_128bitmode 4 /* DCT in 128-bit mode operation*/
617 #define SB_64MuxedMode 5 /* DCT in 64-bit mux'ed mode.*/
618 #define SB_2TMode 6 /* 2T CMD timing mode is enabled.*/
619 #define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/
620 #define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/
621 #define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/
622 #define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/
623 #define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/
624 #define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/
627 /*===============================================================================
628 NVRAM/run-time-configurable Items
629 ===============================================================================*/
630 /*Platform Configuration*/
631 #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
635 #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
636 #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
637 #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
641 400=400Mhz (DDR800)*/
642 #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits)
643 0=Platform not capable
644 1=Platform is capable*/
645 #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits)
647 1=R4 (4-Rank Registered DIMMs in AMD server configuration)
648 2=S4 (Unbuffered SO-DIMMs)*/
649 #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
650 4=4 times bypass (normal for non-UMA systems)
651 7=7 times bypass (normal for UMA systems)*/
652 #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
653 2=8 times (normal for non-UMA systems)
654 3=16 times (normal for UMA systems)*/
658 #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
659 0=Auto, no user limit
660 1=Auto, user limit provided in NV_MemCkVal
661 2=Manual, user value provided in NV_MemCkVal*/
662 #define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
668 /*Dram Configuration*/
669 #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
672 #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
674 1=enable all memclocks*/
675 #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
676 0=Exit current node init if any DIMM has SPD checksum error
677 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
678 #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
680 1=perform DQS training*/
681 #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
684 #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits)
686 1=enable (4 beat burst when width is 64-bits)*/
689 #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
692 #define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
693 0=per Channel control
694 1=per Chip select control*/
695 #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
700 #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
701 NV_BottomIO[7:0]=Addr[31:24]*/
702 #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
703 NV_BottomUMA[7:0]=Addr[31:24]*/
704 #define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
709 #define NV_ECC 50 /* Dram ECC enable*/
710 #define NV_NBECC 52 /* ECC MCE enable*/
711 #define NV_ChipKill 53 /* Chip-Kill ECC Mode enable*/
712 #define NV_ECCRedir 54 /* Dram ECC Redirection enable*/
713 #define NV_DramBKScrub 55 /* Dram ECC Background Scrubber CTL*/
714 #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/
715 #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/
716 #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0:
719 /* Chip Select Spare Control bit 1-4:
720 Reserved, must be zero*/
721 #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
724 #define NV_Unganged 62
726 #define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits)
728 yy1b = enable with DctSelIntLvAddr set to yyb */
731 u32 Get_NB32(u32 dev, u32 reg);
732 void Set_NB32(u32 dev, u32 reg, u32 val);
733 u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
734 void Set_NB32_index(u32 dev, u32 index_reg, u32 index, u32 data);
735 u32 Get_NB32_index_wait(u32 dev, u32 index_reg, u32 index);
736 void Set_NB32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data);
737 u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val);
738 void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct);
739 u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value);
740 u8 mct_checkNumberOfDqsRcvEn_1Pass(u8 pass);
741 u32 SetupDqsPattern_1PassA(u8 Pass);
742 u32 SetupDqsPattern_1PassB(u8 Pass);
743 u8 mct_Get_Start_RcvrEnDly_1Pass(u8 Pass);
744 u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 RcvrEnDlyLimit, u8 Channel, u8 Receiver, u8 Pass);
745 void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
746 void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
747 u32 mctGetLogicalCPUID(u32 Node);
748 u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
749 void TrainReceiverEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u8 Pass);
750 void mct_TrainDQSPos_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
751 void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
752 void TrainMaxReadLatency_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
753 void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,struct DCTStatStruc *pDCTstatA);
754 void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly, u8 FinalValue, u8 Channel, u8 Receiver, u32 dev, u32 index_reg, u8 Addl_Index, u8 Pass);
755 void SetEccDQSRcvrEn_D(struct DCTStatStruc *pDCTstat, u8 Channel);
756 void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 dct);
757 void InterleaveBanks_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct);
758 void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, u32 DramConfigHi);
759 void mct_DramInit_Hw_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct);
760 void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
761 void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
762 void mct_TrainRcvrEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Pass);
763 void mct_EnableDimmEccEn_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 _DisableDramECC);
764 u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val);
765 void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct);
766 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node);
767 void mctSMBhub_Init(u32 node);
768 int mctRead_SPD(u32 smaddr, u32 reg);
769 void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
770 void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
771 void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
773 void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
774 u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass);
775 u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct);
776 void mct_Wait(u32 cycles);
777 u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel);
778 u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid);
779 void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr);