wurms gitweb - coreboot.git/history - src/northbridge/amd/amdmct/mct_ddr3/mct

2011-06-03	Marc Jones	This patch sets max freq defaults for ddr2 and ddr3for...	blob \| commitdiff \| raw
2011-01-06	Zheng Bao	Fix some settings fo AMD MCT. It is based on BIOS test...	blob \| commitdiff \| raw \| diff to current
2010-10-08	Zheng Bao	Trivial. Spell checking.	blob \| commitdiff \| raw \| diff to current
2010-09-28	Zheng Bao	Trivial. re-Indent the code.	blob \| commitdiff \| raw \| diff to current
2010-09-27	Xavi Drudis Ferran	Obviously missing brackets.	blob \| commitdiff \| raw \| diff to current
2010-09-21	Zheng Bao	Fix the typo. Field DisAutoRefresh is in DramTimngHi.	blob \| commitdiff \| raw \| diff to current
2010-09-09	Arne Georg Gleditsch	Also improve boot time on AMD for the DDR3 code path.	blob \| commitdiff \| raw \| diff to current
2010-09-05	Zheng Bao	Trivial. Currently the max frequency is preset as 400Mh...	blob \| commitdiff \| raw \| diff to current
2010-09-04	Kerry She	AMD DDR2 and DDR3 MCT function InitPhyCompensation...	blob \| commitdiff \| raw \| diff to current
2010-08-31	Zheng Bao	Get Byte65/66 for register manufacture ID code. RegMan1...	blob \| commitdiff \| raw \| diff to current
2010-08-30	Kerry She	Trivial syntax correction of AMD mct_ddr3 dir.	blob \| commitdiff \| raw \| diff to current
2010-04-23	Zheng Bao	DDR3 support for AMD Fam10.	blob \| commitdiff \| raw \| diff to current

my coreboot WIP stuff (asus m5a99x-evo board)