Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED 8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED 8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED 8
-#endif
-
/* global function */
u32 NodePresent(u32 Node);
/* global function */
u32 NodePresent(u32 Node);
yy1b = enable with DctSelIntLvAddr set to yyb */
yy1b = enable with DctSelIntLvAddr set to yyb */
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED 8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED 8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED 8
-#endif
-
-#ifndef MCT_DIMM_SPARE_NO_WARM
-#define MCT_DIMM_SPARE_NO_WARM 0
-#endif
-
-
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
u16 word;
/* Get CPU Si Revision defined limit (NPT) */
u16 word;
/* Get CPU Si Revision defined limit (NPT) */
- proposedFreq = 533; /* Rev F0 programmable max memclock is */
+ proposedFreq = 800; /* Rev F0 programmable max memclock is */
/*Get User defined limit if "limit" mode */
if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
/*Get User defined limit if "limit" mode */
if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
yy1b = enable with DctSelIntLvAddr set to yyb */
yy1b = enable with DctSelIntLvAddr set to yyb */
-#ifndef MAX_NODES_SUPPORTED
-#define MAX_NODES_SUPPORTED 8
-#endif
-
-#ifndef MAX_DIMMS_SUPPORTED
-#define MAX_DIMMS_SUPPORTED 8
-#endif
-
-#ifndef MAX_CS_SUPPORTED
-#define MAX_CS_SUPPORTED 8
-#endif
-
-#ifndef MCT_DIMM_SPARE_NO_WARM
-#define MCT_DIMM_SPARE_NO_WARM 0
-#endif
-
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
u32 Get_NB32(u32 dev, u32 reg);
void Set_NB32(u32 dev, u32 reg, u32 val);
u32 Get_NB32_index(u32 dev, u32 index_reg, u32 index);
#define MAX_CS_SUPPORTED 8
#endif
#define MAX_CS_SUPPORTED 8
#endif
+#ifndef MCT_DIMM_SPARE_NO_WARM
+#define MCT_DIMM_SPARE_NO_WARM 0
+#endif
+
+#ifndef MEM_MAX_LOAD_FREQ
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+ #define MEM_MAX_LOAD_FREQ 800
+#else
+ #define MEM_MAX_LOAD_FREQ 400
+#endif
+#endif
+
#define MCT_TRNG_KEEPOUT_START 0x00000C00
#define MCT_TRNG_KEEPOUT_END 0x00000CFF
#define MCT_TRNG_KEEPOUT_START 0x00000C00
#define MCT_TRNG_KEEPOUT_END 0x00000CFF
//val = 200; /* 200MHz(DDR400) */
//val = 266; /* 266MHz(DDR533) */
//val = 333; /* 333MHz(DDR667) */
//val = 200; /* 200MHz(DDR400) */
//val = 266; /* 266MHz(DDR533) */
//val = 333; /* 333MHz(DDR667) */
- val = 400; /* 400MHz(DDR800) */
+ val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */
break;
case NV_ECC_CAP:
#if SYSTEM_TYPE == SERVER
break;
case NV_ECC_CAP:
#if SYSTEM_TYPE == SERVER
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
- pDCTstat->PresetmaxFreq = 400;
+ pDCTstat->PresetmaxFreq = MEM_MAX_LOAD_FREQ;