cpu/src/decode_stage_b.vhd

   1 library IEEE;
   2
   3 use IEEE.std_logic_1164.all;
   4 use IEEE.numeric_std.all;
   5
   6 use work.mem_pkg.all;
   7 use work.core_pkg.all;
   8 use work.common_pkg.all;
   9
  10
  11 architecture behav of decode_stage is
  12
  13 signal instr_spl : instruction_rec;
  14
  15 signal rtw_rec, rtw_rec_nxt : read_through_write_rec;
  16 signal reg1_mem_data, reg2_mem_data : gp_register_t;
  17
  18 begin
  19
  20         -- register file
  21         register_ram : r2_w_ram
  22                 generic map (
  23                         REG_ADDR_WIDTH,
  24                         WORD_WIDTH
  25                 )
  26
  27                 port map (
  28                         clk,
  29                         reg_w_addr,
  30                         instr_spl.reg_src1_addr,
  31                         instr_spl.reg_src2_addr,
  32                         reg_we,
  33                         reg_wr_data,
  34                         reg1_mem_data,
  35                         reg2_mem_data
  36                 );
  37
  38
  39         decoder_inst : decoder
  40
  41                 port map (
  42                         instruction,
  43                         instr_spl
  44                 );
  45
  46 -- sync process for read through write registers
  47 syn: process(clk, reset)
  48
  49 begin
  50
  51         if (reset = RESET_VALUE) then
  52                 rtw_rec.rtw_reg <= (others => '0');
  53                 rtw_rec.rtw_reg1 <= '0';
  54                 rtw_rec.rtw_reg2 <= '0';
  55         elsif rising_edge(clk) then
  56                 rtw_rec <= rtw_rec_nxt;
  57         end if;
  58
  59 end process;
  60
  61
  62 --      type dec_op is record
  63 --              condition : condition_t;
  64 --              op_group : op_info_t;
  65 --              op_detail : op_opt_t;
  66 --              brpr : std_logic;
  67 --
  68 --              src1 : gp_register_t;
  69 --              src2 : gp_register_t;
  70 --
  71 --              saddr1 : gp_addr_t;
  72 --              saddr2 : gp_addr_t;
  73 --
  74 --              daddr   : gp_addr_t;
  75 --
  76 --      end record;
  77
  78 to_alu: process(instr_spl)
  79
  80 begin
  81
  82
  83 end process;
  84
  85 -- async process: decides between memory and read-through-write buffer on output
  86 output: process(rtw_rec, reg1_mem_data, reg2_mem_data)
  87
  88 begin
  89         if (rtw_rec.rtw_reg1 = '1') then
  90                 reg1_rd_data <= rtw_rec.rtw_reg;
  91         else
  92                 reg1_rd_data <= reg1_mem_data;
  93         end if;
  94
  95         if (rtw_rec.rtw_reg2 = '1') then
  96                 reg2_rd_data <= rtw_rec.rtw_reg;
  97         else
  98                 reg2_rd_data <= reg2_mem_data;
  99         end if;
 100 end process;
 101
 102
 103 -- async process: checks forward condition
 104 forward: process(instr_spl, reg_w_addr, reg_wr_data)
 105
 106 begin
 107
 108         rtw_rec_nxt.rtw_reg <= reg_wr_data;
 109         rtw_rec_nxt.rtw_reg1 <= '0';
 110         rtw_rec_nxt.rtw_reg2 <= '0';
 111
 112         rtw_rec_nxt.immediate <= instr_spl.immediate;
 113
 114         if (reg_w_addr = instr_spl.reg_src1_addr) then
 115                 rtw_rec_nxt.rtw_reg1 <= '1';
 116         end if;
 117
 118         if (reg_w_addr = instr_spl.reg_src2_addr) then
 119                 rtw_rec_nxt.rtw_reg2 <= '1';
 120         end if;
 121
 122 end process;
 123
 124
 125 -- async process: calculates branch prediction
 126 br_pred: process(instr_spl)
 127
 128 begin
 129
 130         branch_prediction_res <= (others => '0');
 131         branch_prediction_bit <= '0';
 132
 133         if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
 134                 branch_prediction_res <= instr_spl.immediate;   --both 32 bit
 135                 branch_prediction_bit <= '1';
 136         end if;
 137
 138 end process;
 139
 140 end behav;
 141