2 use IEEE.std_logic_1164.all;
\r
3 use IEEE.numeric_std.all;
\r
5 use work.common_pkg.all;
\r
6 use work.alu_pkg.all;
\r
8 architecture shift_op of exec_op is
\r
10 signal logic, ls, carry : std_logic;
\r
14 logic <= op_detail(LOG_OPT);
\r
15 ls <= op_detail(LEFT_OPT);
\r
16 carry <= op_detail(CARRY_OPT);
\r
18 calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
\r
19 variable alu_result_v : alu_result_rec;
\r
20 variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
\r
21 variable tmp_sb : std_logic;
\r
23 alu_result_v := alu_state;
\r
26 tmp_sb := (carry and alu_state.status.carry and logic);
\r
27 tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
\r
28 tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
\r
30 alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
\r
33 tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));
\r
34 tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
\r
35 tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
\r
37 alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
\r
40 alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);
\r
42 alu_result <= alu_result_v;
\r
46 end architecture shift_op;
\r