-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.alu_pkg.all;\r
-\r
-architecture add_op of exec_op is\r
-\r
-signal sub, addc : std_logic;\r
-\r
-begin\r
-\r
-sub <= op_detail(SUB_OPT);\r
-addc <= op_detail(CARRY_OPT);\r
-\r
-calc: process(left_operand, right_operand, alu_state, sub, addc)\r
- variable alu_result_v : alu_result_rec;\r
- variable complement : gp_register_t;\r
- variable carry_res : unsigned(gp_register_t'length downto 0);\r
- variable tmp_right_operand : unsigned(gp_register_t'length downto 0);\r
- variable oflo1, oflo2, l_neg, r_neg : std_logic;\r
- variable addcarry : unsigned(carry_res'range);\r
-begin\r
- alu_result_v := alu_state;\r
- \r
- addcarry := (others =>'0');\r
- addcarry(0) := alu_state.status.carry and addc;\r
- \r
- complement := inc(not(right_operand));\r
- l_neg := left_operand(gp_register_t'high);\r
- \r
- carry_res := unsigned('0' & left_operand)+addcarry;\r
- oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));\r
- \r
- if sub = '1' then\r
- tmp_right_operand := unsigned('0' & complement);\r
- else\r
- tmp_right_operand := unsigned('0' & right_operand);\r
- end if;\r
- \r
- l_neg := std_logic_vector(carry_res)(gp_register_t'high);\r
- r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);\r
- \r
- carry_res := carry_res + tmp_right_operand;\r
- oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));\r
- \r
-\r
- alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range);\r
- alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high);\r
- \r
- \r
- alu_result_v.status.carry := oflo1 or oflo2;\r
- \r
- --sign will be set globally.\r
- --zero will be set globally.\r
- \r
- alu_result <= alu_result_v;\r
-end process; \r
-\r
-end architecture add_op;\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.alu_pkg.all;
+
+architecture add_op of exec_op is
+
+signal sub, addc : std_logic;
+
+begin
+
+sub <= op_detail(SUB_OPT);
+addc <= op_detail(CARRY_OPT);
+
+calc: process(left_operand, right_operand, alu_state, sub, addc)
+ variable alu_result_v : alu_result_rec;
+ variable complement : gp_register_t;
+ variable carry_res : unsigned(gp_register_t'length downto 0);
+ variable tmp_right_operand : unsigned(gp_register_t'length downto 0);
+ variable oflo1, oflo2, l_neg, r_neg : std_logic;
+ variable addcarry : unsigned(carry_res'range);
+begin
+ alu_result_v := alu_state;
+
+ addcarry := (others =>'0');
+ addcarry(0) := alu_state.status.carry and addc;
+
+ complement := inc(not(right_operand));
+ l_neg := left_operand(gp_register_t'high);
+
+ carry_res := unsigned('0' & left_operand)+addcarry;
+ oflo1 := add_oflo(l_neg,'0',std_logic_vector(carry_res)(gp_register_t'high));
+
+ if sub = '1' then
+ tmp_right_operand := unsigned('0' & complement);
+ else
+ tmp_right_operand := unsigned('0' & right_operand);
+ end if;
+
+ l_neg := std_logic_vector(carry_res)(gp_register_t'high);
+ r_neg := std_logic_vector(tmp_right_operand)(gp_register_t'high);
+
+ carry_res := carry_res + tmp_right_operand;
+ oflo2 := add_oflo(l_neg,r_neg,std_logic_vector(carry_res)(gp_register_t'high));
+
+
+ alu_result_v.result := std_logic_vector(carry_res)(gp_register_t'range);
+ alu_result_v.status.carry := std_logic_vector(carry_res)(carry_res'high);
+
+
+ alu_result_v.status.carry := oflo1 or oflo2;
+
+ --sign will be set globally.
+ --zero will be set globally.
+
+ alu_result <= alu_result_v;
+end process;
+
+end architecture add_op;