From: Markus Hofstätter Date: Mon, 15 Nov 2010 15:38:38 +0000 (+0100) Subject: gpm module and exec first buggy version. X-Git-Tag: bootrom_v1~132 X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=calu.git;a=commitdiff_plain;h=69ab6e6d8f04511bff27a0a585e45a1645ffbbc2 gpm module and exec first buggy version. --- diff --git a/cpu/src/alu.vhd b/cpu/src/alu.vhd index 8928ece..02401db 100755 --- a/cpu/src/alu.vhd +++ b/cpu/src/alu.vhd @@ -19,7 +19,9 @@ entity alu is right_operand : in gp_register_t; op_detail : in op_opt_t; alu_state : in alu_result_rec; - alu_result : out alu_result_rec + alu_result : out alu_result_rec; + addr : out gp_register_t; + data : out gp_register_t ); end alu; diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd index 511b154..78696f2 100755 --- a/cpu/src/alu_b.vhd +++ b/cpu/src/alu_b.vhd @@ -48,7 +48,8 @@ begin result_v.result := add_result.result; res_prod := '1'; - mem_en := '0'; + mem_en := '0'; + addr <= add_result; case condition is when COND_NZERO => @@ -109,8 +110,10 @@ begin end if; result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met; - result_v.mem_en := mem_en and cond_met; - + result_v.mem_en := mem_en and cond_met; + + + data <= add_result; alu_result <= result_v; end process calc; diff --git a/cpu/src/alu_pkg.vhd b/cpu/src/alu_pkg.vhd index 088565b..8936535 100755 --- a/cpu/src/alu_pkg.vhd +++ b/cpu/src/alu_pkg.vhd @@ -86,7 +86,9 @@ package alu_pkg is right_operand : in gp_register_t; op_detail : in op_opt_t; alu_state : in alu_result_rec; - alu_result : out alu_result_rec + alu_result : out alu_result_rec; + addr : out gp_register_t; + data : out gp_register_t ); end component alu; diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd index 925c579..9ca96bc 100644 --- a/cpu/src/execute_stage.vhd +++ b/cpu/src/execute_stage.vhd @@ -8,14 +8,27 @@ entity execute_stage is -- active reset value RESET_VALUE : std_logic; -- active logic value - LOGIC_ACT : std_logic; + --LOGIC_ACT : std_logic; ); port( --System inputs clk : in std_logic; reset : in std_logic; - dec_instr : in dec_op + dec_instr : in dec_op; + + --System output + result : out gp_register_t;--reg + result_addr : out gp_addr_t;--reg + addr : out word_t; --memaddr + data : out gp_register_t; --mem data --ureg + alu_jump : out std_logic;--reg + brpr : out std_logic; --reg + wr_en : out std_logic;--regop --reg + dmem : out std_logic;--memop + dmem_wr_en : out std_logic; + hword : out std_logic; + byte_s : out std_logic ); end execute_stage; diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd index 095d4dc..080fb00 100644 --- a/cpu/src/execute_stage_b.vhd +++ b/cpu/src/execute_stage_b.vhd @@ -12,28 +12,41 @@ signal op_group : op_info_t; signal op_detail : op_opt_t; signal left_operand, right_operand : gp_register_t; signal alu_state, alu_nxt : alu_result_rec; - signal psw : status_rec; +type exec_internal is record + result : gp_register_t; + res_addr : gp_addr_t; + alu_jump : std_logic; + brpr : std_logic; + wr_en : std_logic; +end record; + +signal reg, reg_nxt : exec_internal; + begin alu_inst : alu port map(clk, reset, condition, op_group, - op_detail, left_operand, right_operand, alu_state, alu_nxt); + op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data); -syn: process(sys_clk, reset) +syn: process(clk, reset) begin - if (reset = RESET_VALUE) then - condition <= - elsif rising_edge(sys_clk) then - + if reset = RESET_VALUE then + reg.alu_jmp <= '0'; + reg.brpr <= '0'; + reg.wr_en <= '0'; + reg.result <= (others =>'0'); + reg.res_addr <= (others => '0'); + elsif rising_edge(clk) then + reg <= reg_nxt; end if; end process; -asyn: process(reset,condition) +asyn: process(reset,dec_instr, alu_nxt, psw) begin condition <= dec_instr.condition; @@ -42,20 +55,33 @@ begin left_operand <= dec_instr.src1; right_operand <= dec_instr.src2; - alu_state.status <= psw; - alu_state.result_addr <= dec_instr.daddr; - alu_state.brpr <= brpr; - alu_state.reg_op <= '0'; - alu_state.mem_op <= '0'; - alu_state. + + alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); + if reset = RESET_VALUE then condition <= COND_NEVER; else end if; + + reg_nxt.brpr <= alu_nxt.brpr; + reg_nxt.alu_jump <= alu_nxt.alu_jump; + reg_nxt.wr_en <= alu_nxt.reg_op; + reg_nxt.result <= alu_nxt.result; + reg_nxt.reg_addr <= alu_nxt.result_addr; end process asyn; +result <= reg.result; +result_addr <= reg.res_addr; +alu_jmp <= reg.alu_jump; +brbr <= reg.brpr; +wr_en <= reg.wr_en; +dmem <= alu_nxt.mem_op; +dmem_write_en <= alu_nxt.mem_en; +hword <= alu_nxt.hw_op; +byte_s <= alu_nxt.byte_op; + end behav; diff --git a/cpu/src/gpm.vhd b/cpu/src/gpm.vhd index 7bba400..428bdbb 100644 --- a/cpu/src/gpm.vhd +++ b/cpu/src/gpm.vhd @@ -12,7 +12,7 @@ entity gpm is -- active reset value RESET_VALUE : std_logic; -- active logic value - LOGIC_ACT : std_logic + --LOGIC_ACT : std_logic ); port( @@ -20,7 +20,7 @@ entity gpm is clk : in std_logic; reset : in std_logic; - exti : in extmod_rec; + --exti : in extmod_rec; --alu outpus alu_nxt : in alu_result_rec; --input @@ -28,12 +28,12 @@ entity gpm is --output psw : out status_rec; --to memcnt - addr : out gp_register_t; - mem_en : out std_logic; - ldst : out std_logic; + --addr : out gp_register_t; + --mem_en : out std_logic; + --ldst : out std_logic; --, hw,byte: std_logic; --to output bus - exto : out data_ram_word_t + --exto : out data_ram_word_t ); diff --git a/cpu/src/gpm_b.vhd b/cpu/src/gpm_b.vhd new file mode 100644 index 0000000..0818304 --- /dev/null +++ b/cpu/src/gpm_b.vhd @@ -0,0 +1,63 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.common_pkg.all; +use work.alu_pkg.all; + +entity gpm is + + generic ( + -- active reset value + RESET_VALUE : std_logic; + -- active logic value + --LOGIC_ACT : std_logic + + ); + port( + --System inputs + clk : in std_logic; + reset : in std_logic; + + --exti : in extmod_rec; + --alu outpus + alu_nxt : in alu_result_rec; + --input + + --output + psw : out status_rec; + --to memcnt + --addr : out gp_register_t; + --mem_en : out std_logic; + --ldst : out std_logic; + --, hw,byte: std_logic; + --to output bus + --exto : out data_ram_word_t + + ); + +end gpm; + +architecture behaviour of gpm is +type gpm_internal is record + status : status_rec; +end record gpm_internal; + +reg, reg_nxt : gpm_internal; + +begin +syn : process (clk, reset) + if reset = RESET_VALUE then + reg <= (('0','0','0','0')); + elsif rising_edge(clk) then + reg <= reg_nxt; + end if; +end process syn; + +asyn : process (clk, reset) + reg_nxt <= alu_nxt.status; +end process asyn; + +psw <= reg; + +end architecture behaviour;