cpu/src/execute_stage_b.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 use work.common_pkg.all;
   6 use work.alu_pkg.all;
   7
   8 architecture behav of execute_stage is
   9
  10 signal condition : condition_t;
  11 signal op_group : op_info_t;
  12 signal op_detail : op_opt_t;
  13 signal left_operand, right_operand : gp_register_t;
  14 signal alu_state, alu_nxt : alu_result_rec;
  15 signal psw : status_rec;
  16
  17 type exec_internal is record
  18         result : gp_register_t;
  19         res_addr : gp_addr_t;
  20         alu_jump : std_logic;
  21         brpr    : std_logic;
  22         wr_en   : std_logic;
  23 end record;
  24
  25 signal reg, reg_nxt : exec_internal;
  26
  27 begin
  28
  29 alu_inst : alu
  30 port map(clk, reset, condition, op_group,
  31         op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data);
  32
  33 syn: process(clk, reset)
  34
  35 begin
  36
  37         if reset = RESET_VALUE then
  38                 reg.alu_jmp <= '0';
  39                 reg.brpr <= '0';
  40                 reg.wr_en <= '0';
  41                 reg.result <= (others =>'0');
  42                 reg.res_addr <= (others => '0');
  43         elsif rising_edge(clk) then
  44                 reg <= reg_nxt;
  45         end if;
  46
  47 end process;
  48
  49 asyn: process(reset,dec_instr, alu_nxt, psw)
  50 begin
  51
  52         condition <= dec_instr.condition;
  53         op_group <= dec_instr.op_group;
  54         op_detail <= dec_instr.op_detail;
  55         left_operand <= dec_instr.src1;
  56         right_operand <= dec_instr.src2;
  57
  58
  59         alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0');
  60
  61
  62         if reset = RESET_VALUE then
  63                 condition <= COND_NEVER;
  64         else
  65
  66         end if;
  67
  68         reg_nxt.brpr <= alu_nxt.brpr;
  69         reg_nxt.alu_jump <= alu_nxt.alu_jump;
  70         reg_nxt.wr_en <= alu_nxt.reg_op;
  71         reg_nxt.result <= alu_nxt.result;
  72         reg_nxt.reg_addr <= alu_nxt.result_addr;
  73
  74 end process asyn;
  75
  76 result <= reg.result;
  77 result_addr <= reg.res_addr;
  78 alu_jmp <= reg.alu_jump;
  79 brbr <= reg.brpr;
  80 wr_en <= reg.wr_en;
  81 dmem <= alu_nxt.mem_op;
  82 dmem_write_en <= alu_nxt.mem_en;
  83 hword <= alu_nxt.hw_op;
  84 byte_s <= alu_nxt.byte_op;
  85
  86 end behav;
  87