begin
+<<<<<<< HEAD
+ arith <= op_detail(ARITH_OPT);
+ rs <= op_detail(RIGHT_OPT);
+=======
logic <= op_detail(ARITH_OPT);
ls <= op_detail(RIGHT_OPT);
+>>>>>>> 05fc0d5300956fef107bbb8507a6480ee11695ff
carry <= op_detail(CARRY_OPT);
-calc: process(left_operand, right_operand, logic,ls, carry, alu_state)
+calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
variable alu_result_v : alu_result_rec;
variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
variable tmp_sb : std_logic;
- begin
+begin
alu_result_v := alu_state;
- if ls = '1' then
- tmp_sb := (carry and alu_state.status.carry and logic);
- tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
- tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
-
- alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
-
- else
- tmp_sb := (carry and alu_state.status.carry and logic) or (not(logic) and left_operand(gp_register_t'high));
+ if rs = '1' then
+ tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
+ else
+ tmp_sb := (carry and alu_state.status.carry and not(arith));
+ tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
+ tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
+
+ alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
end if;
alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);