2 use IEEE.std_logic_1164.all;
3 use IEEE.numeric_std.all;
5 use work.common_pkg.all;
8 architecture shift_op of exec_op is
10 signal logic, ls, carry : std_logic;
15 arith <= op_detail(ARITH_OPT);
16 rs <= op_detail(RIGHT_OPT);
18 logic <= op_detail(ARITH_OPT);
19 ls <= op_detail(RIGHT_OPT);
20 >>>>>>> 05fc0d5300956fef107bbb8507a6480ee11695ff
21 carry <= op_detail(CARRY_OPT);
23 calc: process(left_operand, right_operand, arith,rs, carry, alu_state)
24 variable alu_result_v : alu_result_rec;
25 variable tmp_shift : bit_vector(gp_register_t'length+1 downto 0);
26 variable tmp_sb : std_logic;
28 alu_result_v := alu_state;
31 tmp_sb := (carry and alu_state.status.carry and not(arith)) or (arith and left_operand(gp_register_t'high));
32 tmp_shift := to_bitvector(tmp_sb & left_operand & alu_state.status.carry);
33 tmp_shift := tmp_shift sra to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
35 alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(0);
37 tmp_sb := (carry and alu_state.status.carry and not(arith));
38 tmp_shift := to_bitvector(alu_state.status.carry & left_operand & tmp_sb);
39 tmp_shift := tmp_shift sla to_integer(unsigned(right_operand)(SHIFT_WIDTH-1 downto 0));
41 alu_result_v.status.carry := to_stdlogicvector(tmp_shift)(tmp_shift'high);
44 alu_result_v.result := to_stdlogicvector(tmp_shift)(gp_register_t'length downto 1);
46 alu_result <= alu_result_v;
50 end architecture shift_op;