Jordan Crouse [Tue, 20 May 2008 20:10:49 +0000 (20:10 +0000)]
libpayload: Add an exec() and i386_do_exec() function
Add functions for libpayload to execute other payloads in memory,
and have those functions return cleanly.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3338
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 20 May 2008 20:09:42 +0000 (20:09 +0000)]
libpayload: Add larfptr function
Add a function to get a pointer to the start of a LAR entry.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3337
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 20 May 2008 20:08:11 +0000 (20:08 +0000)]
libpayload: Fix curses subwindows
This fixes subwindows in curses so that they draw and refresh correctly.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3336
2b7e53f0-3cfb-0310-b3e9-
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Corey Osgood [Tue, 20 May 2008 18:10:24 +0000 (18:10 +0000)]
Add post-RAM init code for the Fintek
F71805F Super I/O.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Richard Stellingwerff <remenic@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3335
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Aaron Lwe [Mon, 19 May 2008 12:17:43 +0000 (12:17 +0000)]
Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R.
This also contains various improvements of the CN700 code in svn.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334
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Uwe Hermann [Sat, 17 May 2008 21:33:35 +0000 (21:33 +0000)]
Initial support for the Intel 82845 (Brookdale) and ICH2 (trivial).
Tested on hardware:
Intel Northbridge: 8086:1a30 (i845)
Intel Southbridge: 8086:2440 (ICH2)
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3333
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Nikolay Petukhov [Sat, 17 May 2008 01:08:58 +0000 (01:08 +0000)]
flashrom: Support Pm49FL004/2 Block Locking Registers
The PMC chips understand both LPC and FWH flash commands. When in FWH mode
(MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block
Locking Registers by default lock the flash chip for write and erase - in
addition to any chipset write protection.
This patch adds unlock operations before Pm49FL004/2 write and erase, and
it includes an svn mv pm49fl004.c pm49fl00x.c
Thanks go to Nikolay for this patch.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Bari Ari <bari@onelabs.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332
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Carl-Daniel Hailfinger [Fri, 16 May 2008 21:11:53 +0000 (21:11 +0000)]
I looked at the datasheet and erase_sector_39sf020() is totally and
completely wrong. It was a straight cut'n'paste from SST 28SF040 code
and the person doing the cut'n'paste didn't even bother to check the
data sheet. The SST 39SF020 is completely incompatible with the 28SF040.
No need for replacement. According to the data sheet, standard JEDEC
commands will work and we have those commands in the tree already.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3331
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Uwe Hermann [Fri, 16 May 2008 18:56:24 +0000 (18:56 +0000)]
Doesn't have to be executable (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3330
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Marc Jones [Fri, 16 May 2008 18:08:54 +0000 (18:08 +0000)]
Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329
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Joseph Smith [Fri, 16 May 2008 15:43:35 +0000 (15:43 +0000)]
New Target and initial support for the Thomson IP1000.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328
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Carl-Daniel Hailfinger [Fri, 16 May 2008 14:39:39 +0000 (14:39 +0000)]
ICH8 and ICH9 have an almost identical SPI interface, only the location
of the SPIBAR differs. Add ICH8 support to the ICH9 code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3327
2b7e53f0-3cfb-0310-b3e9-
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Dominik Geyer [Fri, 16 May 2008 13:00:28 +0000 (13:00 +0000)]
Add support for the Atmel AT25DF321 SPI flash (tested).
Change ST M25P32 status to tested.
Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3326
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Dominik Geyer [Fri, 16 May 2008 12:55:55 +0000 (12:55 +0000)]
Add support for SPI chips on ICH9. This is done by using the generic SPI
interface.
Signed-off-by: Dominik Geyer <dominik.geyer@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3325
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Carl-Daniel Hailfinger [Fri, 16 May 2008 00:19:52 +0000 (00:19 +0000)]
Enable IT8716F LPC-to-SPI write cycle translation in flashrom if the
IT8716F decodes any address to the attached SPI ROM.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324
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Carl-Daniel Hailfinger [Thu, 15 May 2008 22:32:08 +0000 (22:32 +0000)]
Print detailed status register information for SST25VF series flash.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3323
2b7e53f0-3cfb-0310-b3e9-
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Joseph Smith [Thu, 15 May 2008 13:44:33 +0000 (13:44 +0000)]
This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322
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Carl-Daniel Hailfinger [Thu, 15 May 2008 03:24:43 +0000 (03:24 +0000)]
Lots of new SST flash chip IDs. Only a subset has been added to
flashchips.c, but the IDs in flash.h will make lookups easier if anybody
wants to add support for them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321
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Carl-Daniel Hailfinger [Thu, 15 May 2008 03:19:49 +0000 (03:19 +0000)]
Add support for the JEDEC RES (Read Electronic Signature and Resume from
Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320
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Uwe Hermann [Wed, 14 May 2008 22:56:47 +0000 (22:56 +0000)]
Some NSC Super I/Os can have their config port at 0x15c (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3319
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Uwe Hermann [Wed, 14 May 2008 21:20:55 +0000 (21:20 +0000)]
Cosmetics, whitespace, coding style, partially ident-aided (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3318
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Jordan Crouse [Wed, 14 May 2008 20:10:02 +0000 (20:10 +0000)]
libpayload: implement wborder function
Implement the wborder function for curses to draw a box around a window.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3317
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Wed, 14 May 2008 20:07:31 +0000 (20:07 +0000)]
libpayload: Fix the putc function
Reverse rows and columns on the video putc() function, and watch printf
work again.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3316
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Stefan Reinauer [Wed, 14 May 2008 20:05:00 +0000 (20:05 +0000)]
add ICH7-M and ICH7 DH to inteltool (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3315
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Carl-Daniel Hailfinger [Wed, 14 May 2008 14:51:22 +0000 (14:51 +0000)]
Add more infrastructure for flashrom ICH9 support.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3314
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Stefan Reinauer [Wed, 14 May 2008 14:47:32 +0000 (14:47 +0000)]
fix license mentioning in manpage (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3313
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Stefan Reinauer [Wed, 14 May 2008 14:22:59 +0000 (14:22 +0000)]
trivial patch: move maintainable parts to the top and add ICH7-M DH southbridge
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3312
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Stefan Reinauer [Wed, 14 May 2008 13:52:50 +0000 (13:52 +0000)]
trivial patch to fix options. Thanks to Uwe Hermann for the hint!
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3311
2b7e53f0-3cfb-0310-b3e9-
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Claus Gindhart [Wed, 14 May 2008 12:22:38 +0000 (12:22 +0000)]
Add the Intel 6300ESB as known chipset to the chipset struct enables.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3310
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Carl-Daniel Hailfinger [Wed, 14 May 2008 12:09:31 +0000 (12:09 +0000)]
Fix crash caused by division by zero for unknown flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3309
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Carl-Daniel Hailfinger [Wed, 14 May 2008 12:03:06 +0000 (12:03 +0000)]
Check the JEDEC vendor ID for correct parity. Flash chips which can be
detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308
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Stefan Reinauer [Wed, 14 May 2008 11:38:22 +0000 (11:38 +0000)]
Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7
have different register meanings, so they get their own lookup tables.
This is a trivial patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307
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Carl-Daniel Hailfinger [Wed, 14 May 2008 04:27:02 +0000 (04:27 +0000)]
Add lots of ATMEL SPI flash chips to flash.h.
Add a few flashchips already mentioned in flash.h to flashchips.c
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306
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Carl-Daniel Hailfinger [Tue, 13 May 2008 23:03:12 +0000 (23:03 +0000)]
flashrom: Move all IT87xx specific SPI routines from spi.c to a separate
file it87spi.c.
No behavioural changes, but greatly improved SPI abstraction.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305
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Stefan Reinauer [Tue, 13 May 2008 22:14:21 +0000 (22:14 +0000)]
Add new revised inteltool that dumps all kinds of chipset information and drop old
gpio_dump utility.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Tue, 13 May 2008 21:29:48 +0000 (21:29 +0000)]
This is a trivial patch which fixes the tint build by removing the extra
typedef for time_t. The other half bumps the tint patch revision in buildrom
to take advantage of it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3303
2b7e53f0-3cfb-0310-b3e9-
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Carl-Daniel Hailfinger [Tue, 13 May 2008 14:58:23 +0000 (14:58 +0000)]
flashrom: Move the SPI #defines from spi.c to spi.h
This patch has no code changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302
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Carl-Daniel Hailfinger [Tue, 13 May 2008 14:01:22 +0000 (14:01 +0000)]
Change the SPI parts of flashrom to prepare for a merge of
ICH9 SPI support. In theory, this patch has no behaviour changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301
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Carl-Daniel Hailfinger [Mon, 12 May 2008 21:19:53 +0000 (21:19 +0000)]
MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OK
by Harald Gutmann.
SST39VF040 has been confirmed to probe OK by misi e.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300
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Carl-Daniel Hailfinger [Mon, 12 May 2008 14:25:31 +0000 (14:25 +0000)]
Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LF
series has the same IDs.
Add short AMIC vendor ID to flashrom.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299
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Uwe Hermann [Sun, 11 May 2008 16:13:24 +0000 (16:13 +0000)]
Fix the build when serial console support is disabled (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3298
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Uwe Hermann [Sun, 11 May 2008 15:51:31 +0000 (15:51 +0000)]
Quickfix to repair 'make clean; make menuconfig' (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3297
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Carl-Daniel Hailfinger [Sat, 10 May 2008 23:40:51 +0000 (23:40 +0000)]
Improve flashrom SPI abstraction, second step.
This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.
The third step would be calling SPI controller functions via a function
pointer.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296
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Peter Stuge [Sat, 10 May 2008 23:07:52 +0000 (23:07 +0000)]
flashrom: Rename generic_spi_*() functions to spi_*()
This is a very early step toward cleaning up SPI code in flashrom.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295
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Jordan Crouse [Fri, 9 May 2008 15:32:46 +0000 (15:32 +0000)]
coreboot-v2: Disable second serial port on Norwich
There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294
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Uwe Hermann [Thu, 8 May 2008 14:37:12 +0000 (14:37 +0000)]
Add support for dumping ITE IT8718F EC registers (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3293
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Uwe Hermann [Thu, 8 May 2008 13:50:23 +0000 (13:50 +0000)]
Don't split up register list in two blocks, otherwise "Register dump:"
will be printed twice in the output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292
2b7e53f0-3cfb-0310-b3e9-
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Claus Gindhart [Thu, 8 May 2008 00:31:44 +0000 (00:31 +0000)]
flashrom: Probe for up to 3 flash chips.
Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
For this reason some boards have multiple chips of different technologies
onboard. This patch makes flashrom probe for up to 3 chips and if more than
one chip is found flashrom exits, asking the user to specify -c.
[root@localhost src]# ./flashrom
...
Multiple flash chips were detected: SST49LF008A M25P16@ICH9
Please specify which chip to use with the -c <chipname> option.
[root@localhost src]#
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Claus Gindhart <claus.gindhart@kontron.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291
2b7e53f0-3cfb-0310-b3e9-
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Ed Swierk [Wed, 7 May 2008 21:57:12 +0000 (21:57 +0000)]
Implement GPIO configuration routines for the Intel 3100 southbridge,
allowing you to specify per-mainboard GPIO settings.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Wed, 7 May 2008 20:43:15 +0000 (20:43 +0000)]
coreinfo: Add a module for browsing the boot LAR
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3289
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Wed, 7 May 2008 20:34:02 +0000 (20:34 +0000)]
libpayload: Add LAR walking support
Add suport for walking LARs. These try to emulate the f*
functions from POSIX, though they are obviously different
in their behavior.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3288
2b7e53f0-3cfb-0310-b3e9-
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Ed Swierk [Wed, 7 May 2008 19:21:18 +0000 (19:21 +0000)]
Fix a typo in lbtdump output (trivial).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ed Swierk <eswierk@arastra.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 6 May 2008 22:15:31 +0000 (22:15 +0000)]
coreinfo: Show the current time and date in the menu
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3286
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 6 May 2008 22:03:16 +0000 (22:03 +0000)]
We were in the risk of running out of space in the option menu at
the bottom of the screen - this turns the function keys into
categories and then list specific items as part of the category.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3285
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 6 May 2008 22:00:55 +0000 (22:00 +0000)]
The previous commit had more in it then I wanted - so I am reverting
this and re-commiting so that the history and comments are correct.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3284
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Tue, 6 May 2008 21:32:52 +0000 (21:32 +0000)]
coreinfo: Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFO
rdtsc.h shouldn't be included unless we really need it (and use it).
Trivial.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3283
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 6 May 2008 16:56:47 +0000 (16:56 +0000)]
cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a
pci_write_config8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Tue, 6 May 2008 15:17:43 +0000 (15:17 +0000)]
This patch changes Config-lab.lb for qemu to use lzma like the other targets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281
2b7e53f0-3cfb-0310-b3e9-
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Aaron Lwe [Tue, 6 May 2008 15:02:22 +0000 (15:02 +0000)]
This patch adds pc keyboard init function call for qemu in v2 since some payloads assume
Coreboot initializes it. Coreboot v3 already does it.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280
2b7e53f0-3cfb-0310-b3e9-
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Jonathan A. Kollasch [Tue, 6 May 2008 13:26:32 +0000 (13:26 +0000)]
Fix various issues on MSI MS-7135 board.
- W83627THF is strapped to 0x4e, not 0x2e
- there's no device 9 on PCI-E x1 bus, it should be device 0
- add mptable entries for AGR slot, based on info in user manual
- enable floppy drive controller so that some legacy VGA ROMs will work
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279
2b7e53f0-3cfb-0310-b3e9-
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Ward Vandewege [Mon, 5 May 2008 20:50:58 +0000 (20:50 +0000)]
This patch changes the payload path for Config.lb; this board is supported by
buildrom and this bit was forgotten during r3092.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Sat, 3 May 2008 04:34:37 +0000 (04:34 +0000)]
flashrom: Add a tested bitmap field to the flash chip table.
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.
All chips are TEST_UNTESTED for now.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277
2b7e53f0-3cfb-0310-b3e9-
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Ed Swierk [Wed, 30 Apr 2008 18:29:35 +0000 (18:29 +0000)]
By default, the Intel 3100 LPC interface enables only I/O range 0x3f8
for both serial ports, making it challenging to use COM2 for the early
console.
Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276
2b7e53f0-3cfb-0310-b3e9-
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Bari Ari [Tue, 29 Apr 2008 13:46:38 +0000 (13:46 +0000)]
flashrom: Enable ROM decode range to 1MB for vt8237r
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275
2b7e53f0-3cfb-0310-b3e9-
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Claus Gindhart [Mon, 28 Apr 2008 17:51:09 +0000 (17:51 +0000)]
The generic jedec.c does not work for the ST M50FLW flash
devices, because they need an unlock command first.
For this reason, ST M50FLW support is moved to a
new HW support module, because any change in jedec.c
would bear the risk to cause problems with the already
supported devices.
It's already tested with ST M50FLW080A; the other
chips of this family i dont have available, so i couldnt
test it.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 28 Apr 2008 14:47:30 +0000 (14:47 +0000)]
flashrom: Handle NULL probe, erase and write function pointers in the
flashchips table. The read pointer was already checked properly.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Fri, 25 Apr 2008 23:11:02 +0000 (23:11 +0000)]
libpayload: Add gettimeofday() and friends
Add a gettimeofday() implementation - it works pretty well, but it
drifts a little bit so its not very suitable for keeping time. It
works best to track changes in time over small periods of time.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3272
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jordan Crouse [Fri, 25 Apr 2008 23:10:23 +0000 (23:10 +0000)]
libpayload: Fix a small but aggressive bug in printf()
This was causing the returned counter value to be one more then it
should be when printing a single character.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3271
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Fri, 25 Apr 2008 23:09:39 +0000 (23:09 +0000)]
libpayload: Enable keyboard translation so that we can use scancode set 1
The qemu keyboard controller defaults to using scancode set 2, we use set 1.
Turn on the translate mode in the keyboard controller to force the issue.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3270
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Fri, 25 Apr 2008 23:08:47 +0000 (23:08 +0000)]
libpayload: Fix malloc allocation
Apparently the previous version worked on luck. Fix the allocation
and add parens to better guide the compiler. Also, halt() if
the heap is poisoned (like by an overrun). Finally, fix calloc()
so that it actually works.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3269
2b7e53f0-3cfb-0310-b3e9-
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Jordan Crouse [Fri, 25 Apr 2008 23:07:39 +0000 (23:07 +0000)]
libpayload: Add the null terminator to the end of the duplicated string
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3268
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Fri, 25 Apr 2008 22:56:57 +0000 (22:56 +0000)]
Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb.
The FAM10 code takes up more space in the uncompressed "ROMCC" portion
of coreboot. Also, It is still growing as features are added.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Fri, 25 Apr 2008 21:34:25 +0000 (21:34 +0000)]
Remove inline from FAM10 CPU initialization functions.
This doesn't save any space for me but it is the right thing to allow GCC to
optimize.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266
2b7e53f0-3cfb-0310-b3e9-
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Aaron Lwe [Fri, 25 Apr 2008 02:02:33 +0000 (02:02 +0000)]
Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Fri, 25 Apr 2008 00:38:41 +0000 (00:38 +0000)]
Payload location fix for buildrom (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3264
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Thu, 24 Apr 2008 20:03:13 +0000 (20:03 +0000)]
Add CPUID processor name string support for Fam10 CPUs.
Peter did a nice job cleaning up my initial patch. Thanks!
Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Thu, 24 Apr 2008 19:49:59 +0000 (19:49 +0000)]
On APs the ClLinesToNbDis was being left enabled from CAR setup.
Disabling it should help performance.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262
2b7e53f0-3cfb-0310-b3e9-
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Nikolay Petukhov [Thu, 24 Apr 2008 13:37:01 +0000 (13:37 +0000)]
This board (ieiworld.com/en/product_IPC.asp?model=PCISA-LX)
is based on amd-lx800/cs5536.
Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261
2b7e53f0-3cfb-0310-b3e9-
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Claus Gindhart [Thu, 24 Apr 2008 09:07:57 +0000 (09:07 +0000)]
Flash pages, which where excluded from updating using the exclude or the
layout option, as well as areas, whose flash contents already contain the
desired data, will be skipped.
These ensures absolute data security of critical areas (BIOS boot block),
e.g. against a sudden power off or a CPU hangup during flashing. As a
nice side effect, it speeds up the flash process, if the BIOS to be flashed
is very similar to the version in flash.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260
2b7e53f0-3cfb-0310-b3e9-
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Carl-Daniel Hailfinger [Wed, 23 Apr 2008 22:54:40 +0000 (22:54 +0000)]
Same old story: Fam10 needs more space again. My calculations say it
needs 172 more bytes, give it 512 and hope that's enough for a while.
Trivial.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3259
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Wed, 23 Apr 2008 22:01:55 +0000 (22:01 +0000)]
Trivial payload location changes for buildrom.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3258
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Wed, 23 Apr 2008 21:06:08 +0000 (21:06 +0000)]
These config files are so that buildrom can use these two boards.
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3257
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Wed, 23 Apr 2008 20:40:55 +0000 (20:40 +0000)]
This is the sata irq patch for s2895 and ultra40. It also changes some broken
white space in the s2892 and s2891 mptable.c files.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Wed, 23 Apr 2008 17:55:25 +0000 (17:55 +0000)]
Fix irqs for secondary ports on both sata controllers.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3255
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Wed, 23 Apr 2008 09:27:18 +0000 (09:27 +0000)]
Detect SMSC SCH5027 (trivial).
This chip seems to be very similar to the SMSC DME1737, for coreboot
purposes it might even work without any code changes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3254
2b7e53f0-3cfb-0310-b3e9-
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Ward Vandewege [Wed, 23 Apr 2008 00:40:39 +0000 (00:40 +0000)]
This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.
Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.
While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 22 Apr 2008 23:32:56 +0000 (23:32 +0000)]
Clean up and remove late initialization code that is no longer needed.
Pstate intialization has moved to early init because it requires a warm reset.
Add CPUID setup and disable SMM access to late initialization.
Much of this code is leftover from porting from K8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 22 Apr 2008 23:27:53 +0000 (23:27 +0000)]
Find matching settings for each CPUs FID, VID, and P-state registers and initialize them.
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).
The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 22 Apr 2008 23:20:07 +0000 (23:20 +0000)]
Update the FAM10 microcode to current versions.
In addition, AP microcode is now updated in early initialization to support errata settings that require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 22 Apr 2008 23:09:34 +0000 (23:09 +0000)]
Missed this file in the previous check-in, r3248.
Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Tue, 22 Apr 2008 22:11:31 +0000 (22:11 +0000)]
Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 22 Apr 2008 20:19:53 +0000 (20:19 +0000)]
Add support for a 'bootlog' module to coreinfo.
It displays the coreboot printk buffer in RAM and let's you scroll through it.
This feature is only available for coreboot v3 though, as v2 doesn't have a
printk-buffer feature, yet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3247
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Uwe Hermann [Tue, 22 Apr 2008 16:56:21 +0000 (16:56 +0000)]
Show index numbers in the NVRAM dump, similar to the PCI config space dump.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3246
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Jordan Crouse [Mon, 21 Apr 2008 22:33:58 +0000 (22:33 +0000)]
libpayload: Fix keyboard buglet
This solves the multiple keystroke issue that popped up recently.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3245
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Christopher Kilgour [Sat, 19 Apr 2008 13:32:19 +0000 (13:32 +0000)]
This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the
generic SMSC support, and corrects a small typo.
With this patch, coreboot v2 on a mainboard with SCH3112 has been
demonstrated to correctly use the serial port. No other chip
functions were tested.
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3244
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Ed Swierk [Fri, 18 Apr 2008 20:48:22 +0000 (20:48 +0000)]
Replace buildtarget's check for --build-id with something
a bit less awkward (pun intended).
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3243
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Ed Swierk [Fri, 18 Apr 2008 20:47:11 +0000 (20:47 +0000)]
Alter buildtarget to invoke the cross-compiler when
checking for --build-id, if the user has specified one by setting CC
in the environment; there's no point in checking the native linker in
this case.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3242
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Uwe Hermann [Wed, 16 Apr 2008 00:46:08 +0000 (00:46 +0000)]
Change default payload location for easier buildrom support (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3241
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Uwe Hermann [Tue, 15 Apr 2008 17:24:08 +0000 (17:24 +0000)]
Move curses/speaker.c to drivers/ as it's not curses-specific (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3240
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Uwe Hermann [Tue, 15 Apr 2008 16:47:20 +0000 (16:47 +0000)]
Add the patch for building tint as payload, as well as a small README,
into the payloads/external/tint directory.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3239
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