Add early MSR and PCI register initialization.
authorMarc Jones <marc.jones@amd.com>
Tue, 22 Apr 2008 22:11:31 +0000 (22:11 +0000)
committerMarc Jones <marc.jones@amd.com>
Tue, 22 Apr 2008 22:11:31 +0000 (22:11 +0000)
commitda4ce6b45157060447cb02fa15349f7de3f531ff
treeb2b8c34dbff559f715f7832f59a6703a6870625c
parent0ab8cddf02f592a34f3c555ba78a11eaf66a59c0
Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_10xxx/init_cpus.c
src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
src/northbridge/amd/amdfam10/raminit_amdmct.c
src/northbridge/amd/amdht/AsPsDefs.h
src/northbridge/amd/amdht/ht_wrapper.c
src/northbridge/amd/amdmct/amddefs.h