#define PCI_DEVICE_ID_INTEL_ICH0 0x2420
#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
+#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
#define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
} supported_chips_list[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_ICH7:
+ case PCI_DEVICE_ID_INTEL_ICH7M:
+ case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = ich7_gpio_registers;
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_ICH7:
+ case PCI_DEVICE_ID_INTEL_ICH7M:
+ case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break;
switch (sb->device_id) {
case PCI_DEVICE_ID_INTEL_ICH7:
+ case PCI_DEVICE_ID_INTEL_ICH7M:
+ case PCI_DEVICE_ID_INTEL_ICH7DH:
case PCI_DEVICE_ID_INTEL_ICH7MDH:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
break;