Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all
authorMarc Jones <marc.jones@amd.com>
Fri, 16 May 2008 18:08:54 +0000 (18:08 +0000)
committerMarc Jones <marc.jones@amd.com>
Fri, 16 May 2008 18:08:54 +0000 (18:08 +0000)
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/db800/Config.lb
src/mainboard/digitallogic/msm800sev/Config.lb
src/mainboard/iei/pcisa-lx-800-r10/Config.lb
src/mainboard/pcengines/alix1c/Config.lb

index bdc109369f1241cddc548a45760fde1d55cc1b55..2c0cce3e1ea1ffd27500e185ef42b94ea809c636 100644 (file)
@@ -127,8 +127,8 @@ chip northbridge/amd/lx
                        # IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
                        # SIRQ Mode = Active(Quiet) mode. Save power....
                        # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-                       register "lpc_serirq_enable" = "0x000010da"
-                       register "lpc_serirq_polarity" = "0x0000EF25"
+                       register "lpc_serirq_enable" = "0x0000105a"
+                       register "lpc_serirq_polarity" = "0x0000EFA5"
                        register "lpc_serirq_mode" = "1"
                        register "enable_gpio_int_route" = "0x0D0C0700"
                        register "enable_ide_nand_flash" = "0"  # 0:ide mode, 1:flash
index 84db58bb425d85a296b4fdbc2f2cddb66501044d..eceee5bf49e6b533f06d9995d239c5517558dc07 100644 (file)
@@ -128,9 +128,9 @@ chip northbridge/amd/lx
                        # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
                        # How to get these? Boot linux and do this:
                        # rdmsr 0x51400025
-                       register "lpc_serirq_enable" = "0x000010da"
+                       register "lpc_serirq_enable" = "0x0000105a"
                        # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
-                       register "lpc_serirq_polarity" = "0x0000EF25"
+                       register "lpc_serirq_polarity" = "0x0000EFA5"
                        # mode is high 10 bits (determined from code)
                        register "lpc_serirq_mode" = "1"
                        # Don't yet know how to find this.
index 7c89aaffcaafede5443417b69e2e6f27b2fd73fc..87aa03d741565450004f59f21732cac1d771e942 100644 (file)
@@ -78,8 +78,8 @@ chip northbridge/amd/lx
                        # IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
                        # SIRQ Mode = Active(Quiet) mode. Save power....
                        # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-                       register "lpc_serirq_enable" = "0x000010da"
-                       register "lpc_serirq_polarity" = "0x0000EF25"
+                       register "lpc_serirq_enable" = "0x0000105a"
+                       register "lpc_serirq_polarity" = "0x0000EFA5"
                        register "lpc_serirq_mode" = "1"
                        register "enable_gpio_int_route" = "0x0D0C0700"
                        register "enable_ide_nand_flash" = "0"  # 0:ide mode, 1:flash
index c78587851bb49c434fb9b7c7822bc0b2ebae962b..73a1875280303927404c7b7f49cc6d4e3693eda8 100644 (file)
@@ -148,9 +148,9 @@ chip northbridge/amd/lx
                        # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
                        # How to get these? Boot linux and do this:
                        # rdmsr 0x51400025
-                       register "lpc_serirq_enable" = "0x000010da"
+                       register "lpc_serirq_enable" = "0x0000105a"
                        # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
-                       register "lpc_serirq_polarity" = "0x0000EF25"
+                       register "lpc_serirq_polarity" = "0x0000EFA5"
                        # mode is high 10 bits (determined from code)
                        register "lpc_serirq_mode" = "1"
                        # Don't yet know how to find this.