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(parent: da4ce6b) | patch
Missed this file in the previous check-in, r3248.
authorMarc Jones <marc.jones@amd.com>
Tue, 22 Apr 2008 23:09:34 +0000 (23:09 +0000)
committerMarc Jones <marc.jones@amd.com>
Tue, 22 Apr 2008 23:09:34 +0000 (23:09 +0000)
commitc74e3627233558c62e93beb37efa271f0f353f8d
tree05b9e5780cf75275dbffd1f2c42b79bccf7eea58tree | snapshot
parentda4ce6b45157060447cb02fa15349f7de3f531ffcommit | diff
Missed this file in the previous check-in, r3248.

Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_10xxx/defaults.h [new file with mode: 0644] blob
my coreboot WIP stuff (asus m5a99x-evo board)