+ to_next_stage <= dec_op_inst;
+ to_next_stage.src1 <= reg1_rd_data;
+ to_next_stage.src2 <= reg2_rd_data;
+
+end process;
+
+
+-- fills output register
+to_next: process(instr_spl)
+
+begin
+ dec_op_inst_nxt.condition <= instr_spl.predicates;
+ dec_op_inst_nxt.op_detail <= instr_spl.op_detail;
+ dec_op_inst_nxt.brpr <= instr_spl.bp; --branch_prediction_bit;
+ dec_op_inst_nxt.src1 <= (others => '0');
+ dec_op_inst_nxt.src2 <= (others => '0');
+ dec_op_inst_nxt.saddr1 <= instr_spl.reg_src1_addr;
+ dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
+ dec_op_inst_nxt.daddr <= (others => '0');