- -- next state
- process(state_int, opcode, done_intern, error_intern, do_calc, div_go_calc_int)
- begin
- -- set a default value for next state
- state_next <= state_int;
- -- next state berechnen
- case state_int is
- when SIDLE =>
- if do_calc = '1' then
- case opcode is
- when ALU_ADD => state_next <= SADD;
- when ALU_SUB => state_next <= SSUB;
- when ALU_MUL => state_next <= SMUL;
- when ALU_DIV => state_next <= SDIV;
- when others => state_next <= SIDLE;
- end case;
- end if;
- when SADD | SSUB | SMUL | SDIV | SDIV_CALC =>
- case state_int is
- when SDIV =>
- if div_go_calc_int = '1' then
- state_next <= SDIV_CALC;
- end if;
- when others => null;
- end case;
- if done_intern = '1' then
- state_next <= SDONE;
- end if;
- if error_intern = '1' then
- state_next <= SERROR;
- end if;
- when SDONE | SERROR =>
- if do_calc = '0' then
- state_next <= SIDLE;
+ -- next state & out
+ process(opcode, do_calc, state_int, op1, op2, dividend_msb_int,
+ laengediv_int, quo_int, aktdiv_int, sign_int, op1_int, op2_int,
+ op3_int, opM_int)
+ -- http://www.velocityreviews.com/forums/showpost.php?p=137148&postcount=5
+ function find_msb(a : std_logic_vector) return std_logic_vector is
+ function bits_to_fit(n : positive) return natural is
+ variable nn, bits : natural := 0;
+ begin
+ nn := n;
+ while nn > 0 loop
+ bits := bits + 1;
+ nn := nn/2;
+ end loop;
+ return bits;
+ end;
+
+ function or_all(p : std_logic_vector) return std_logic is
+ variable r : std_logic;
+ begin
+ r := '0';
+ for i in p'range loop
+ r := r or p(i);
+ end loop;
+ return r;
+ end;
+
+ constant wN : positive := bits_to_fit(a'length - 1);
+ constant wP : positive := 2 ** wN;
+ variable pv : std_logic_vector(wP-1 downto 0);
+ variable n : std_logic_vector(wN downto 1);
+ begin
+ if a'length <= 2 then
+ n(n'right) := a(a'left);
+ else
+ pv(a'length-1 downto 0) := a;
+ if or_all(pv(wP-1 downto wP/2)) = '1' then
+ n := '1' & find_msb((pv(wP-1 downto wP/2)));
+ else
+ n := '0' & find_msb((pv(wP/2-1 downto 0)));